WO2015066955A1 - 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 - Google Patents
一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 Download PDFInfo
- Publication number
- WO2015066955A1 WO2015066955A1 PCT/CN2013/090289 CN2013090289W WO2015066955A1 WO 2015066955 A1 WO2015066955 A1 WO 2015066955A1 CN 2013090289 W CN2013090289 W CN 2013090289W WO 2015066955 A1 WO2015066955 A1 WO 2015066955A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- sio
- growth
- substrate structure
- buffer layer
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000000737 periodic effect Effects 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 44
- 229910052594 sapphire Inorganic materials 0.000 claims description 16
- 239000010980 sapphire Substances 0.000 claims description 16
- 238000009616 inductively coupled plasma Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 10
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 238000010992 reflux Methods 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 230000008901 benefit Effects 0.000 description 6
- 238000000605 extraction Methods 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 238000009776 industrial production Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
- H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
Definitions
- This invention relates to the field of semiconductor illumination, and more particularly to a substrate structure for III-V nitride growth and a method of fabricating the same. Background technique
- semiconductor lighting As a new high-efficiency solid-state light source, semiconductor lighting has significant advantages such as long life, energy saving, environmental protection and safety. It will become another leap after the incandescent lamp and fluorescent lamp in the history of human lighting. Its application field is rapidly expanding, which is driving traditional lighting and display. The upgrading of the industry and other industries has huge economic and social benefits. For this reason, semiconductor lighting is widely regarded as one of the most promising emerging industries in the 21st century, and one of the most important commanding heights in the field of optoelectronics in the next few years.
- the light-emitting diode is made of a III-V compound such as Ga As (gallium arsenide), GaP (gallium phosphide), or GaAsP (phosphorus gallium arsenide), and its core is a PN junction. Therefore, it has the I-N characteristics of the general P-N junction, namely forward conduction, reverse cutoff, and breakdown characteristics. In addition, it has luminescent properties under certain conditions. At the forward voltage, electrons are injected into the P region from the N region, and holes are injected into the N region from the P region. A minority carrier (small child) entering the other region is combined with a majority carrier (multiple) to emit light.
- a III-V compound such as Ga As (gallium arsenide), GaP (gallium phosphide), or GaAsP (phosphorus gallium arsenide)
- the existing light-emitting diodes generally use sapphire as a preparation substrate.
- a plurality of convex structures periodically arranged on the surface of the sapphire substrate are prepared, and then a GaN-based light-emitting epitaxial structure is prepared.
- the sapphire substrate with a convex structure the direct deposition of the GaN light-emitting epitaxial structure often brings huge crystal defects, which seriously affects the brightness of the light-emitting diode. Therefore, the existing preparation process is preceded by 1100°.
- the surface of the sapphire substrate having a convex structure is subjected to H 2 reduction treatment, and then a reaction source is introduced, and a low temperature G aN layer is deposited on the surface of the sapphire substrate by low temperature chemical vapor deposition, and then the reaction source is stopped. And heating up to about 1050 °C to recombine the low-temperature GaN layer on the surface of the sapphire substrate to form a nucleation site of the GaN-based light-emitting epitaxial structure, and finally depositing a GaN-based light-emitting epitaxial structure to complete the subsequent light-emitting diode preparation.
- the process is complicated, and the cost is high, and the refractive index of the sapphire substrate is relatively high, about 1.8, even on the surface thereof.
- the raised structure also has a great limitation on the improvement of the light-emitting rate of the light-emitting diode.
- an object of the present invention is to provide a substrate structure for III-V nitride growth and a method for fabricating the same, which are used to solve the growth quality and light emission rate of a light emitting diode in the prior art. Low question.
- the present invention provides a method of fabricating a substrate structure for III-V nitride growth, comprising at least the following steps:
- the material of the growth substrate is one of sapphire, SiC, Si, and ZnO.
- the buffer layer has a thickness of 50 to 400 angstroms.
- the buffer layer is a low temperature Al x G ai _ x N layer prepared by low temperature chemical vapor deposition. 0 ⁇ X ⁇ 0.5, the temperature range of preparation is 450 ⁇ 700 °C.
- the buffer layer is an A1N layer prepared by a sputtering method, and a main crystal orientation of the A1N layer is (0001) Orientation.
- the buffer layer is a BN material layer.
- step 2) forming a SiO 2 layer on the surface of the buffer layer by plasma enhanced chemical vapor deposition.
- the thickness of the SiO 2 layer of the step 2) is 0.2 to 2 ⁇ m.
- a preferred method of the method for fabricating a substrate structure for III-V nitride growth of the present invention 5 ⁇ 3 ⁇
- the plurality of Si0 2 protrusions are arranged at a periodic interval, the width of the Si0 2 protrusion is 1 ⁇ 4 ⁇ , the pitch is 0. 5 ⁇ 3 ⁇ .
- the SiO 2 protrusion of the step 3) is a Si0 2 clad protrusion, and a Si0 2 conical protrusion. Or Si0 2 pyramid-like projections.
- the SiO 2 protrusion is a SiO 2 packet-like protrusion, and the step 3) includes the following steps:
- the present invention also provides a substrate structure for group III-V nitride growth, comprising at least: a growth substrate; a buffer layer for subsequent growth of the epitaxial structure, bonded to the surface of the growth substrate; The Si0 2 protrusions are spaced apart from the surface of the buffer layer.
- the material of the growth substrate is one of sapphire, SiC, Si, and ZnO.
- the buffer layer has a thickness of 50 to 400 angstroms.
- the buffer layer is a (0001) crystal orientation A1N layer; or an Al x G ai _ x N layer, wherein, 0 ⁇ X ⁇ 0.5; or BN material layer.
- the height of the SiO 2 protrusion is 0.2 to 3 ⁇ m.
- the plurality of S00 2 protrusions are arranged at periodic intervals, and the width of the Si0 2 protrusion is 1 to 4 ⁇ m, pitch It is 0.5 ⁇ 2 ⁇ .
- the SiO 2 bump is a Si0 2 clad bump, a Si0 2 conical bump or a Si0 2 pyramid bump.
- the present invention provides a substrate structure for III-V nitride growth and a method of fabricating the same, the method of manufacturing comprising the steps of: 1) providing a growth substrate on a surface of the growth substrate Forming a buffer layer for subsequent growth of the epitaxial structure; 2) forming a layer of Si0 2 on the surface of the buffer layer; 3) passing light The etching process etches the Si0 2 layer into a plurality of Si0 2 protrusions arranged at intervals, and exposes a buffer layer between the Si0 2 protrusions.
- the invention first prepares a BN material layer or an AlN layer or an Al x G ai _ x N layer containing a hexagonal lattice structure as a buffer layer for luminescent epitaxial structure growth, and then passes through a photoresist reflow process and ICP etching. The process produces periodically arranged packet-shaped SiO 2 protrusions.
- the invention can not only ensure the crystal quality of the growth luminescent epitaxial structure, but also improve the light extraction efficiency of the light emitting diode.
- the invention has simple process, is beneficial to reduce manufacturing cost, and is suitable for industrial production.
- 1 to 2 are schematic views showing the structure of the method for fabricating a III-V nitride grown substrate structure according to the present invention.
- Fig. 3 is a view showing the structure of the step 2) of the method for fabricating a III-V nitride grown substrate of the present invention.
- 4 to 7 are diagrams showing the steps of the manufacturing method of the substrate structure for III-V nitride growth of the present invention.
- this embodiment provides a method for fabricating a substrate structure for III-V nitride growth, comprising at least the following steps:
- step 1) is first performed to provide a growth substrate 101, and a buffer layer 102 for growth of a subsequent luminescent epitaxial structure is formed on the surface of the growth substrate 101.
- the material of the growth substrate 101 is one of sapphire, SiC, Si, and ZnO.
- the growth substrate 101 is a flat-plate type sapphire substrate whose surface is a flat surface.
- the buffer layer 102 is a low temperature Al x G ai _ x N layer (0 ⁇ X ⁇ 0.5) prepared by low temperature chemical vapor deposition, preferably a low temperature Al x G ai _ x N layer (0 ⁇ X ⁇ 0.2) The temperature range is 450 ⁇ 700 °C.
- the preparation temperature of the low temperature Al x Ga ⁇ N layer (0 ⁇ X ⁇ 0.5) is 500 °C
- the low temperature Al x Ga ⁇ N layer (0 ⁇ X ⁇ 0.5) is a low temperature GaN layer. Or AlfuGa ⁇ N layer, etc.
- the buffer layer 102 has a thickness of 50 to 400 angstroms. In this embodiment, the buffer layer 102 has a thickness of 200 angstroms.
- the thickness range exemplified herein is the most preferable range. In other embodiments, the thickness of the buffer layer 102 can be selected according to actual needs, and is not limited thereto.
- the thickness required to be prepared is smaller, and the luminescent growth of the subsequent luminescent epitaxial structure (especially the GaN-based luminescent epitaxial structure) can be effectively performed. reduce manufacturing cost.
- step 2) is then performed to form a SiO 2 layer 103 on the surface of the buffer layer 102.
- the SiO 2 layer 103 is formed on the surface of the buffer layer 102 by plasma enhanced chemical vapor deposition.
- the SiO 2 layer 103 can be prepared by any of the preparation methods contemplated, and is not limited to the ones listed herein.
- the SiO 2 layer 103 has a thickness of 0.2 to 3 ⁇ m. In this embodiment, the thickness of the SiO 2 layer 103 is 1 ⁇ m.
- step 3 the SiO 2 layer 103 is etched out of the plurality of Si0 2 bumps 107 arranged by a photolithography process, and each of the Si0 2 bumps 107 is exposed. Inter buffer layer 102.
- the plurality of SiO 2 protrusions 107 are arranged at periodic intervals, and the width of the Si0 2 protrusions 107 It is 1 ⁇ 4 ⁇ , and the pitch is 0.5 ⁇ 2 ⁇ .
- the SiO 2 protrusions 107 have a period of 3 ⁇ m, a width of 2 ⁇ m, and a pitch of 1 ⁇ m.
- the SiO 2 protrusions 107 are Si0 2 clad protrusions.
- the relatively smooth Si0 2 clad protrusion can effectively improve the growth quality of the subsequent luminescent epitaxial structure (especially the GaN-based luminescent epitaxial structure).
- the SiO 2 protrusions 107 may be a Si0 2 conical protrusion, a Si0 2 pyramid protrusion, or the like, and are not limited thereto.
- step 3 includes the following steps:
- step 3-1) is first performed to form a photoresist layer 104 on the surface of the SiO 2 layer 103, and the photoresist layer 104 is formed into a plurality of spaced intervals by an exposure process.
- Photoresist block 105 In this embodiment, the plurality of photoresist blocks 105 have a rectangular parallelepiped shape.
- step 3-2) is then performed to reflow the plurality of photoresist blocks 105 into a plurality of package-shaped photoresist blocks 106 by a heat reflow process.
- step 3-3) is performed, and the shape of each of the packet-shaped photoresist blocks 106 is transferred to the SiO 2 layer 103 by inductively coupled plasma etching to form a plurality of Si0 2 packages.
- a bump is formed, and a buffer layer 102 between each of the Si0 2 bumps is exposed for growth of a subsequent GaN-based light-emitting epitaxial structure.
- different photoresist shapes such as a cone shape, a pyramid shape, etc., can be produced by different processes, and a Si0 2 conical protrusion, a Si0 2 pyramidal protrusion, and the like can be prepared as a mask layer.
- the refractive index of Si0 2 is generally 1.3 to 1.4, which is larger than that of the sapphire substrate 101, the light extraction rate of the GaN-based light emitting diode can be effectively improved.
- the embodiment further provides a substrate structure for III-V nitride growth, comprising at least: a growth substrate 101; a buffer layer 102 for subsequent growth of the epitaxial structure, combined with the growth a substrate surface; and a plurality of SiO 2 protrusions 107 spaced apart from the surface of the buffer layer 102.
- the material of the growth substrate 101 is one of sapphire, SiC, Si, and ZnO.
- the growth substrate 101 is a sapphire substrate.
- the buffer layer 102 is an Al x G ai — x N layer, where 0 ⁇ X ⁇ 0.5.
- the buffer layer 102 has a thickness of 50 to 400 angstroms; and the SiO 2 protrusions 107 have a height of 0.2 to 3 ⁇ m.
- the plurality of SiO 2 protrusions 107 are arranged at periodic intervals, and the Si0 2 protrusions 107 have a width of 1 to 4 ⁇ m and a pitch of 0.5 to 2 ⁇ m.
- the SiO 2 protrusions 107 are Si0 2 clad protrusions, Si0 2 conical protrusions or Si0 2 gold characters. Tower-like projections.
- Example 2
- the present embodiment provides a method for fabricating a substrate structure for III-V nitride growth, the basic steps of which are as in Embodiment 1, wherein the buffer layer 102 is splashed.
- the A IN layer prepared by the sputtering method, the crystal orientation or the main crystal orientation of the A1N layer is (0001) orientation.
- the advantage of the A1N layer prepared by sputtering is that the thickness is controllable and the orientation orientation is high, and it is also advantageous for the luminescent epitaxial structure (especially the GaN-based luminescent epitaxial structure). ) nucleation growth.
- this embodiment further provides a substrate structure for III-V nitride growth, the basic structure of which is as in Embodiment 1, wherein the buffer layer 102 is a (0001) crystal orientation A1N.
- the layer or (0001) is the A1N layer of the main crystal orientation.
- the present embodiment provides a method for fabricating a substrate structure for III-V nitride growth, the basic steps of which are as in Embodiment 1, wherein the buffer layer 102 is a BN material.
- the layer can be prepared by sputtering or the like.
- the present embodiment further provides a substrate structure for III-V nitride growth, the basic structure of which is as in Embodiment 1, wherein the buffer layer 102 is a BN material layer.
- the present invention provides a substrate structure for III-V nitride growth and a method of fabricating the same, the manufacturing method comprising the steps of: 1) providing a growth substrate, The growth substrate surface forms a buffer layer for subsequent luminescence epitaxial structure growth; 2) forming a SiO 2 layer on the surface of the buffer layer; 3) etching the SiO 2 layer by a photolithography process to align a plurality of Si0s arranged at intervals 2 protrusions, and exposing a buffer layer between each of the Si 0 2 protrusions.
- the invention first prepares a BN material layer or an A1N layer or an Al x G ai _ x N layer containing a hexagonal lattice structure as a buffer layer for luminescent epitaxial structure growth, and then passes through a photoresist reflow process and ICP etching. The process produces periodically arranged packet-shaped SiO 2 protrusions.
- the invention can not only ensure the crystal quality of the growth luminescent epitaxial structure, but also improve the light extraction efficiency of the light emitting diode.
- the invention has simple process, is beneficial to reduce manufacturing cost, and is suitable for industrial production. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Led Devices (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
一种用于Ⅲ-V族氮化物生长的衬底结构和制造方法。制造方法包括以下步骤:1)提供一生长衬底(101),在生长衬底表面形成用于后续发光外延结构生长的缓冲层(102);2)在缓冲层表面形成SiO2层(103);3)通过光刻工艺将SiO2层刻蚀出间隔排列的多个SiO2凸起(107),且暴露出SiO2凸起之间的缓冲层。使用含有六角晶格结构的BN材料层、AlN层或AlxGa1—xN层作为缓冲层,然后通过光刻胶的加热回流工艺和ICP刻蚀工艺制备出周期性排列的包装SiO2凸起,既能保证生长发光外延结构的晶体质量,又能提高发光二极管的出光效率。
Description
一种用于 III-V族氮化物生长的衬底结构及其制备方法
技术领域
本发明涉及半导体照明领域, 特别是涉及一种用于 III- V族氮化物生长的衬底 结构及其制造方法。 背景技术
半导体照明作为新型高效固体光源, 具有寿命长、 节能、 环保、 安全等显著优 点, 将成为人类照明史上继白炽灯、 荧光灯之后的又一次飞跃, 其应用领域正在迅 速扩大, 正带动传统照明、 显示等行业的升级换代, 其经济效益和社会效益巨大。 正因如此, 半导体照明被普遍看作是 21世纪最具发展前景的新兴产业之一, 也是 未来几年光电子领域最重要的制高点之一。发光二极管是由 III-V族化合物, 如 Ga As (砷化镓) 、 GaP (磷化镓) 、 GaAsP (磷砷化镓) 等半导体制成的, 其核心是 PN结。 因此它具有一般 P-N结的 I-N特性, 即正向导通, 反向截止、 击穿特性。 此外, 在一定条件下, 它还具有发光特性。 在正向电压下, 电子由 N区注入 P区, 空穴由 P区注入 N区。 进入对方区域的少数载流子 (少子) 一部分与多数载流子 (多子) 复合而发光。
现有的发光二极管一般采用蓝宝石作为制备衬底,为了提高发光二极管的出光 效率, 会于蓝宝石衬底表面制备出周期排列的多个凸起结构, 然后再制备 GaN基 发光外延结构。 然而, 具有凸起结构的蓝宝石衬底, 直接进行 GaN发光外延结构 的沉积往往会带来巨大的晶体缺陷, 严重影响发光二极管的亮度, 因此, 现有的一 种制备过程是, 先于 1100°C左右对具有凸起结构的蓝宝石衬底表面进行 H2还原处 理, 然后通入反应源, 采用低温化学气相沉积法于蓝宝石衬底表面沉积一层低温 G aN层,接着停止反应源的通入, 并升温至 1050°C左右使该层低温 GaN层在蓝宝石 衬底表面的平台上进行重组, 形成 GaN基发光外延结构的成核位置, 最后开始沉 积 GaN基发光外延结构, 完成后续发光二极管的制备。
对于以上的发光二极管制备方法, 需要多步才能形成 GaN基发光外延结构的 成核位置, 工艺复杂, 成本较高, 而且, 蓝宝石衬底的折射率较高, 为 1.8左右, 即使于其表面形成凸起结构, 对发光二极管的出光率的提升也有很大的限制。
因此, 提供一种可以有效提高 GaN基发光二极管生长质量、 并且能提高发光
二极管出光率的制备方法实属必要。 发明内容
鉴于以上所述现有技术的缺点, 本发明的目的在于提供一种用于 III- V族氮化 物生长的衬底结构及其制造方法,用于解决现有技术中发光二极管生长质量及出光 率低等问题。
为实现上述目的及其他相关目的, 本发明提供一种用于 III- V族氮化物生长的 衬底结构的制造方法, 至少包括以下步骤:
1 ) 提供一生长衬底, 于所述生长衬底表面形成用于后续发光外延结构生长的 缓冲层;
2) 于所述缓冲层表面形成 Si02层;
3)通过光刻工艺将所述 Si02层刻蚀出间隔排列的多个 Si02凸起,且露出各该 Si02凸起之间的缓冲层。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 所述生长衬底的材料为蓝宝石、 SiC、 Si及 ZnO的一种。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的的一种优选方 案, 所述缓冲层的厚度为 50〜400埃。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 所述缓冲层为采用低温化学气相沉积法所制备的低温 AlxGai_xN层, 0≤X≤0.5, 制备的温度范围为 450〜700°C。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 所述缓冲层为采用溅射法所制备的 A1N层, 所述 A1N层的主要晶向为 (0001 ) 取向。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 所述缓冲层为 BN材料层。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 步骤 2) 采用等离子体增强化学气相沉积法于所述缓冲层表面形成 Si02层。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 步骤 2) 所述的 Si02层的厚度为 0.2〜2μηι。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方
案, 所述多个 Si02凸起呈周期性间隔排列, Si02凸起的宽度为 1〜4μηι, 间距为 0. 5〜3μηι。
作为本发明的用于 III- V族氮化物生长的衬底结构的制造方法的一种优选方 案, 步骤 3) 所述的 Si02凸起为 Si02包状凸起、 Si02圆锥状凸起或 Si02金字塔状 凸起。
进一步地, 所述 Si02凸起为 Si02包状凸起, 步骤 3) 包括以下步骤:
3-1 ) 于所述 Si02层表面形成光刻胶层, 通过曝光工艺将所述光刻胶层制作成 间隔排列的多个光刻胶块;
3-2) 通过加热回流工艺使所述多个光刻胶块回流成多个包状的光刻胶块;
3-3 )采用感应耦合等离子体刻蚀法将各该包状的光刻胶块的形状转移至所述 S i02层, 形成多个 Si02包状凸起, 且露出各该 Si02包状凸起之间的缓冲层, 用于后 续 GaN基发光外延结构的成核生长。
本发明还提供一种用于 III-V族氮化物生长的衬底结构, 至少包括: 生长衬底; 用于后续发光外延结构生长的缓冲层, 结合于所述生长衬底表面; 以及多个 Si02 凸起, 间隔排列于所述缓冲层表面。
作为本发明的用于 III- V族氮化物生长的衬底结构的一种优选方案, 所述生长 衬底的材料为蓝宝石、 SiC、 Si及 ZnO的一种。
作为本发明的用于 III- V族氮化物生长的衬底结构的一种优选方案, 所述缓冲 层的厚度为 50〜400埃。
作为本发明的用于 III- V族氮化物生长的衬底结构的一种优选方案, 所述缓冲 层为 (0001 ) 晶向的 A1N层; 或 AlxGai_xN层, 其中, 0≤X≤0.5; 或 BN材料层。
作为本发明的用于 III-V族氮化物生长的衬底结构的一种优选方案, 所述 Si02 凸起的高度为 0.2〜3μηι。
作为本发明的用于 III-V族氮化物生长的衬底结构的一种优选方案,所述多个 S i02凸起呈周期性间隔排列, Si02凸起的宽度为 1〜4μηι, 间距为 0.5〜2μηι。
作为本发明的用于 III-V族氮化物生长的衬底结构的一种优选方案, 所述 Si02 凸起为 Si02包状凸起、 Si02圆锥状凸起或 Si02金字塔状凸起。
如上所述, 本发明提供一种用于 III-V族氮化物生长的衬底结构及其制造方法, 所述制造方法包括以下步骤: 1 ) 提供一生长衬底, 于所述生长衬底表面形成用于 后续发光外延结构生长的缓冲层; 2) 于所述缓冲层表面形成 Si02层; 3) 通过光
刻工艺将所述 Si02层刻蚀出间隔排列的多个 Si02凸起,且露出各该 Si02凸起之间 的缓冲层。 本发明先制备一层含有六角晶格结构的 BN材料层或 A1N层或 AlxGai_x N层, 作为发光外延结构生长的缓冲层, 然后通过光刻胶的加热回流工艺和 ICP刻 蚀工艺制备出周期性排列的包状的 Si02凸起。 本发明既能保证生长发光外延结构 的晶体质量, 又能提高发光二极管的出光效率。 本发明工艺简单, 有利于降低制造 成本, 适用于工业生产。 附图说明
图 1〜图 2显示为本发明的用于 III-V族氮化物生长的衬底结构的制造方法步骤 1 ) 所呈现的结构示意图。
图 3显示为本发明的用于 III- V族氮化物生长的衬底结构的制造方法步骤 2)所 呈现的结构示意图。
图 4〜图 7显示为本发明的用于 III-V族氮化物生长的衬底结构的制造方法步骤 3) 所呈现的结构示意图 元件标号说明
101 生长衬底
102 缓冲层
103 Si02层
104 光刻胶层
105 光刻胶块
106 包状的光刻胶块
107 Si02凸起 具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明 书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同 的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应 用, 在没有背离本发明的精神下进行各种修饰或改变。
请参阅图 1〜图 7。需要说明的是,本实施例中所提供的图示仅以示意方式说明
本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的 组件数目、 形状及尺寸绘制, 其实际实施时各组件的型态、数量及比例可为一种随 意的改变, 且其组件布局型态也可能更为复杂。 实施例 1
如图 1〜图 7所示, 本实施例提供一种用于 III-V族氮化物生长的衬底结构的制 造方法, 至少包括以下步骤:
如图 1〜图 2所示, 首先进行步骤 1 ) , 提供一生长衬底 101, 于所述生长衬底 101表面形成用于后续发光外延结构生长的缓冲层 102。
作为示例, 所述生长衬底 101的材料为蓝宝石、 SiC、 Si及 ZnO的一种。 在本 实施例中, 所述生长衬底 101为平片型蓝宝石衬底, 其表面为平直面。所述缓冲层 102为采用低温化学气相沉积法所制备的低温 AlxGai_xN层 (0≤X≤0.5 ), 优选为低 温 AlxGai_xN层 (0≤X≤0.2), 制备的温度范围为 450〜700°C。 在本实施例中, 所述 低温 AlxGa^N层 (0≤X≤0.5 ) 的制备温度为 500 °C, 所述低温 AlxGa^N层 (0≤X≤ 0.5 ) 为低温 GaN层或 AlfuGa^N层等。
作为示例, 所述缓冲层 102的厚度为 50〜400埃。 在本实施例中, 所述缓冲层 102的厚度为 200埃。 当然, 此处所列举的厚度范围为最优选的范围, 在其它的实 施例中, 所述缓冲层 102的厚度可以根据实际需求进行选择, 并不限定于此。
由于所述低温 AlxGai_xN层制备的温度较低, 所需制备的厚度较小, 在保证后 续发光外延结构 (尤其是 GaN基发光外延结构) 成核生长的同时, 可以有效地降 低生产成本。
如图 3所示, 然后进行步骤 2) , 于所述缓冲层 102表面形成 Si02层 103。 在本实施例中,采用等离子体增强化学气相沉积法于所述缓冲层 102表面形成 Si02层 103。 当然, 在其它的实施例中, 所述 Si02层 103可以采用预期的一切制备 方法进行制备, 并不限定于此处所列举的一种。
作为示例, 所述的 Si02层 103的厚度为 0.2〜3μηι。 在本实施例中, 所述 Si02 层 103的厚度为 1μηι。
如图 4〜图 7所示, 最后进行步骤 3 ) , 通过光刻工艺将所述 Si02层 103刻蚀 出间隔排列的多个 Si02凸起 107, 且露出各该 Si02凸起 107之间的缓冲层 102。
作为示例, 所述多个 Si02凸起 107呈周期性间隔排列, Si02凸起 107的宽度
为 1〜4μηι, 间距为 0.5〜2μηι。 在本实施例中, 所述 Si02凸起 107的周期为 3μηι, 宽度为 2μηι, 间距为 1μηι。
作为示例, 所述的 Si02凸起 107为 Si02包状凸起。表面较平缓的 Si02包状凸 起可以有效提高后续发光外延结构 (尤其是 GaN基发光外延结构) 的生长质量。 当然, 在其它的实施例中, 所述 Si02凸起 107也可以为 Si02圆锥状凸起、 Si02金 字塔状凸起等, 并不限定于此。
具体地, 步骤 3 ) 包括以下步骤:
如图 4〜图 5所示, 首先进行步骤 3-1 ), 于所述 Si02层 103表面形成光刻胶层 104, 通过曝光工艺将所述光刻胶层 104制作成间隔排列的多个光刻胶块 105。 在 本实施例中, 所述多个光刻胶块 105为长方体状。
如图 6所示, 然后进行步骤 3-2) , 通过加热回流工艺使所述多个光刻胶块 10 5回流成多个包状的光刻胶块 106。
如图 7所示, 最后进行步骤 3-3 ) , 采用感应耦合等离子体刻蚀法将各该包状 的光刻胶块 106的形状转移至所述 Si02层 103, 形成多个 Si02包状凸起, 且露出 各该 Si02包状凸起之间的缓冲层 102, 用于后续 GaN基发光外延结构的生长。 当 然, 通过不同的工艺可以制作出不同的光刻胶形状, 如圆锥状、 金字塔状等, 以此 为掩膜层可制备出 Si02圆锥状凸起、 Si02金字塔状凸起等。
由于 Si02的折射率一般为 1.3〜1.4, 相比于蓝宝石衬底 101有较大的降低, 因 此, 可以有效提高 GaN基发光二极管的出光率。
如图 Ί所示, 本实施例还提供一种用于 III-V族氮化物生长的衬底结构, 至少 包括: 生长衬底 101 ; 后续发光外延结构生长的缓冲层 102, 结合于所述生长衬底 表面; 以及多个 Si02凸起 107, 间隔排列于所述缓冲层 102表面。
作为示例, 所述生长衬底 101的材料为蓝宝石、 SiC、 Si及 ZnO的一种。 在本 实施例中, 所述生长衬底 101为蓝宝石衬底。
在本实施例中, 所述缓冲层 102为 AlxGai_xN层, 其中, 0≤X≤0.5。
作为示例, 所述缓冲层 102的厚度为 50〜400埃; 所述 Si02凸起 107的高度为 0.2〜3μηι。
作为示例, 所述多个 Si02凸起 107呈周期性间隔排列, Si02凸起 107的宽度 为 1〜4μηι, 间距为 0.5〜2μηι。
作为示例, 所述 Si02凸起 107为 Si02包状凸起、 Si02圆锥状凸起或 Si02金字
塔状凸起。 实施例 2
如图 1〜图 7所示, 本实施例提供一种用于 III-V族氮化物生长的衬底结构的制 造方法, 其基本步骤如实施例 1, 其中, 所述缓冲层 102为采用溅射法所制备的 A IN层,所述 A1N层的晶向或者主要晶向为( 0001 )取向。相比于低温 AlxGai_xN层, 溅射法制备 A1N层的好处是厚度可控性强、 晶向取向度较高, 同时也有利于发光 外延结构 (尤其是 GaN基发光外延结构) 的成核生长。
如图 7所示, 本实施例还提供一种用于 III-V族氮化物生长的衬底结构, 其基 本结构如实施例 1, 其中, 所述缓冲层 102为 (0001 ) 晶向的 A1N层或 (0001 ) 为 主要晶向的 A1N层。 实施例 3
如图 1〜图 7所示, 本实施例提供一种用于 III-V族氮化物生长的衬底结构的制 造方法, 其基本步骤如实施例 1, 其中, 所述缓冲层 102为 BN材料层, 可以采用 溅射等方法制备。
如图 7所示, 本实施例还提供一种用于 III-V族氮化物生长的衬底结构, 其基 本结构如实施例 1, 其中, 所述缓冲层 102为 BN材料层。 如上所述, 如上所述, 本发明提供一种用于 III-V族氮化物生长的衬底结构及 其制造方法, 所述制造方法包括以下步骤: 1 ) 提供一生长衬底, 于所述生长衬底 表面形成用于后续发光外延结构生长的缓冲层; 2)于所述缓冲层表面形成 Si02层; 3 ) 通过光刻工艺将所述 Si02层刻蚀出间隔排列的多个 Si02凸起, 且露出各该 Si 02凸起之间的缓冲层。 本发明先制备一层含有六角晶格结构的 BN材料层或 A1N 层或 AlxGai_xN层, 作为发光外延结构生长的缓冲层, 然后通过光刻胶的加热回流 工艺和 ICP刻蚀工艺制备出周期性排列的包状的 Si02凸起。 本发明既能保证生长 发光外延结构的晶体质量, 又能提高发光二极管的出光效率。 本发明工艺简单, 有 利于降低制造成本, 适用于工业生产。 所以, 本发明有效克服了现有技术中的种种 缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效, 而非用于限制本发明。任何
熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或 改变。 因此, 举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与 技术思想下所完成的一切等效修饰或改变, 仍应由本发明的权利要求所涵盖。
Claims
权利要求书 、 一种用于 III-V族氮化物生长的衬底结构的制造方法, 其特征在于, 至少包括 以下步骤:
1 )提供一生长衬底,于所述生长衬底表面形成用于后续发光外延结构生 长的缓冲层;
2) 于所述缓冲层表面形成 Si02层;
3 )通过光刻工艺将所述 Si02层刻蚀出间隔排列的多个 Si02凸起, 且露 出各该 Si02凸起之间的缓冲层。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于: 所述生长衬底的材料为蓝宝石、 SiC、 Si及 ZnO的一种。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于: 所述缓冲层的厚度为 50〜400埃。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于:所述缓冲层为采用化学气相沉积法所制备的 AlxGai_xN层, 0≤X≤0.5, 制备的温度范围为 450〜700°C。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于: 所述缓冲层为采用溅射法所制备的 A1N层, 所述 A1N层的晶向为
(0001 ) 取向。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于: 所述缓冲层为 BN材料层。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于: 步骤 2) 采用等离子体增强化学气相沉积法于所述缓冲层表面形成 Si02层。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特
征在于: 步骤 2) 所述的 Si02层的厚度为 0.2〜3μηι。 、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法,其特 征在于: 所述多个 Si02凸起呈周期性间隔排列, Si02凸起的宽度为 1〜4μηι, 间距为 0.5〜2μηι。 0、 根据权利要求 1所述的用于 III-V族氮化物生长的衬底结构的制造方法, 其特征在于: 步骤 3 )所述的 Si02凸起为 Si02包状凸起、 Si02圆锥状凸起或 Si02金字塔状凸起。 1、 根据权利要求 10所述的用于 III- V族氮化物生长的衬底结构的制造方法, 其特征在于: 所述 Si02凸起为 Si02包状凸起, 步骤 3 ) 包括以下步骤:
3-1 ) 于所述 Si02层表面形成光刻胶层, 通过曝光工艺将所述光刻胶层 制作成间隔排列的多个光刻胶块;
3-2 ) 通过加热回流工艺使所述多个光刻胶块回流成多个包状的光刻胶 块;
3-3 )采用感应耦合等离子体刻蚀法将各该包状的光刻胶块的形状转移至 所述 Si02层,形成多个 Si02包状凸起,且露出各该 Si02包状凸起之间的缓冲 层, 用于后续发光外延结构的生长。 、 一种用于 III-V族氮化物生长的衬底结构, 其特征在于, 至少包括:
生长衬底;
用于后续发光外延结构生长的缓冲层, 结合于所述生长衬底表面; 以及 多个 Si02凸起, 间隔排列于所述缓冲层表面。 3、 根据权利要求 12所述的用于 III-V族氮化物生长的衬底结构, 其特征在于: 所述生长衬底的材料为蓝宝石、 SiC、 Si及 ZnO的一种。 、 根据权利要求 12所述的用于 III-V族氮化物生长的衬底结构, 其特征在于: 所述缓冲层的厚度为 50〜400埃。 5、 根据权利要求 12所述的用于 III-V族氮化物生长的衬底结构, 其特征在于:
所述缓冲层为 (0001 ) 晶向的 A1N层; 或 AlxGai_xN层, 其中, 0≤X≤0.5; 或
BN材料层。 、 根据权利要求 12所述的用于 III-V族氮化物生长的衬底结构, 其特征在于: 所述 Si02凸起的高度为 0.2〜3μηι。 、 根据权利要求 12所述的用于 III-V族氮化物生长的衬底结构, 其特征在于: 所述多个 Si02凸起呈周期性间隔排列, Si02凸起的宽度为 1〜4μηι, 间距为 0.5〜2μηι。 、 根据权利要求 12所述的用于 III-V族氮化物生长的衬底结构, 其特征在于: 所述 Si02凸起为 Si02包状凸起、 Si02圆锥状凸起或 Si02金字塔状凸起。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310548758.4A CN104638068B (zh) | 2013-11-07 | 2013-11-07 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 |
CN201310548758.4 | 2013-11-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015066955A1 true WO2015066955A1 (zh) | 2015-05-14 |
Family
ID=53040823
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2013/090289 WO2015066955A1 (zh) | 2013-11-07 | 2013-12-24 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 |
PCT/CN2014/090414 WO2015067182A1 (zh) | 2013-11-07 | 2014-11-06 | 一种用于ⅲ-ⅴ族氮化物生长的衬底及其制备方法 |
PCT/CN2014/090415 WO2015067183A1 (zh) | 2013-11-07 | 2014-11-06 | 一种ⅲ-ⅴ族氮化物半导体外延片、包含该外延片的器件及其制备方法 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/090414 WO2015067182A1 (zh) | 2013-11-07 | 2014-11-06 | 一种用于ⅲ-ⅴ族氮化物生长的衬底及其制备方法 |
PCT/CN2014/090415 WO2015067183A1 (zh) | 2013-11-07 | 2014-11-06 | 一种ⅲ-ⅴ族氮化物半导体外延片、包含该外延片的器件及其制备方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US10230018B2 (zh) |
JP (2) | JP2017504221A (zh) |
KR (2) | KR20160120271A (zh) |
CN (2) | CN104638068B (zh) |
TW (2) | TWI521734B (zh) |
WO (3) | WO2015066955A1 (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6375890B2 (ja) * | 2014-11-18 | 2018-08-22 | 日亜化学工業株式会社 | 窒化物半導体素子及びその製造方法 |
CN104993023B (zh) * | 2015-05-29 | 2018-06-05 | 上海芯元基半导体科技有限公司 | 一种利用化学腐蚀的方法剥离生长衬底的方法 |
CN105575797A (zh) * | 2015-12-23 | 2016-05-11 | 苏州工业园区纳米产业技术研究院有限公司 | 一种使蚀刻后晶圆上介质倾斜角变小的光阻回流制备方法 |
CN108780828B (zh) | 2016-01-05 | 2022-02-11 | 苏州乐琻半导体有限公司 | 半导体器件 |
CN106340571B (zh) * | 2016-09-12 | 2019-05-14 | 华灿光电(浙江)有限公司 | 一种发光二极管及其制作方法 |
CN106784217A (zh) * | 2016-12-12 | 2017-05-31 | 上海芯元基半导体科技有限公司 | 复合衬底、半导体器件结构及其制备方法 |
CN106684256A (zh) * | 2016-12-23 | 2017-05-17 | 上海天马有机发光显示技术有限公司 | 一种显示面板及其制作方法 |
EP3346508B1 (en) | 2017-01-10 | 2023-03-01 | Samsung Electronics Co., Ltd. | Optical sensor and image sensor including graphene quantum dots |
CN110112271A (zh) * | 2019-06-14 | 2019-08-09 | 江西乾照光电有限公司 | 一种底层带有凹纳米图形的led外延结构及其制作方法 |
FR3086097B1 (fr) * | 2018-09-18 | 2020-12-04 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif electroluminescent |
CN110923808A (zh) * | 2018-09-19 | 2020-03-27 | 中国科学院上海高等研究院 | 一种双壳层结构籽晶衬底及其制备方法 |
JP7298111B2 (ja) | 2019-06-07 | 2023-06-27 | 日亜化学工業株式会社 | 発光素子及びその製造方法 |
CN110571311B (zh) * | 2019-07-30 | 2021-12-14 | 中国科学技术大学 | 一种多量子阱结构、光电器件外延片及光电器件 |
JP7137539B2 (ja) * | 2019-08-06 | 2022-09-14 | 日機装株式会社 | 窒化物半導体発光素子の製造方法 |
CN112467005A (zh) * | 2020-11-18 | 2021-03-09 | 福建中晶科技有限公司 | 一种多复合层图形化蓝宝石衬底的制备方法 |
CN112563377A (zh) * | 2020-12-09 | 2021-03-26 | 武汉大学 | 生长在具有异质材料阵列的衬底上的倒装发光二极管芯片 |
CN112687777B (zh) * | 2020-12-18 | 2021-12-03 | 华灿光电(苏州)有限公司 | 发光二极管外延片及其制备方法 |
KR20230073549A (ko) | 2021-11-19 | 2023-05-26 | 주식회사루미지엔테크 | 질화물막의 성장 방법 |
CN115267953A (zh) * | 2022-07-29 | 2022-11-01 | 深圳通感微电子有限公司 | 微透镜的制备方法及制得的微透镜 |
CN116978991B (zh) * | 2023-09-22 | 2023-12-12 | 江西兆驰半导体有限公司 | 发光二极管外延片及其制备方法、led |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101471401A (zh) * | 2007-12-27 | 2009-07-01 | 深圳市方大国科光电技术有限公司 | 蓝宝石衬底发光二极管芯片的外延生长方法 |
CN101964382A (zh) * | 2009-07-21 | 2011-02-02 | 展晶科技(深圳)有限公司 | 提高光萃取效率的半导体光电结构及其制造方法 |
JP2011119627A (ja) * | 2009-12-05 | 2011-06-16 | Mtec:Kk | 半導体装置 |
CN102368526A (zh) * | 2011-10-27 | 2012-03-07 | 华灿光电股份有限公司 | 一种近紫外led器件的制造方法 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3026087B2 (ja) * | 1989-03-01 | 2000-03-27 | 豊田合成株式会社 | 窒化ガリウム系化合物半導体の気相成長方法 |
EP2234142A1 (en) * | 1997-04-11 | 2010-09-29 | Nichia Corporation | Nitride semiconductor substrate |
JP3196833B2 (ja) * | 1998-06-23 | 2001-08-06 | 日本電気株式会社 | Iii−v族化合物半導体の成長方法及びこの方法を用いた半導体発光素子の製造方法 |
JP2001196699A (ja) * | 2000-01-13 | 2001-07-19 | Sony Corp | 半導体素子 |
TW518767B (en) * | 2000-03-31 | 2003-01-21 | Toyoda Gosei Kk | Production method of III nitride compound semiconductor and III nitride compound semiconductor element |
JP4595198B2 (ja) * | 2000-12-15 | 2010-12-08 | ソニー株式会社 | 半導体発光素子及び半導体発光素子の製造方法 |
US6890785B2 (en) * | 2002-02-27 | 2005-05-10 | Sony Corporation | Nitride semiconductor, semiconductor device, and manufacturing methods for the same |
JP3966207B2 (ja) * | 2003-03-28 | 2007-08-29 | 豊田合成株式会社 | 半導体結晶の製造方法及び半導体発光素子 |
CN1306624C (zh) | 2003-07-16 | 2007-03-21 | 璨圆光电股份有限公司 | 选择性生长的发光二极管结构 |
US7683386B2 (en) * | 2003-08-19 | 2010-03-23 | Nichia Corporation | Semiconductor light emitting device with protrusions to improve external efficiency and crystal growth |
US6977219B2 (en) * | 2003-12-30 | 2005-12-20 | Intel Corporation | Solvent vapor-assisted plasticization of photoresist films to achieve critical dimension reduction during temperature reflow |
JP2005223154A (ja) * | 2004-02-05 | 2005-08-18 | Nichia Chem Ind Ltd | 基板の形成方法、半導体基板及び半導体素子 |
JP4652888B2 (ja) * | 2004-05-27 | 2011-03-16 | 昭和電工株式会社 | 窒化ガリウム系半導体積層構造体の製造方法 |
KR100580751B1 (ko) | 2004-12-23 | 2006-05-15 | 엘지이노텍 주식회사 | 질화물 반도체 발광소자 및 그 제조방법 |
KR100588377B1 (ko) * | 2005-05-10 | 2006-06-09 | 삼성전기주식회사 | 수직구조 질화갈륨계 발광다이오드 소자 및 그 제조방법 |
JP5023318B2 (ja) * | 2005-05-19 | 2012-09-12 | 国立大学法人三重大学 | 3−5族窒化物半導体積層基板、3−5族窒化物半導体自立基板の製造方法、及び半導体素子 |
JP2007214276A (ja) * | 2006-02-08 | 2007-08-23 | Mitsubishi Chemicals Corp | 発光素子 |
WO2007123496A1 (en) * | 2006-04-25 | 2007-11-01 | National University Of Singapore | Method of zinc oxide film grown on the epitaxial lateral overgrowth gallium nitride template |
JP2008034444A (ja) * | 2006-07-26 | 2008-02-14 | Showa Denko Kk | Iii族窒化物半導体発光素子の製造方法、iii族窒化物半導体発光素子及びランプ |
JP5311765B2 (ja) * | 2006-09-15 | 2013-10-09 | 住友化学株式会社 | 半導体エピタキシャル結晶基板およびその製造方法 |
KR100902512B1 (ko) * | 2007-05-17 | 2009-06-15 | 삼성코닝정밀유리 주식회사 | 실리콘 기판 상에 GaN 단결정의 성장 방법, GaN기반의 발광소자의 제조방법 및 GaN 기반의 발광소자 |
CN100563037C (zh) * | 2008-07-30 | 2009-11-25 | 鹤山丽得电子实业有限公司 | 一种发光二极管芯片及其制造方法 |
CN103038901A (zh) * | 2010-03-31 | 2013-04-10 | Cs解决方案有限公司 | 半导体模板衬底、使用半导体模板衬底的发光元件及其制造方法 |
CN101820041A (zh) * | 2010-04-01 | 2010-09-01 | 晶能光电(江西)有限公司 | 降低硅衬底led外延应力的方法以及结构 |
EP2587556B1 (en) * | 2010-06-28 | 2018-05-02 | Nichia Corporation | Method for manufacturing a sapphire substrate and growing a nitride semiconductor light emitting device |
CN102485944A (zh) | 2010-12-03 | 2012-06-06 | 武汉迪源光电科技有限公司 | 一种具有外延缺陷阻挡层的外延结构 |
CN102959739B (zh) * | 2010-12-08 | 2016-05-18 | 崇高种子公司 | Iii族氮化物半导体器件及其制造方法 |
CN102130245A (zh) | 2010-12-23 | 2011-07-20 | 映瑞光电科技(上海)有限公司 | 发光二极管及其制造方法 |
WO2012090818A1 (ja) * | 2010-12-29 | 2012-07-05 | シャープ株式会社 | 窒化物半導体構造、窒化物半導体発光素子、窒化物半導体トランジスタ素子、窒化物半導体構造の製造方法および窒化物半導体素子の製造方法 |
TWI514614B (zh) | 2011-08-30 | 2015-12-21 | Lextar Electronics Corp | 固態發光半導體結構及其磊晶層成長方法 |
TWI437737B (zh) * | 2011-09-14 | 2014-05-11 | Lextar Electronics Corp | 發光二極體結構及其製造方法 |
JP2013187296A (ja) * | 2012-03-07 | 2013-09-19 | Sharp Corp | 窒化物半導体素子形成用ウエハ、窒化物半導体素子形成用ウエハの製造方法、窒化物半導体素子、および窒化物半導体素子の製造方法 |
JP5874495B2 (ja) * | 2012-03-29 | 2016-03-02 | 豊田合成株式会社 | Gaを含むIII族窒化物半導体の製造方法 |
JP5811009B2 (ja) * | 2012-03-30 | 2015-11-11 | 豊田合成株式会社 | Iii族窒化物半導体の製造方法及びiii族窒化物半導体 |
CN103840051A (zh) * | 2013-12-03 | 2014-06-04 | 上海蓝光科技有限公司 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构的制造方法 |
CN103840041A (zh) * | 2013-12-03 | 2014-06-04 | 上海蓝光科技有限公司 | 一种用于氮化物生长的复合衬底结构的制造方法 |
-
2013
- 2013-11-07 CN CN201310548758.4A patent/CN104638068B/zh not_active Expired - Fee Related
- 2013-12-24 WO PCT/CN2013/090289 patent/WO2015066955A1/zh active Application Filing
-
2014
- 2014-11-06 CN CN201480009718.5A patent/CN105190915A/zh active Pending
- 2014-11-06 WO PCT/CN2014/090414 patent/WO2015067182A1/zh active Application Filing
- 2014-11-06 US US15/035,274 patent/US10230018B2/en active Active
- 2014-11-06 KR KR1020167015088A patent/KR20160120271A/ko not_active Application Discontinuation
- 2014-11-06 TW TW103138556A patent/TWI521734B/zh active
- 2014-11-06 US US15/035,314 patent/US20160359083A1/en not_active Abandoned
- 2014-11-06 JP JP2016552661A patent/JP2017504221A/ja active Pending
- 2014-11-06 WO PCT/CN2014/090415 patent/WO2015067183A1/zh active Application Filing
- 2014-11-06 TW TW103138560A patent/TWI574434B/zh active
- 2014-11-06 KR KR1020167015087A patent/KR20160122118A/ko not_active IP Right Cessation
-
2018
- 2018-10-09 JP JP2018003891U patent/JP3219854U/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101471401A (zh) * | 2007-12-27 | 2009-07-01 | 深圳市方大国科光电技术有限公司 | 蓝宝石衬底发光二极管芯片的外延生长方法 |
CN101964382A (zh) * | 2009-07-21 | 2011-02-02 | 展晶科技(深圳)有限公司 | 提高光萃取效率的半导体光电结构及其制造方法 |
JP2011119627A (ja) * | 2009-12-05 | 2011-06-16 | Mtec:Kk | 半導体装置 |
CN102368526A (zh) * | 2011-10-27 | 2012-03-07 | 华灿光电股份有限公司 | 一种近紫外led器件的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI574434B (zh) | 2017-03-11 |
TW201521228A (zh) | 2015-06-01 |
WO2015067182A1 (zh) | 2015-05-14 |
US20160359083A1 (en) | 2016-12-08 |
JP2017504221A (ja) | 2017-02-02 |
CN104638068A (zh) | 2015-05-20 |
WO2015067183A1 (zh) | 2015-05-14 |
TW201521223A (zh) | 2015-06-01 |
KR20160122118A (ko) | 2016-10-21 |
TWI521734B (zh) | 2016-02-11 |
US20160359082A1 (en) | 2016-12-08 |
US10230018B2 (en) | 2019-03-12 |
KR20160120271A (ko) | 2016-10-17 |
JP3219854U (ja) | 2019-01-31 |
CN105190915A (zh) | 2015-12-23 |
CN104638068B (zh) | 2018-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2015066955A1 (zh) | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 | |
WO2016192434A1 (zh) | 一种利用化学腐蚀的方法剥离生长衬底的方法 | |
CN101908505B (zh) | 一种发光二极管芯片的制造方法 | |
JP2007294972A (ja) | 発光素子及びその製造方法 | |
JP5306779B2 (ja) | 発光素子及びその製造方法 | |
KR20110013325A (ko) | 나노 패턴화 기판 및 에피택시 구조체 | |
WO2011143918A1 (zh) | 发光二极管及其制造方法 | |
CN103700735B (zh) | 一种发光二极管及其制造方法 | |
CN101814564B (zh) | 氮化物外延生长的纳米图形衬底制备方法 | |
US20130193406A1 (en) | Light emitting diode and fabrication method thereof | |
CN105336821A (zh) | GaN基LED外延结构及其制备方法 | |
WO2016041471A1 (zh) | 一种具有特殊粗化形貌的led垂直芯片结构及其制备方法 | |
CN103840041A (zh) | 一种用于氮化物生长的复合衬底结构的制造方法 | |
WO2011143919A1 (zh) | 发光二极管及其制造方法 | |
CN103840051A (zh) | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构的制造方法 | |
TWI475721B (zh) | Led磊晶結構及製造方法 | |
CN104752568A (zh) | 一种改善晶体质量的GaN基LED外延结构的制备方法 | |
CN104681681B (zh) | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 | |
CN108550673B (zh) | 图形化衬底、外延片及其制作方法 | |
TW201242076A (en) | LED and method for manufacturing the same | |
WO2016173359A1 (zh) | 一种发光二极管结构及其制备方法 | |
CN218215342U (zh) | 发光器件的结构 | |
CN201956386U (zh) | 一种发光二极管结构 | |
CN101719466B (zh) | 一种在图形衬底上生长氮化物薄膜外延层的方法 | |
KR100730752B1 (ko) | 초격자층을 갖는 화합물 반도체, 이를 이용한 발광 다이오드 및 이의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13897159 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 13897159 Country of ref document: EP Kind code of ref document: A1 |