WO2016041471A1 - 一种具有特殊粗化形貌的led垂直芯片结构及其制备方法 - Google Patents

一种具有特殊粗化形貌的led垂直芯片结构及其制备方法 Download PDF

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WO2016041471A1
WO2016041471A1 PCT/CN2015/089497 CN2015089497W WO2016041471A1 WO 2016041471 A1 WO2016041471 A1 WO 2016041471A1 CN 2015089497 W CN2015089497 W CN 2015089497W WO 2016041471 A1 WO2016041471 A1 WO 2016041471A1
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layer
epitaxial structure
holes
micron
silicon dioxide
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PCT/CN2015/089497
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English (en)
French (fr)
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童玲
张琼
吕孟岩
张宇
李起鸣
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映瑞光电科技(上海)有限公司
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Priority to DE112015004200.8T priority Critical patent/DE112015004200T5/de
Priority to GB1704361.3A priority patent/GB2547123B/en
Publication of WO2016041471A1 publication Critical patent/WO2016041471A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Definitions

  • the invention relates to the field of semiconductors, in particular to an LED vertical chip structure with a special roughened topography and a preparation method thereof.
  • LED Light-Emitting Diode
  • LED Light-Emitting Diode
  • a formal structure a flip-chip structure
  • a vertical structure a vertical structure.
  • Vertical structure LED can effectively solve the key problems of low heat dissipation efficiency and current blocking of LEDs in flip-chip structure and flip-chip structure, improve LED luminous efficiency and light intensity, and have good heat dissipation, can carry large current, and have high luminous intensity. It is widely used in general lighting, landscape lighting, special lighting, automotive lighting and other fields due to its low power consumption and long life. It is receiving more and more attention and research from the industry and is an inevitable trend in the development of semiconductor lighting technology.
  • the vertical structure LED is stripped of the sapphire substrate, and the reflective layer can be directly disposed on the P-type epitaxial layer, and the light randomly radiated toward the non-light-emitting surface of the device is directly reflected by the reflective layer, and the common reflective layer is composed of a metal reflective layer or a dielectric material.
  • the distribution of reflective layers in Prague, etc. avoids the problem that the light extraction efficiency is reduced due to the random emission of the active region inside the device to the non-light-emitting surface.
  • the light extraction efficiency of GaN-based LEDs is limited by the large refractive index difference between GaN and air. According to Snell's law, only light with an incident angle within a critical angle (about 23°) can be emitted into the air, outside the critical angle. The light can only be reflected back and forth inside the GaN until it is self-absorbed.
  • the patterned substrate is widely used in the preparation of the LED because the pattern on the substrate can be reflected on the surface of the epitaxial N-type layer and serves as an LED.
  • the light exiting surface increases the refractive index of the light exiting surface.
  • the patterned substrate needs to be stripped, so the vertical structure LED faces the problem of how to improve the light extraction efficiency.
  • the present invention provides an LED vertical chip structure having a special roughened topography, including:
  • a metal bonding electrode layer formed on a surface of the conductive support substrate
  • a metal reflective electrode layer formed on a surface of the metal bonding electrode layer
  • An epitaxial structure layer is formed on a surface of the contact layer, the epitaxial structure layer includes a P-type GaN layer, an N-type GaN layer, and an active region layer bonded between the P-type GaN layer and the N-type GaN layer, wherein a micron-sized hole on the surface of the epitaxial structure layer and a submicron-sized hole at the bottom of the micro-scale hole;
  • An N electrode is bonded to the surface of the epitaxial structure layer.
  • the micron-sized pores have a pore diameter of 2 ⁇ m to 3 ⁇ m and a depth of 1 ⁇ m to 3 ⁇ m; and the submicron-sized pores have a pore diameter of 300 nm to 800 nm and a depth of 1 ⁇ m to 2 ⁇ m.
  • the material of the metal bonding electrode layer is Au-Sn eutectic.
  • the metal reflective electrode layer is made of Ag.
  • the contact layer is made of ITO or Ni.
  • the invention also provides a preparation method of an LED vertical chip structure having a special roughened morphology, comprising:
  • An N electrode is formed on a surface of the epitaxial structure layer.
  • the step of etching the surface of the epitaxial structure layer comprises:
  • Dry etching is performed by using the silicon dioxide layer as a mask to form submicron holes at the bottom of the micron-sized holes;
  • the remaining silicon dioxide layer is removed.
  • an unintentionally doped layer is formed on the surface of the growth substrate, and an epitaxial structure layer is formed on the surface of the unintentionally doped layer;
  • micron-scale holes are formed on the surface of the unintentionally doped layer, the unintentionally doped layer is removed, and the micro-scale holes are transferred to the epitaxial structure layer, and finally The surface of the epitaxial structure layer is etched to form submicron-scale holes at the bottom of the micron-sized holes.
  • the sub-micron holes are formed by the following steps:
  • the silicon dioxide layer is removed.
  • the thickness of the epitaxial structure layer is 5 ⁇ m-8 ⁇ m
  • the thickness of the unintentional doped layer is 1 ⁇ m-3 ⁇ m
  • the thickness of the silicon dioxide layer deposited on the surface of the epitaxial structure layer is 1000 nm-2000 nm.
  • the sub-micron holes are formed by the following steps:
  • the micron-scale holes are formed on the surface of the epitaxial structure layer and submicron-sized holes are formed at the bottom of the micro-scale holes.
  • the thickness of the epitaxial structure layer is 5 ⁇ m-8 ⁇ m
  • the thickness of the unintentionally doped layer is 1 ⁇ m-3 ⁇ m
  • the thickness of the silicon dioxide layer deposited on the surface of the unintentionally doped layer is 500 nm-1000 nm. .
  • a process of surface roughening the surface of the epitaxial structure layer is further included.
  • the LED vertical chip structure with special roughening morphology provided by the invention forms micron-scale holes on the surface of the epitaxial structure layer and sub-micron holes at the bottom of the micro-scale holes, and the light-emitting surface structure can increase the light emission inside the device. Probability, greatly improving the efficiency of light extraction.
  • the method for preparing the above chip structure provided by the present invention forms a micron-sized hole on the epitaxial structure layer by stripping the growth substrate with micron-sized bumps, and forms submicron-sized holes at the bottom of the micron-sized holes by etching. Simple process, can be used for large-scale industrial production, can greatly improve the vertical structure LED luminous efficiency.
  • FIG. 1 is a flow chart of a method for fabricating an LED vertical chip structure having a special roughened topography according to an embodiment of the invention.
  • FIG. 2 to FIG. 8 are schematic cross-sectional views showing a device in a process for fabricating an LED vertical chip structure having a special roughened appearance according to an embodiment of the present invention.
  • FIGS. 9A-9D are schematic cross-sectional views of a device from a specific forming process of Figs. 5 to 6.
  • 10A-10B are schematic cross-sectional views of a device from another embodiment of FIG. 5 to FIG.
  • Figure 11 is a plan view (left) and a side view (right) of the device in an SEM electron microscope after stripping the growth substrate.
  • Figure 12 is a plan view (left) and a side view (right) of the device in the step shown in Figure 9A in a SEM electron microscope.
  • Fig. 13A is a plan view (left) and a side view (right) of a device formed by the formation method shown in Figs. 9A to 9D in an SEM electron microscope.
  • Fig. 13B is a plan view (left) and a side view (right) of the device formed by the formation method shown in Figs. 10A to 10B in an SEM electron microscope.
  • the invention provides an LED vertical chip structure with a special roughened appearance, as shown in FIG.
  • the LED vertical chip structure includes: a conductive support substrate 700, a metal bonding electrode layer 600 formed on a surface of the conductive support substrate 700, and a metal reflective electrode layer 500 formed on a surface of the metal bonding electrode layer 600, A contact layer 400 formed on a surface of the metal reflective electrode layer 500, an epitaxial structure layer 300 formed on a surface of the contact layer 400, and an N electrode 800 formed on a surface of the epitaxial structure layer 300.
  • the epitaxial structure layer 300 includes a P-type GaN layer 330, an N-type GaN layer 310, and an active region layer 320 formed between the P-type GaN layer 330 and the N-type GaN layer 310.
  • On the surface of the epitaxial structure layer 300 there are micron-sized holes 311 and submicron-sized holes 312 at the bottom of the micro-scale holes.
  • the micron-scale and sub-micron-scale descriptions are such that, in terms of the pore size (diameter) of the pores, the formation of sub-micron pores 312 having a narrower pore diameter at the bottom of the micron-sized pores 311 is more advantageous for improving light extraction efficiency.
  • the micron-sized pores have a pore diameter of 2 ⁇ m to 3 ⁇ m and a depth of 1 ⁇ m to 3 ⁇ m; and the submicron-sized pores have a pore diameter of 300 nm to 800 nm and a depth of 1 ⁇ m to 2 ⁇ m.
  • the material of the conductive support substrate 700 is silicon, copper, aluminum, tungsten or various alloys, etc., preferably, silicon, tungsten copper alloy or copper molybdenum alloy with high electrical conductivity; the metal bond
  • the material of the electrode layer 600 is Au-Sn eutectic; the material of the metal reflective electrode layer 500 is Ag; and the material of the contact layer 400 is ITO or Ni.
  • the material of the N electrode 800 is a Ni/Au alloy, an Al/Ti/Pt/Au alloy, or a Cr/Pt/Au alloy.
  • the invention also provides a method for preparing an LED vertical chip structure having a special roughened topography, and the steps of the LED vertical chip structure manufacturing method are described in detail below with reference to FIGS. 1 to 8.
  • step S1 providing a growth substrate, etching a surface of the growth substrate to form a micro-scale protrusion, and then forming an epitaxial structure layer on the growth substrate;
  • etching is performed on the surface of the substrate by wet etching or dry etching.
  • a micron-sized bump is formed to prepare a growth substrate 100 having a surface having a specific micron-scale protrusion.
  • the substrate is a sapphire substrate or a silicon substrate, which is not limited in the present invention.
  • an N-type GaN layer 310, an active region layer 320, and a P-type GaN layer 330 are sequentially grown on the growth substrate 100 to form an epitaxial structure layer 300.
  • a preferred embodiment of the present embodiment is that (CH 3 ) 3 Ga (trimethylgallium) is a Ga (gallium) source, NH 3 (ammonia gas) is an N source, and SiH 4 (silane) is used as an N-type doping.
  • An N-type GaN layer 310 is grown on the growth substrate 100 by a metal organic compound chemical vapor deposition method;
  • (CH 3 ) 3 In (trimethyl indium) is a source of In (indium)
  • (CH 3 ) 3 Ga is a Ga source
  • NH 3 is an N source
  • an InGaN/GaN active layer 320 is grown on the N-type GaN layer 310 by a metal organic compound chemical vapor deposition method
  • (CH 3 ) 3 Ga is used as a Ga source.
  • NH 3 is an N source
  • Mg(C 5 H 5 ) 2 magnesium pentoxide
  • a P-type GaN layer is grown on the active layer 320 by a metal organic compound chemical vapor deposition method.
  • an unintentionally doped layer 200 is formed on the surface of the growth substrate.
  • An epitaxial structure layer 300 is formed on the surface of the unintentionally doped layer 200.
  • the material of the unintentionally doped layer 200 is undoped GaN, which is more advantageous for the growth of the subsequent epitaxial structure layer 300.
  • step S2 is performed to sequentially form a contact layer, a metal reflective electrode layer and a metal bonding electrode layer on the epitaxial structure layer;
  • a contact layer 400 is evaporated on the P-type GaN layer 330, and a P-type GaN layer 330 is bonded to the contact layer 400 to form an ohmic contact, and then the metal is evaporated on the contact layer 400.
  • the electrode layer 500 is reflective such that an optical reflective layer is formed between the contact layer 400 and the metal reflective electrode layer 500, and finally the metal bonding electrode layer 600 is formed.
  • step S3 is performed to form a conductive support substrate on the metal bonding electrode layer
  • the metal reflective electrode layer 500 is bonded to the conductive support substrate 700 through the metal bonding electrode layer 600.
  • the material of the conductive support substrate 700 is silicon, copper, aluminum, tungsten or various alloys, etc., preferably, silicon, tungsten copper alloy or copper molybdenum alloy with high electrical and thermal conductivity;
  • the material of the metal bonding electrode layer 600 is Au-Sn eutectic;
  • the material of the metal reflective electrode layer 500 is Ag;
  • the material of the contact layer 400 is ITO or Ni;
  • the material of the N electrode 800 is Ni /Au alloy, Al/Ti/Pt/Au alloy or Cr/Pt/Au alloy.
  • step S4 is performed to peel off the growth substrate to form micron-scale holes on the surface of the epitaxial structure layer
  • the growth substrate 100 is peeled off by a laser lift-off technique, and a micron-scale is formed on the surface of the N-type GaN layer 310 of the epitaxial structure layer 300 by the micro-scale bumps on the growth substrate 100. Hole.
  • the shape of the surface of the epitaxial structure layer is as shown in FIG. Figure 11 is a plan view (left) and a side view (right) of the device after stripping the growth substrate 100.
  • the surface of the growth substrate 100 is etched to form a micro-scale bump, an unintentionally doped layer 200 is formed on the surface of the growth substrate, and then the unintentional layer is unintentionally
  • the epitaxial structure layer 300 is formed on the surface of the doped layer 200. Therefore, after the growth substrate 100 is peeled off, the micro-scale holes 210 are formed on the unintentionally doped layer 200.
  • step S5 is performed to etch the surface of the epitaxial structure layer to form submicron holes at the bottom of the micron-sized holes;
  • the step of etching the surface of the epitaxial structure layer comprises: depositing a silicon dioxide layer on the surface of the epitaxial structure layer; performing dry etching on the silicon dioxide layer as a mask, in the Submicron holes are formed in the bottom of the micron-sized holes; the remaining silicon dioxide layer is removed.
  • the process of depositing a silicon dioxide layer is performed by chemical vapor deposition. It should be particularly noted that, due to the characteristics of the chemical vapor deposition process, silicon dioxide formed on the surface of the epitaxial structure layer filled with micron-sized pores may concentrate on a portion between the micron-sized pores, and at the micron level. There is relatively little silica deposited at the bottom of the hole. Therefore, when the silicon dioxide layer is used as a mask for dry etching, the silicon dioxide at the bottom of the micron-sized pores is first etched, and the etching is continued at the bottom of the micron-sized pores. Micron holes. In the process, the micron The portion between the graded holes is protected by thicker silica.
  • an unintentionally doped layer 200 is formed on the surface of the growth substrate, and then the unintentional layer is unintentionally
  • the epitaxial structure layer 300 is formed on the surface of the doped layer 200, and the micro-scale holes 210 are formed on the unintentionally doped layer 200 after the growth substrate 100 is peeled off as described above. Therefore, as shown in FIG. 6, the unintentionally doped layer 200 is first etched away and the micro-scale holes are transferred to the epitaxial structure layer 300, and the surface of the epitaxial structure layer 300 is etched again.
  • the bottom of the micron-sized holes 311 forms submicron-sized holes 312.
  • step S6 is performed to form an N electrode on the surface of the epitaxial structure layer.
  • a process of roughening the surface of the epitaxial structure layer 300 is further included, and after roughening, on the surface of the N-type GaN layer 310.
  • a plurality of raised structures 313 are formed between the plurality of micron-sized holes 311.
  • an N electrode 800 is formed on the surface of the epitaxial structure layer 300.
  • the roughening is performed by a wet etching process, and the solution may be KOH, H 3 PO 4 or the like.
  • the process of forming the N electrode 800 is vapor deposition, and the material of the N electrode 800 is Ni/Au alloy, Al/Ti/Pt/Au alloy, Cr/Pt/Au alloy, or the like.
  • the method for fabricating an LED vertical chip structure having a special roughened topography has a preferred solution, which involves a process of integrally processing the substrate, thereby taking into account the vertical chip structure of the LED. Inter-groove processing.
  • the gap between the LED vertical chip structures is the gap between different devices after forming a plurality of the above-mentioned LED vertical chip structures on one substrate.
  • This process can be implemented in two ways. The implementation of the two methods is described in detail below.
  • micron-sized holes 210 are formed on the unintentionally doped layer 200.
  • the surface of the unintentionally doped layer 200 is dry etched to remove the unintentionally doped layer 200, and the micron-sized holes existing on the unintentionally doped layer 200 are removed.
  • 210 is transferred to the surface of the epitaxial structure layer 300.
  • the thickness of the epitaxial structure layer 300 is 5 ⁇ m-8 ⁇ m
  • the thickness of the unintentionally doped layer 200 is 1 ⁇ m-3 ⁇ m
  • the dry etching is about 30 min, thereby removing the unintentional blend of 1 ⁇ m-3 ⁇ m thick. Miscellaneous layer 200.
  • the formed device topography is shown in Figure 12.
  • Figure 12 is a plan view (left) and a side view (right) of the device in the step shown in Figure 9A in a SEM electron microscope.
  • a silicon dioxide layer 10 is deposited on the surface of the epitaxial structure layer 300.
  • a silicon dioxide layer formed on the surface of the epitaxial structure layer 300 filled with micron-sized pores may concentrate on a portion between the micro-scale pores, and in the micron There is relatively little silica deposited at the bottom of the graded holes.
  • the thickness of the silicon dioxide layer 10 deposited on the surface of the epitaxial structure layer 300 is 1000 nm to 2000 nm, and the thickness of the silicon dioxide layer 10 is a portion of the silicon dioxide layer between the micron-sized holes. 10 thickness.
  • the silicon dioxide layer 10 at the trench between the vertical chip structures of the LED is removed by photolithography, and the epitaxial structure layer 300 is exposed at the trench to retain silicon dioxide only above the vertical chip structure of the LED.
  • the gap between the LED vertical chip structures is the gap between different devices after forming a plurality of the above-mentioned LED vertical chip structures on one substrate.
  • the photolithography method comprises: forming a photoresist layer on the silicon dioxide layer 10, performing exposure development on the photoresist layer to form a patterned photoresist layer, the patterned photoresist a layer exposing the silicon dioxide layer 10 of the trench portion, and then etching the silicon dioxide layer 10 with the patterned photoresist layer as a mask, and exposing the epitaxial structure layer at the trench portion 300, the remaining photoresist layer is removed to form a structure as shown in FIG. 9C. Wherein the silicon dioxide layer is wet etched 10 using BOE solution.
  • the epitaxial structure layer 300 and the silicon dioxide layer 10' are simultaneously dry etched, and the contact layer 400 is exposed at the trench by controlling the process, and at the same time
  • the bottom of the micron-sized holes 311 forms the purpose of submicron-scale holes 312.
  • a portion of the silicon dioxide layer 10" remains between the micro-scale holes 311 without being completely etched, thereby protecting the underlying epitaxial structure layer 300.
  • Fig. 13A is a plan view (left) and a side view (right) of a device formed by the formation method shown in Figs. 9A to 9D in an SEM electron microscope.
  • micron-sized holes 210 are formed on the unintentionally doped layer 200.
  • a silicon dioxide layer 20 is deposited on the surface of the unintentionally doped layer 200.
  • the thickness of the epitaxial structure layer 300 is 5 ⁇ m-8 ⁇ m
  • the thickness of the unintentionally doped layer 200 is 1 ⁇ m-3 ⁇ m
  • the thickness of the silicon dioxide layer 20 is deposited on the surface of the unintentionally doped layer 300.
  • the maximum value is from 500 nm to 1000 nm
  • the maximum of the thickness is the thickness of the silicon dioxide layer 20 on the portion between the micron-sized holes.
  • the silicon dioxide layer 20 at the trench between the vertical chip structures of the LED is removed by photolithography, and the unintentionally doped layer 200 is exposed at the trench, and only remains above the vertical chip structure of the LED.
  • the photolithography method comprises: forming a photoresist layer on the silicon dioxide layer 20, and performing exposure development on the photoresist layer to form a patterned photoresist layer, the patterned photoresist The layer exposes the silicon dioxide layer 20 of the trench portion, and then the patterned photoresist layer is used as a mask, engraved The silicon dioxide layer 20 is etched, the unintentionally doped layer 200 is exposed at the trench portion, and the remaining photoresist layer is removed to form a structure as shown in FIG. 10B. Wherein, the silicon dioxide layer 20 is wet etched using a BOE solution.
  • the silicon dioxide layer 20' and the unintentionally doped layer 300 exposed at the trench are simultaneously dry etched, and the exposure at the trench is realized by controlling the process.
  • the contact layer 400 is being described, the silicon dioxide layer 20 ′ and the unintentionally doped layer 200 are removed at the non-the trench (above the LED vertical chip structure), and formed on the surface of the epitaxial structure layer 300
  • the micron-sized pores 311 and the submicron-sized pores 312 are formed at the bottom of the micron-sized pores to obtain a structure as shown in the surface of FIG.
  • the specific shape of the device formed by this method is shown in Fig. 13B.
  • Fig. 13B is a plan view (left) and a side view (right) of the device formed by the formation method shown in Figs. 10A to 10B in an SEM electron microscope.
  • the method of forming the silicon dioxide layer 20 by this method can remove all the silicon dioxide layers 20 by forming the micro-scale holes 311 and the sub-micron-sized holes 312 by dry etching before removing the unintentionally doped layer 200, eliminating the need to remove all the silicon dioxide layers 20 by dry etching.
  • the subsequent step of removing silica is convenient and quick. However, the requirements for process control are fine, and the etched submicron holes 312 are not as fine as the method.
  • the LED vertical chip structure with special roughened morphology provided by the invention has micron-shaped holes on the surface of the epitaxial structure layer and sub-micron holes at the bottom of the microscopic holes, and the light-emitting surface structure can increase the probability of light emission inside the device. , greatly improve the efficiency and quality of light.
  • the method for fabricating the above LED vertical chip structure provided by the present invention forms a micron-sized hole on the epitaxial structure layer by stripping the growth substrate with the micron-sized bump, and forms submicron-sized holes at the bottom of the micron-sized hole by etching. The method is simple in process, can be used for large-scale industrial production, and can greatly improve the luminous efficiency of the vertical structure LED.

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Abstract

一种提高垂直结构LED发光效率的方法。首先，提供一种具有特殊粗化形貌的LED垂直芯片结构，在外延结构层（300）的表面形成微米级孔洞（311）以及位于微米级孔洞底部的亚微米级孔洞（312），此种出光面结构能增加器件内部光的出射几率，大大提高出光效率。还提供了一种上述芯片结构的制备方法，通过剥离带微米级凸起的生长衬底（100），在外延结构层（300）上形成微米级孔洞（311），并通过刻蚀在微米级孔洞（311）的底部形成亚微米级孔洞（312），此方法工艺简单，可用于大规模的工业生产，能够大大提高垂直结构LED发光效率。

Description

一种具有特殊粗化形貌的LED垂直芯片结构及其制备方法 技术领域
本发明涉及半导体领域，尤其涉及一种具有特殊粗化形貌的LED垂直芯片结构及其制备方法。
背景技术
从LED(Light-Emitting Diode,发光二极管)的结构上讲，可以分为正装结构、倒装结构和垂直结构。垂直结构LED可以有效解决正装结构LED和倒装结构LED存在的散热效率低和电流阻塞等关键问题，提高LED的发光效率和光强密度，且具有散热好、能够承载大电流、发光强度高、耗电量小以及寿命长等优点，因此被广泛应用于通用照明、景观照明、特种照明、汽车照明等领域，正受到业界越来越多的关注和研究，是半导体照明技术发展的必然趋势。
垂直结构LED剥离了蓝宝石衬底，可直接在P型外延层上布置反射层，器件内部随机射向非出光面的光直接通过反射层反射，通常的反射层为金属反射层或者电介质材料构成的布拉格分布反射层等，避免了由于器件内部有源区随机射向非出光面而易造成光抽取效率降低的问题。GaN基LED的光抽取效率受制于GaN与空气之间巨大的折射率差，根据斯涅耳定律，只有入射角在临界角(约23°)以内的光可以出射到空气中，而临界角以外的光只能在GaN内部来回反射，直至被自吸收。
对于正装结构LED和倒装结构LED，为了提高LED的出光效率，图形化衬底在LED的制备中被广泛采用，因为衬底上的图形能体现到外延N型层的表面，并作为LED的出光面，增大出光面的折射率。而对于垂直结构LED，图形化衬底需被剥离，因此垂直结构LED面临着如何提高光提取效率的问题。
发明内容
本发明的目的在于提供一种垂直结构LED及其制备方法，以解决现有技术中垂直结构LED光提取效率低的问题。
鉴于此，本发明提供一种具有特殊粗化形貌的LED垂直芯片结构，包括：
导电支撑衬底；
金属键合电极层，形成于所述导电支撑衬底的表面；
金属反射电极层，形成于所述金属键合电极层的表面；
接触层，形成于所述金属反射电极层的表面；
外延结构层，形成于所述接触层的表面，所述外延结构层包括P型GaN层、N型GaN层以及结合于所述P型GaN层和N型GaN层中间的有源区层，其中，在所述外延结构层的表面具有微米级孔洞以及位于所述微米级孔洞底部的亚微米级孔洞；
N电极，结合于所述外延结构层的表面。
可选的，所述微米级孔洞的孔径为2μm-3μm，深度为1μm-3μm；所述亚微米级孔洞的孔径为300nm-800nm,深度为1μm-2μm。
可选的，所述金属键合电极层的材质为Au-Sn共晶。
可选的，所述金属反射电极层的材质为Ag。
可选的，所述接触层的材质为ITO或Ni。
本发明还提供一种具有特殊粗化形貌的LED垂直芯片结构的制备方法，包括:
提供生长衬底，在所述生长衬底表面刻蚀形成微米级凸起，然后在所述生长衬底上形成外延结构层；
在所述外延结构层上依次形成接触层、金属反射电极层和金属键合电 极层；
在所述金属键合电极层上形成导电支撑衬底；
剥离所述生长衬底，以在所述外延结构层的表面形成微米级孔洞；
刻蚀所述外延结构层的表面，以在所述微米级孔洞的底部形成亚微米级孔洞；
在所述外延结构层的表面形成N电极。
可选的，刻蚀所述外延结构层的表面的步骤包括：
在所述外延结构层的表面沉积二氧化硅层；
以所述二氧化硅层作掩膜进行干法刻蚀，以在所述微米级孔洞的底部形成亚微米级孔洞；
去除剩余的所述二氧化硅层。
可选的，在所述生长衬底表面刻蚀形成微米级凸起后，先在所述生长衬底表面形成非故意掺杂层，再在所述非故意掺杂层表面形成外延结构层；在剥离所述生长衬底后，先在所述非故意掺杂层的表面形成微米级孔洞，再去除所述非故意掺杂层并将所述微米级孔洞转移至所述外延结构层，最后刻蚀所述外延结构层的表面，以在所述微米级孔洞的底部形成亚微米级孔洞。
可选的，在所述非故意掺杂层的表面形成微米级孔洞后，通过以下步骤形成亚微米级孔洞：
干法刻蚀所述非故意掺杂层的表面以去除所述非故意掺杂层，并将所述微米级孔洞转移至所述外延结构层的表面；
在所述外延结构层的表面沉积二氧化硅层；
通过光刻和刻蚀工艺去除LED器件间沟槽处的二氧化硅层，在所述沟槽处露出所述外延结构层；
对所述外延结构层和二氧化硅层同时进行干法刻蚀，在所述沟槽处露 出所述接触层，并在所述微米级孔洞的底部形成亚微米级孔洞；
去除所述二氧化硅层。
可选的，所述外延结构层的厚度是5μm-8μm，所述非故意掺杂层的厚度为1μm-3μm，在所述外延结构层的表面沉积的二氧化硅层厚度为1000nm-2000nm。
可选的，在所述非故意掺杂层的表面形成微米级孔洞后，通过以下步骤形成亚微米级孔洞：
在所述非故意掺杂层表面沉积二氧化硅层；
通过光刻和刻蚀工艺去除LED器件间沟槽处的二氧化硅层，在所述沟槽处露出所述非故意掺杂层；
对所述二氧化硅层以及在所述沟槽处露出的所述非故意掺杂层同时进行干法刻蚀，在所述沟槽处露出所述接触层，同时在非所述沟槽处去除所述二氧化硅层和所述非故意掺杂层后，在所述外延结构层的表面形成所述微米级孔洞并在所述微米级孔洞的底部形成亚微米级孔洞。
可选的，所述外延结构层的厚度是5μm-8μm，所述非故意掺杂层的厚度为1μm-3μm，在所述非故意掺杂层表面沉积二氧化硅层的厚度为500nm-1000nm。
可选的，在形成N电极之前，还包括对所述外延结构层的表面进行表面粗化的过程。
本发明提供的具有特殊粗化形貌的LED垂直芯片结构，在外延结构层的表面形成微米级孔洞以及位于微米级孔洞底部的亚微米级孔洞，此种出光面结构能增加器件内部光的出射几率，大大提高出光效率。本发明提供的上述芯片结构的制备方法通过剥离带微米级凸起的生长衬底，在外延结构层上形成微米级孔洞，并通过刻蚀在微米级孔洞的底部形成亚微米级孔洞，此方法工艺简单，可用于大规模的工业生产，能够大大提高垂直结构 LED发光效率。
附图说明
图1为本发明一实施例所述具有特殊粗化形貌的LED垂直芯片结构的制备方法的流程图。
图2-图8为本发明一实施例所述具有特殊粗化形貌的LED垂直芯片结构的制造方法过程中的器件剖面示意图。
图9A-图9D为从图5到图6的一种具体形成过程的器件剖面示意图。
图10A-图10B为从图5到图6的另一种具体形成过程的器件剖面示意图。
图11为剥离生长衬底后器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
图12为图9A所示步骤中器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
图13A为通过图9A-图9D所示形成方法形成的器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
图13B为通过图10A-图10B所示形成方法形成的器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
具体实施方式
以下结合附图和具体实施例对本发明作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明提供一种具有特殊粗化形貌的LED垂直芯片结构，如图8所示， 所述LED垂直芯片结构包括：导电支撑衬底700，形成于所述导电支撑衬底700表面的金属键合电极层600，形成于所述金属键合电极层600表面的金属反射电极层500，形成于所述金属反射电极层500表面的接触层400，形成于所述接触层400表面的外延结构层300，以及形成于所述外延结构层300表面的N电极800。
其中，外延结构层300包括P型GaN层330、N型GaN层310以及形成于所述P型GaN层330和N型GaN层310中间的有源区层320。在所述外延结构层300的表面具有微米级孔洞311以及位于所述微米级孔洞底部的亚微米级孔洞312。所述微米级以及亚微米级的描述是针对孔洞的孔径(直径)而言，在微米级孔洞311的底部形成孔径更窄的亚微米级孔洞312，能更有利于提高光提取效率。优选方案中，所述微米级孔洞的孔径为2μm-3μm，深度为1μm-3μm；所述亚微米级孔洞的孔径为300nm-800nm,深度为1μm-2μm。在N型GaN层310表面的多个微米级孔洞311之间，具有经表面粗化形成的多个凸起结构313。
具体的，所述导电支撑衬底700的材质为硅、铜、铝、钨或各类合金等，优选的，为高导电导热率的硅、钨铜合金或铜钼合金；所述金属键合电极层600的材质为Au-Sn共晶；所述金属反射电极层500的材质为Ag；所述接触层400的材质为ITO或Ni。所述N电极800的材质为Ni/Au合金、Al/Ti/Pt/Au合金或Cr/Pt/Au合金等。
本发明还提供一种具有特殊粗化形貌的LED垂直芯片结构的制备方法，下面结合图1至图8所示，详细说明LED垂直芯片结构制造方法的各个步骤。
首先，执行步骤S1，提供生长衬底，在所述生长衬底表面刻蚀形成微米级凸起，然后在所述生长衬底上形成外延结构层；
在本实施例中，通过湿法刻蚀或者干法刻蚀刻蚀在所述衬底表面刻蚀 形成微米级凸起，以制备出一表面具有特定微米级凸起的生长衬底100，所述衬底为蓝宝石衬底，也可以为硅衬底，本发明不作限制。
然后，在所述生长衬底100上依次生长N型GaN层310、有源区层320以及P型GaN层330，以形成外延结构层300。本实施例的一个优选方案为，以(CH3)3Ga(三甲基镓)为Ga(镓)源，NH3(氨气)为N源，SiH4(硅烷)用作为N型掺杂剂，采用金属有机化合物化学气相淀积法在所述生长衬底100上生长N型GaN层310；以(CH3)3In(三甲基铟)为In(铟)源，(CH3)3Ga为Ga源，NH3为N源，采用金属有机化合物化学气相淀积法在所述的N型GaN层310上生长InGaN/GaN有源层320；以(CH3)3Ga为Ga源，NH3为N源，Mg(C5H5)2(二茂镁)作为P型掺杂剂，采用金属有机化合物化学气相淀积法在所述的有源层320上生长P型GaN层330。
如图2所示，在本实施例的一个优选方案中，在所述生长衬底100表面刻蚀形成微米级凸起后，先在所述生长衬底表面形成非故意掺杂层200，再在所述非故意掺杂层200表面形成外延结构层300。非故意掺杂层200的材质为未掺杂的GaN，其目的是更为了有利于后续外延结构层300的生长。
接着，执行步骤S2，在所述外延结构层上依次形成接触层、金属反射电极层和金属键合电极层；
如图3所示，在所述P型GaN层330上蒸镀接触层400，并熔合P型GaN层330与接触层400以形成欧姆接触，然后在所述接触层400上蒸镀所述金属反射电极层500，使得接触层400与金属反射电极层500之间形成一光学反射层，最后形成金属键合电极层600。
接着，执行步骤S3，在所述金属键合电极层上形成导电支撑衬底；
如图4所示，通过金属键合电极层600将所述的金属反射电极层500键合于导电支撑衬底700上。所述导电支撑衬底700的材质为硅、铜、铝、钨或各类合金等，优选的，为高导电导热率的硅、钨铜合金或铜钼合金； 所述金属键合电极层600的材质为Au-Sn共晶；所述金属反射电极层500的材质为Ag；所述接触层400的材质为ITO或Ni；所述N电极800的材质为Ni/Au合金、Al/Ti/Pt/Au合金或Cr/Pt/Au合金等。
接着，执行步骤S4，剥离所述生长衬底，以在所述外延结构层的表面形成微米级孔洞；
如图5所示，采用激光剥离技术剥离所述生长衬底100，通过所述生长衬底100上的微米级凸起，在所述外延结构层300的N型GaN层310的表面形成微米级孔洞。剥离所述生长衬底100后，外延结构层的表面的形状如图11所示。图11为剥离生长衬底100后器件的俯视图(左)和侧视图(右)。
在本实施例的一个优选方案中，由于在所述生长衬底100表面刻蚀形成微米级凸起后，先在所述生长衬底表面形成非故意掺杂层200，再在所述非故意掺杂层200表面形成外延结构层300，因此，剥离所述生长衬底100后，微米级孔洞210形成于非故意掺杂层200上。
接着，执行步骤S5，刻蚀所述外延结构层的表面，以在所述微米级孔洞的底部形成亚微米级孔洞；
其中，刻蚀所述外延结构层的表面的步骤包括：在所述外延结构层的表面沉积二氧化硅层；以所述二氧化硅层作掩膜进行干法刻蚀，在以在所述微米级孔洞的底部形成亚微米级孔洞；去除剩余的所述二氧化硅层。
具体的，沉积二氧化硅层的工艺采用化学气相淀积。需要特别说明的是，由于化学气相淀积工艺的特点，在充满微米级孔洞的外延结构层的表面形成的二氧化硅会集中于所述微米级孔洞之间的部分，而在所述微米级孔洞的底部沉积的二氧化硅相对较少。因此，以所述二氧化硅层作掩膜进行干法刻蚀时，所述微米级孔洞底部的二氧化硅会首先被刻蚀完，而在所述微米级孔洞的底部继续刻蚀形成亚微米级孔洞。在此过程中，所述微米 级孔洞之间的部分得到了较厚的二氧化硅的保护。
在本实施例的一个优选方案中，由于在所述生长衬底100表面刻蚀形成微米级凸起后，先在所述生长衬底表面形成非故意掺杂层200，再在所述非故意掺杂层200表面形成外延结构层300，且如前所述，剥离所述生长衬底100后，微米级孔洞210形成于非故意掺杂层200上。因此，如图6所示，此时先刻蚀去除所述非故意掺杂层200并将所述微米级孔洞转移至所述外延结构层300，再刻蚀所述外延结构层300的表面，在所述微米级孔洞311的底部形成亚微米级孔洞312。
最后，执行步骤S6，在所述外延结构层的表面形成N电极。
如图7所示，在本实施例的一个优选方案中，形成N电极800之前，还包括对外延结构层300的表面进行表面粗化的过程，粗化后，在N型GaN层310表面的多个微米级孔洞311之间，形成多个凸起结构313。如图8所示，此时在所述外延结构层300的表面形成N电极800。
具体的，所述粗化采用湿法刻蚀工艺，溶液可以为KOH、H3PO4等。形成N电极800的工艺为蒸镀，所述N电极800的材质为Ni/Au合金、Al/Ti/Pt/Au合金或Cr/Pt/Au合金等。
如前所述，本发明提供的具有特殊粗化形貌的LED垂直芯片结构的制造方法具有一优选方案，此方案涉及对衬底整体处理的工艺过程，因此考虑到了所述LED垂直芯片结构之间沟槽的处理。LED垂直芯片结构间沟槽是在一块基底上形成多个上述LED垂直芯片结构后，不同器件之间的间隙。在此方案中，所述非故意掺杂层200的表面形成微米级孔洞后，需要将微米级孔洞转移至外延结构层300上，并在外延结构层300上形成亚微米级孔洞，即在对衬底整体处理的工艺过程之中，从图5表面到形成图6表面的过程。此过程可通过两种方式实现，下面详细说明两种方法的实现过程。
方法一：
如图5所示，在剥离所述生长衬底100后，微米级孔洞210形成于非故意掺杂层200上。
请参考图9A，此时，干法刻蚀所述非故意掺杂层200的表面以去除所述非故意掺杂层200，并将存在于非故意掺杂层200上的所述微米级孔洞210转移至所述外延结构层300的表面。较佳的，所述外延结构层300的厚度是5μm-8μm，所述非故意掺杂层200的厚度为1μm-3μm，干法刻蚀约30min，即可去除1μm-3μm厚的非故意掺杂层200。形成的器件形貌如图12所示。图12为图9A所示步骤中器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
之后，请参考图9B，在所述外延结构层300的表面沉积二氧化硅层10。如前所述，由于化学气相淀积工艺的特点，在充满微米级孔洞的外延结构层300的表面形成的二氧化硅层会集中于所述微米级孔洞之间的部分，而在所述微米级孔洞的底部沉积的二氧化硅相对较少。较佳的，在所述外延结构层300的表面沉积的二氧化硅层10厚度为1000nm-2000nm，所述二氧化硅层10的厚度即所述微米级孔洞之间部分上的二氧化硅层10厚度。
请参考图9C，通过光刻去除LED垂直芯片结构间沟槽处的二氧化硅层10，在所述沟槽处露出所述外延结构层300，仅在LED垂直芯片结构的上方保留二氧化硅层，即二氧化硅层10’。LED垂直芯片结构间沟槽是在一块基底上形成多个上述LED垂直芯片结构后，不同器件之间的间隙。
所述光刻的方法是，在所述二氧化硅层10上形成光刻胶层，对所述光刻胶层进行曝光显影形成图案化的光刻胶层，所述图案化的光刻胶层暴露所述沟槽部分的二氧化硅层10，然后以所述图案化的光刻胶层为掩膜，刻蚀所述二氧化硅层10，在所述沟槽部分的露出外延结构层300，再去除剩余的光刻胶层，形成如图9C所示的结构。其中，湿法刻蚀所述二氧化硅层 10采用BOE溶液。
请参考图9D，对所述外延结构层300和二氧化硅层10’同时进行干法刻蚀，通过对工艺的控制，实现在所述沟槽处露出所述接触层400，并同时在所述微米级孔洞311的底部形成亚微米级孔洞312的目的。形成亚微米级孔洞312后，在微米级孔洞311之间仍有部分二氧化硅层10”未被完全刻蚀，起到了保护下方外延结构层300的作用。
最后，通过BOE溶液湿法刻蚀去除所述二氧化硅层10”，得到如图6表面所示的结构，即在外延结构层300上形成微米级孔洞311及亚微米级孔洞312，并去除所述二氧化硅层10”。此种方法形成的器件形貌如图13A所示。图13A为通过图9A-图9D所示形成方法形成的器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
方法二：
如图5所示，在剥离所述生长衬底100后，微米级孔洞210形成于非故意掺杂层200上。
请参考图10A，此时，在所述非故意掺杂层200表面沉积二氧化硅层20。优选方案中，所述外延结构层300的厚度是5μm-8μm，所述非故意掺杂层200的厚度为1μm-3μm，在所述非故意掺杂层300的表面沉积二氧化硅层20厚度的最大值为500nm-1000nm，所述厚度的最大值即所述微米级孔洞之间部分上的二氧化硅层20厚度。
请参考图10B，通过光刻去除LED垂直芯片结构间沟槽处的二氧化硅层20，在所述沟槽处露出所述非故意掺杂层200，仅在LED垂直芯片结构的上方保留二氧化硅层，即二氧化硅层20’。
所述光刻的方法是，在所述二氧化硅层20上形成光刻胶层，对所述光刻胶层进行曝光显影形成图案化的光刻胶层，所述图案化的光刻胶层暴露所述沟槽部分的二氧化硅层20，然后以所述图案化的光刻胶层为掩膜，刻 蚀所述二氧化硅层20，在所述沟槽部分的露出非故意掺杂层200，再去除剩余的光刻胶层，形成如图10B所示的结构。其中，湿法刻蚀所述二氧化硅层20采用BOE溶液。
然后，对所述二氧化硅层20’以及在所述沟槽处露出的所述非故意掺杂层300同时进行干法刻蚀，通过对工艺的控制，实现在所述沟槽处露出所述接触层400的同时，在非所述沟槽处(LED垂直芯片结构上方)去除所述二氧化硅层20’和所述非故意掺杂层200，在所述外延结构层300的表面形成所述微米级孔洞311并在所述微米级孔洞的底部形成亚微米级孔洞312的目的，得到如图6表面所示的结构。此种方法形成的器件具体形貌如图13B所示。图13B为通过图10A-图10B所示形成方法形成的器件在SEM电子显微镜中的俯视图(左)和侧视图(右)。
此方法形成二氧化硅层20的步骤在去除非故意掺杂层200之前，通过干法刻蚀能在形成微米级孔洞311和亚微米级孔洞312的同时去除所有二氧化硅层20，省去了后续去除二氧化硅的步骤，方便快捷。但对工艺控制的要求较细，刻蚀出的亚微米级孔洞312也不如方法一精细。
本发明提供的具有特殊粗化形貌的LED垂直芯片结构在外延结构层的表面具有微米型孔洞以及位于微米性孔洞底部的亚微米级孔洞，此种出光面结构能增加器件内部光的出射几率，大大提高出光效率和质量。本发明提供的上述LED垂直芯片结构的制造方法通过剥离带微米级凸起的生长衬底，在外延结构层上形成微米级孔洞，并通过刻蚀在微米级孔洞的底部形成亚微米级孔洞，此方法工艺简单，可用于大规模的工业生产，且能够大大提高垂直结构LED发光效率。
显然，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包括这些改动和变型在内。

Claims (13)

  1. 一种具有特殊粗化形貌的LED垂直芯片结构，其特征在于，包括：
    导电支撑衬底；
    金属键合电极层，形成于所述导电支撑衬底的表面；
    金属反射电极层，形成于所述金属键合电极层的表面；
    接触层，形成于所述金属反射电极层的表面；
    外延结构层，形成于所述接触层的表面，所述外延结构层包括P型GaN层、N型GaN层以及形成于所述P型GaN层和N型GaN层中间的有源区层，其中，在所述外延结构层的表面具有微米级孔洞以及位于所述微米级孔洞底部的亚微米级孔洞；
    N电极，结合于所述外延结构层的表面。
  2. 如权利要求1所述的LED垂直芯片结构，其特征在于，所述微米级孔洞的孔径为2μm-3μm，深度为1μm-3μm；所述亚微米级孔洞的孔径为300nm-800nm,深度为1μm-2μm。
  3. 如权利要求1所述的LED垂直芯片结构，其特征在于，所述金属键合电极层的材质为Au-Sn共晶。
  4. 如权利要求1所述的LED垂直芯片结构，其特征在于，所述金属反射电极层的材质为Ag。
  5. 如权利要求1所述的LED垂直芯片结构，其特征在于，所述接触层的材质为ITO或Ni。
  6. 一种具有特殊粗化形貌的LED垂直芯片结构的制备方法，其特征在于，包括:
    提供生长衬底，在所述生长衬底表面刻蚀形成微米级凸起，然后在所述生长衬底上形成外延结构层；
    在所述外延结构层上依次形成接触层、金属反射电极层和金属键合电极层；
    在所述金属键合电极层上形成导电支撑衬底；
    剥离所述生长衬底，以在所述外延结构层的表面形成微米级孔洞；
    刻蚀所述外延结构层的表面，在所述微米级孔洞的底部形成亚微米级孔洞；
    在所述外延结构层的表面形成N电极。
  7. 如权利要求6所述的LED垂直芯片结构的制备方法，其特征在于，刻蚀所述外延结构层的表面的步骤包括：
    在所述外延结构层的表面沉积二氧化硅层；
    以所述二氧化硅层作掩膜进行干法刻蚀，以在所述微米级孔洞的底部形成亚微米级孔洞；
    去除剩余的所述二氧化硅层。
  8. 如权利要求6所述的LED垂直芯片结构的制备方法，其特征在于：
    在所述生长衬底表面刻蚀形成微米级凸起后，先在所述生长衬底表面形成非故意掺杂层，再在所述非故意掺杂层表面形成外延结构层；
    在剥离所述生长衬底后，先在所述非故意掺杂层的表面形成微米级孔洞，再刻蚀去除所述非故意掺杂层并将所述微米级孔洞转移至所述外延结构层，最后刻蚀所述外延结构层的表面，以在所述微米级孔洞的底部形成亚微米级孔洞。
  9. 如权利要求8所述的LED垂直芯片结构的制备方法，其特征在于，在所述非故意掺杂层的表面形成微米级孔洞后，通过以下步骤形成亚微米级孔洞：
    干法刻蚀所述非故意掺杂层的表面以去除所述非故意掺杂层，并将所述微米级孔洞转移至所述外延结构层的表面；
    在所述外延结构层的表面沉积二氧化硅层；
    通过光刻和刻蚀工艺去除LED器件间沟槽处的二氧化硅层，在所述沟槽处露出所述外延结构层；
    对所述外延结构层和二氧化硅层同时进行干法刻蚀，在所述沟槽处露出所述接触层，并在所述微米级孔洞的底部形成亚微米级孔洞；
    去除所述二氧化硅层。
  10. 如权利要求9所述的LED垂直芯片结构的制备方法，其特征在于，所述外延结构层的厚度是5μm-8μm，所述非故意掺杂层的厚度为1μm-3μm，在所述外延结构层的表面沉积的二氧化硅层厚度为1000nm-2000nm。
  11. 如权利要求8所述的LED垂直芯片结构的制备方法，其特征在于，在所述非故意掺杂层的表面形成微米级孔洞后，通过以下步骤形成亚微米级孔洞：
    在所述非故意掺杂层表面沉积二氧化硅层；
    通过光刻和刻蚀工艺去除LED器件间沟槽处的二氧化硅层，在所述沟槽处露出所述非故意掺杂层；
    对所述二氧化硅层以及在所述沟槽处露出的所述非故意掺杂层同时进行干法刻蚀，在所述沟槽处露出所述接触层，同时在非所述沟槽处去除所述二氧化硅层和所述非故意掺杂层后，在所述外延结构层的表面形成所述微米级孔洞并在所述微米级孔洞的底部形成亚微米级孔洞。
  12. 如权利要求11所述的LED垂直芯片结构的制备方法，其特征在于，所述外延结构层的厚度是5μm-8μm，所述非故意掺杂层的厚度为1μm-3μm，在所述非故意掺杂层表面沉积二氧化硅层的厚度为500nm-1000nm。
  13. 如权利要求6所述的LED垂直芯片结构的制备方法，其特征在于，在形成N电极之前，还包括对所述外延结构层的表面进行表面粗化的过程。
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