WO2023060515A1 - 微型发光二极管芯片及显示装置 - Google Patents

微型发光二极管芯片及显示装置 Download PDF

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WO2023060515A1
WO2023060515A1 PCT/CN2021/123900 CN2021123900W WO2023060515A1 WO 2023060515 A1 WO2023060515 A1 WO 2023060515A1 CN 2021123900 W CN2021123900 W CN 2021123900W WO 2023060515 A1 WO2023060515 A1 WO 2023060515A1
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semiconductor layer
type semiconductor
emitting diode
micro
diode chip
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PCT/CN2021/123900
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English (en)
French (fr)
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徐宸科
谢相伟
刘同凯
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厦门市芯颖显示科技有限公司
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Priority to PCT/CN2021/123900 priority Critical patent/WO2023060515A1/zh
Publication of WO2023060515A1 publication Critical patent/WO2023060515A1/zh
Priority to US18/392,121 priority patent/US20240128244A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the invention relates to the technical field of solid-state light-emitting devices, in particular to a miniature light-emitting diode chip and a display device using the miniature light-emitting diode chip.
  • Micro-LED chips generally refer to semiconductor light-emitting diode chips whose length, width, and thickness are all less than 100 micrometers ( ⁇ m).
  • the related technology uses the traditional patterned sapphire substrate (Patterned Sapphire Substrate, PSS) process to make the Micro-LED chip; but in laser lift-off (Laser Lift-off, LLO)
  • PSS Patterned Sapphire Substrate
  • LLO Laser Lift-off
  • the required laser energy is high and the process window is small, which easily leads to low laser lift-off yield, or chip damage or cracking.
  • embodiments of the present invention provide a micro LED chip and a display device using the micro LED chip.
  • a micro light-emitting diode chip proposed by an embodiment of the present invention includes an epitaxial structure; wherein, the epitaxial structure includes a first doping type semiconductor layer, a second doping type semiconductor layer, and a an active layer between the doping type semiconductor layer and the second doping type semiconductor layer, a patterned structure is provided on the light emitting side of the first doping type semiconductor layer away from the active layer, and the The long side a of the micro-LED chip, the thickness b of the micro-LED chip, and the peak-to-valley height difference c of the patterned structure satisfy the conditions: 0.01 ⁇ b/a ⁇ 6, and 0.01 ⁇ c/b ⁇ 0.3 .
  • the peak-valley height difference c of the patterned structure satisfies the condition: c ⁇ 1 ⁇ m.
  • the peak-valley height difference c of the patterned structure satisfies the condition: 0.1 ⁇ m ⁇ c ⁇ 1 ⁇ m.
  • the peak-valley height difference c of the patterned structure satisfies the condition: c ⁇ 0.1 ⁇ m.
  • the long side a of the micro LED chip is less than 100 ⁇ m, and the thickness b of the micro LED chip is less than 20 ⁇ m.
  • the patterned structure is a two-dimensional photonic crystal structure.
  • the peak-valley height difference of the patterned structure is less than or equal to 1.5 ⁇ m.
  • the patterned structure is arranged on the first doping type semiconductor layer far away from the active layer by using a growth substrate formed with a patterned structure through pattern transfer. Describe the light side.
  • the patterned structure is disposed on the light-exiting side of the first doped type semiconductor layer away from the active layer by dry etching after laser lift-off of the growth substrate. .
  • a miniature light-emitting diode chip which includes an epitaxial structure that has removed the growth substrate and is not supported by a bonding substrate.
  • the epitaxial structure includes a first doped type semiconductor layer, a second doped semiconductor layer, heterotype semiconductor layer, and an active layer located between the first doping type semiconductor layer and the second doping type semiconductor layer, the part of the first doping type semiconductor layer far away from the active layer
  • the light-emitting side is provided with a patterned structure, and the peak-valley height difference of the patterned structure is less than 1 micron, the long side of the micro-LED chip is less than 100 microns, and the thickness of the micro-LED chip is less than or equal to 10 microns , and the thickness b of the micro LED chip and the peak-valley height difference c of the patterned structure satisfy the condition: 0.01 ⁇ c/b ⁇ 0.3.
  • a display device proposed by an embodiment of the present invention includes: a circuit substrate provided with a plurality of electrode structures, and each of the electrode structures includes electrodes arranged in pairs;
  • the micro light emitting diode chip is arranged on the circuit substrate and electrically connected with the plurality of electrode structures respectively.
  • the structural size and/or shape of the micro light-emitting diode chip 100 for example, designing the peak-to-valley height difference of the patterned structure to satisfy the condition 0.01 ⁇ c/b ⁇ 0.3, it can even be With the photonic crystal design, the light extraction efficiency can be optimized, so that the power of laser stripping can be reduced, the process window can be enlarged, the chip can not be damaged, and the light extraction efficiency can be improved.
  • FIG. 1 is a schematic structural diagram of a micro LED chip according to the first embodiment of the present invention.
  • 2A-2E are schematic structural diagrams of a manufacturing method of a miniature LED chip related to the first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a micro LED chip according to the second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a display device according to a third embodiment of the present invention.
  • a kind of miniature light-emitting diode chip 100 that the first embodiment of the present invention provides it comprises the epitaxial structure (epitaxial structure) 110 that has removed growth substrate (growth substrate) and has no bonding substrate support, and the bond here
  • the bonded substrate generally refers to a substrate that is connected to an epitaxial structure through a bonding process (such as a metal bonding process).
  • the epitaxial structure 110 includes: a first doping type semiconductor layer 112 , a second doping type semiconductor layer 116 and a semiconductor layer between the first doping type semiconductor layer 112 and the second doping type semiconductor layer 116
  • the active layer 114 is such as a multiple quantum well (multiple quantum well, MQW) layer, and the side of the first doping type semiconductor layer 112 away from the active layer 114 (that is, the light emitting side of the micro light emitting diode chip 100 ) is provided with a patterned structure 113 such as an array of microstructures.
  • the micro light emitting diode 100 of this embodiment is also provided with a first electrode electrically connected to the first doping type semiconductor layer 112 ( FIG. 1 not shown) and the second electrode (not shown in FIG. 1 ) which is electrically connected to the second doping type semiconductor layer 116, it is only for the convenience of describing the epitaxy with the patterned structure 113 in this embodiment of the present invention. structure 110, the detailed description of the first electrode and the second electrode will be omitted below.
  • the epitaxial structure 110 of this embodiment can also add other functional layers according to actual needs, such as unintentionally doped gallium nitride layer (u-GaN), located in The stress release layer between the N-type semiconductor layer and the multi-quantum well layer, the electron blocking layer (EBL, Electron Blocking Layer) between the multi-quantum well layer and the P-type semiconductor layer, etc., the embodiments of the present invention are not based on this limit.
  • u-GaN unintentionally doped gallium nitride layer
  • EBL Electron Blocking Layer
  • the first doping type semiconductor layer 112 is, for example, an N-type GaN (gallium nitride, gallium nitride) layer
  • the second doping type semiconductor layer 116 is, for example, a P-type GaN layer
  • the active layer 114 is, for example, an InGaN/GaN multiple quantum well layer.
  • the miniature light-emitting diode chip 100 of this embodiment is not limited to the blue light Micro-LED chip, and it can also be other color light Micro-LED chips, such as green light Micro-LED chips, red light Micro-LED chips, etc., correspondingly
  • the composition and materials of each layer in the epitaxial structure 110 need to be adjusted, but it is an existing mature technology, so it will not be repeated here.
  • the micro light emitting diode chip 100 design the structural size and/or shape of the micro light emitting diode chip 100, such as the The long side a of the micro-LED chip 100 (such as the length a in the X direction in FIG. 1 ), the thickness b of the micro-LED chip 100 (that is, the height in the Z direction in FIG. 1 , not marked) and the pattern The peak-to-valley height difference c of the chemical structure 113 (that is, the height c in the Z direction in FIG.
  • b is defined as a micro light-emitting diode chip
  • the overall thickness of 100 in the Z direction, b/a mainly describes the size specifications of the micro-LED chip 100 itself (typically, b/a ⁇ 1), and the value of the thickness b can be determined by the thickness of the epitaxial structure 110, The electrode thickness of the micro LED chip 100 and the etching depth of the semiconductor layer (such as Mesa etching depth) are determined.
  • the condition 0.01 ⁇ b/a ⁇ 6 means that the long side a of the micro LED chip 100 can be greater than the thickness b (for example, 0.01 ⁇ b/a ⁇ 1) so that the shape of the micro LED chip 100 looks relatively long but relatively thin Therefore, it is beneficial to the thinning of the display device using this kind of micro light emitting diode chip 100, and it can also be smaller than the thickness b (for example, 1 ⁇ b/a ⁇ 3) so that the shape of the micro light emitting diode chip 100 looks relatively short but relatively Thickness is beneficial to achieve high pixel density in a display device using this kind of micro LED chip 100 .
  • the condition of 0.01 ⁇ c/b ⁇ 0.3 can prevent the micro-LED chip 100 from being easily damaged due to the large height difference of the surface roughening, and at the same time ensure the effect of improving the light extraction efficiency.
  • the specific size of the peak-valley height difference c of the patterned structure 113 is set to be less than or equal to 1.5 ⁇ m, more preferably sub-micron or even nano-scale, where the sub-micron refers to the patterned
  • the peak-to-valley height difference c of the structure 113 (that is, the height difference in the Z direction in Figure 1, or the surface roughening height difference) satisfies the condition: 0.1 ⁇ m ⁇ c ⁇ 1 ⁇ m, and the nanoscale here refers to the pattern
  • the peak-valley height difference c of the chemical structure 113 satisfies the condition: c ⁇ 0.1 ⁇ m (that is, less than 100 nanometers).
  • a ⁇ 100 ⁇ m may even be less than 10 ⁇ m
  • b ⁇ 20 ⁇ m more specifically, b ⁇ 10 ⁇ m
  • the thickness of the epitaxial structure 110 is less than 10 ⁇ m (Specifically, it may be 2 ⁇ 6 ⁇ m, such as 3 ⁇ 5 ⁇ m), but the embodiments of the present invention are not limited thereto.
  • each microstructure in the patterned structure 113 can be striped, dome, columnar, etc., and there is no specific limitation here, as long as it can break the total reflection to improve the microstructure.
  • the light extraction efficiency (or called light extraction efficiency) of the light emitting diode chip 100 can be any.
  • micro light emitting diode chip 100 of this embodiment an exemplary manufacturing method of the micro light emitting diode chip 100 of this embodiment is briefly described below taking the blue light Micro-LED chip as an example, specifically:
  • a patterned sapphire substrate 200 is used as a growth substrate, where the patterned sapphire substrate 200 refers to a sapphire substrate with a patterned structure 202 formed on its surface.
  • a buffer layer 1121 on the surface of the patterned sapphire substrate 200 where the patterned structure 202 is formed, a buffer layer 1121, an N-type semiconductor layer 1120, an active layer 1140 (such as an MQW layer) and a P type semiconductor layer 1160 .
  • Micro-LED chip (COW, chip on wafer) production is carried out, for example, using ICP (Inductive Coupled Plasma, inductively coupled plasma) dry etching method to first perform Mesa structure production and then Isolation (isolation) structure production, which can be specifically : Utilize ICP to etch the P-type semiconductor layer 1160 and the active layer 1140 until part of the N-type semiconductor layer 1120 is removed to form a mesa structure (mesa structure) thereby exposing part of the N-type semiconductor layer 1120, after that Then use ICP to etch the patterned blu-ray stone substrate 200 to form an Isolation structure to define a plurality of Micro-LED chips. Of course, you can also make the Isolation structure first and then the Mesa structure.
  • ICP Inductive Coupled Plasma, inductively coupled plasma
  • the Mesa structure and the Isolation structure After forming the Mesa structure and the Isolation structure, form electrical connections with the N-type semiconductor layer 1120 (corresponding to the first doping type semiconductor layer 112) and the P-type semiconductor layer 1160 (corresponding to the second doping type semiconductor layer 116), for example
  • the N electrode 118a and the P electrode 118b are in ohmic contact, as shown in FIG. 2C.
  • the aforementioned COW structure formed with the Mesa structure, the Isolation structure, the N electrode 118 a and the P electrode 118 b is temporarily fixed to the temporary substrate 400 by using micro-adhesive glue, as shown in FIG. 2D .
  • the patterned sapphire substrate 200 is removed by laser lift-off, and the buffer layer 1121 is ablated by the laser at the same time, and then a plurality of Micro-LED chips temporarily fixed with the temporary substrate 400 can be obtained, that is, temporarily fixed with the temporary substrate 400
  • a plurality of fixed miniature LED chips 100 as shown in FIG. 2E; it should be noted here that the miniature LED chips 100 shown in FIG. 2E are the same components as the miniature LED chips 100 shown in FIG.
  • the micro LED chip 100 shown in FIG. 1 omits the drawing of the N electrode 118a and the P electrode 118b.
  • the negative pattern of the patterned structure 202 of the patterned sapphire substrate 200 is transferred to the light-emitting side of the N-type semiconductor layer (first doping type semiconductor layer 112) to form the pattern
  • the patterned structure 113 (as shown in FIG. 1 or 2E ), and the peak-to-valley height difference of the patterned structure 113 is preferably less than or equal to 1.5 ⁇ m, more preferably submicron or nanometer.
  • the patterned structure 113 is integrated with the N-type semiconductor layer 112, that is, the patterned structure 113 is directly formed on the N-type semiconductor layer 112 and has the same material. .
  • a micro light-emitting diode chip 300 provided in the second embodiment of the present invention includes an epitaxial structure 310 from which the growth substrate has been removed and which is not supported by a bonding substrate.
  • the epitaxial structure 310 includes: a first doping type semiconductor layer 312, a second doping type semiconductor layer 316, and a semiconductor layer located between the first doping type semiconductor layer 312 and the second doping type semiconductor layer 316
  • the active layer 314 is such as a multi-quantum well layer, and the side of the first doping type semiconductor layer 312 away from the active layer 314 (that is, the light emitting side of the micro light emitting diode chip 300) is provided with a patterned structure 313 For example, two-dimensional photonic crystal structure.
  • the micro light emitting diode 300 of this embodiment is also provided with a first electrode electrically connected to the first doping type semiconductor layer 312 ( FIG. 3 not shown) and the second electrode (not shown in FIG. 3 ) that is electrically connected to the second doping type semiconductor layer 316, it is only for the convenience of describing the epitaxial structure with the patterned structure 313 in this embodiment of the present invention.
  • structure 310 the detailed description of the first electrode and the second electrode (refer to the N electrode 118a and the P electrode 118b in FIG. 2E) will be omitted below.
  • the epitaxial structure 310 of this embodiment can also add other functional layers according to actual needs, such as unintentionally doped gallium nitride layer (u-GaN), located in
  • u-GaN unintentionally doped gallium nitride layer located in
  • the embodiment of the present invention is not limited to the stress release layer between the N-type semiconductor layer and the multi-quantum well layer, the electron blocking layer between the multi-quantum well layer and the P-type semiconductor layer, and the like.
  • the first doping type semiconductor layer 312 is, for example, an N-type GaN layer
  • the second doping type semiconductor layer 316 is, for example, a P-type GaN layer
  • the active layer 314 is, for example, It is an InGaN/GaN multiple quantum well layer.
  • the miniature light-emitting diode chip 300 of this embodiment is not limited to the blue light Micro-LED chip, and it can also be other color light Micro-LED chips, such as green light Micro-LED chips, red light Micro-LED chips, etc., correspondingly
  • the composition and materials of each layer in the epitaxial structure 310 need to be adjusted, but it is an existing mature technology, so it will not be repeated here.
  • the structural size and/or shape of the micro light emitting diode chip 300 is designed, for example, the long side a of the micro light emitting diode chip 300 (such as the length a in the X direction in FIG. 3 ), the The thickness b of the micro light emitting diode chip 300 (that is, the height in the Z direction in FIG.
  • the peak-valley height difference c that is, the The height c in the Z direction satisfies the conditions: 0.01 ⁇ b/a ⁇ 6, 0.01 ⁇ c/b ⁇ 0.3; where b is defined as the overall thickness of the micro-LED chip 300 in the Z direction, and b/a mainly indicates the micro The dimensions of the light emitting diode chip 300 itself (typically, b/a ⁇ 1), and the value of the thickness b can be determined by the thickness of the epitaxial structure 310, the electrode thickness of the micro light emitting diode chip 300, the etching depth of the semiconductor layer (such as Mesa Etching depth) to determine.
  • the condition 0.01 ⁇ b/a ⁇ 6 means that the long side a of the micro LED chip 300 can be greater than the thickness b (for example, 0.01 ⁇ b/a ⁇ 1) so that the shape of the micro LED chip 300 looks longer but thinner Therefore, it is beneficial to the thinning of the display device using this kind of micro light emitting diode chip 300, and it can also be smaller than the thickness b (for example, 1 ⁇ b/a ⁇ 3) so that the shape of the micro light emitting diode chip 300 looks relatively short but relatively Thickness is beneficial to achieve high pixel density in a display device using this kind of micro LED chip 300 .
  • the condition of 0.01 ⁇ c/b ⁇ 0.3 can prevent the micro LED chip 300 from being easily damaged due to the large difference in height of the surface roughening, and at the same time ensure the effect of improving the light extraction efficiency.
  • the specific size of the peak-valley height difference of the patterned structure 313 is set to be less than or equal to 1.5 ⁇ m, more preferably sub-micron or even nano-scale, here the sub-micron It means that the peak-to-valley height difference c of the patterned structure 313 (that is, the height difference in the Z direction in FIG. The level refers to that the peak-valley height difference c of the patterned structure 313 satisfies the condition: c ⁇ 0.1 ⁇ m.
  • its lattice type can be a square lattice, a triangular lattice, or a honeycomb lattice, etc., and there is no specific limitation here, as long as it can enhance the micro-LED chip 300 The light extraction efficiency can be achieved. It is worth explaining here that the photonic crystal structure has photon energy levels, which can improve the light extraction efficiency, and can also change/control the light type (light output direction) and control the light wavelength band according to requirements.
  • micro light emitting diode chip 300 of this embodiment an exemplary manufacturing method of the micro light emitting diode chip 300 of this embodiment is briefly described below taking the blue light Micro-LED chip as an example, specifically:
  • a sapphire substrate with a two-dimensional photonic crystal structure is produced, specifically: a silicon dioxide layer is deposited on the sapphire substrate by CVD process, and a two-dimensional photonic crystal is formed on the silicon dioxide layer by electron beam exposure technology
  • the unintentionally doped GaN layer (u-GaN), N-type GaN layer, InGaN/GaN multiple quantum well layer and P-type GaN layer were epitaxially grown sequentially on the sapphire substrate formed with a two-dimensional photonic crystal structure, where u -GaN first fills the periodically distributed micropore area.
  • the Micro-LED chip (COW) is produced, for example, the Mesa structure is firstly produced by ICP dry etching method and then the Isolation structure is produced. Specifically, the P-type GaN layer and the InGaN/GaN multilayer are etched by ICP The quantum well layer is removed until part of the N-type GaN layer is removed to form a mesa structure to expose part of the N-type GaN layer, and then etched to the bluite substrate by ICP to form an Isolation structure to define multiple Micro-LED chips . Of course, you can also make the Isolation structure first and then the Mesa structure. After forming the Mesa structure and the Isolation structure, an N electrode and a P electrode respectively electrically connected to the N-type GaN layer and the P-type GaN layer are formed.
  • micro-adhesive glue to temporarily fix the aforementioned COW structure formed with the Mesa structure, Isolation structure and N-P electrodes to the temporary substrate.
  • the 248nm KrF excimer laser is used to lift off the sapphire substrate to expose the coexistence interface of silicon dioxide and u-GaN;
  • etching is used to simultaneously remove the u-GaN layer and the silicon dioxide layer in the exposed area until the N-type GaN layer is etched.
  • the silicon layer is used as a mask layer to form a patterned structure 313 as shown in FIG. 3 on the light-emitting side of the N-type GaN layer (first doping type semiconductor layer 312), so that it can be temporarily fixed with the temporary substrate and provided with a patterned structure.
  • the pattern of the two-dimensional photonic crystal of the sapphire substrate formed with the two-dimensional photonic crystal structure is transferred to the u-GaN layer on the light-emitting side of the N-type GaN layer, and the patterned structure
  • the peak-to-valley height difference of 313 is less than or equal to 1.5 ⁇ m, preferably submicron or nanometer.
  • the patterned structure 313 (two-dimensional photonic crystal structure) and the N-type GaN layer (corresponding to the first doping type semiconductor layer 312 ) are two layer structures in contact with each other.
  • a growth substrate such as a sapphire substrate
  • a patterned structure on the surface is used to manufacture the micro light-emitting diode chip 100/300, so as to transfer the pattern of the patterned structure on the surface of the growth substrate
  • the patterned structure 113/313 located on the light-emitting side of the micro-LED chip 100/300 is obtained by pattern transfer;
  • the embodiment of the present invention does not use
  • the adoption of the dry etching method here can avoid technical problems such as the need to use strong acid and strong alkali potion for surface roughening in related technologies, resulting in damage to the micro-adhesive glue, which will easily cause the chip to fall off, which is not conducive to the subsequent chip transfer process.
  • the light extraction efficiency of the miniature light-emitting diode chip is improved.
  • the exemplary manufacturing method of the foregoing embodiments of the present invention is described by making flip-chip Micro-LED chips as an example, but the miniature light-emitting diode chips of the embodiments of the present invention are not limited to flip-chip Micro-LED chips , which can also be a Micro-LED chip with a vertical structure, that is, the P electrode and the N electrode are respectively located above and below the Micro-LED chip.
  • FIG. 4 is a schematic structural diagram of a display device according to a third embodiment of the present invention.
  • the display device 40 includes a circuit substrate 41 and a plurality of (only three are shown in FIG. 4 as an example) micro light emitting diode chips 43 .
  • the circuit substrate 41 is provided with a plurality (only three are shown as an example in FIG. 4 ) of electrode structures, and each of the electrode structures includes electrodes 411 and 413 arranged in pairs;
  • the chip 43 is disposed on the circuit substrate 41 and electrically connected to the plurality of electrode structures respectively.
  • the circuit substrate 41 is, for example, a complementary metal-oxide semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) substrate, a liquid crystal on silicon (Liquid Crystal on Silicon, LCOS) substrate, a thin film transistor (Thin Film Transistor, TFT ) substrate or other substrates with working circuits, which are not limited here;
  • the plurality of miniature light-emitting diode chips 43 can adopt the same color Micro-LED chip, or adopt multiple different colors (such as R, G, B) Micro-LED chips; each of the micro light emitting diode chips 43 is, for example, the micro light emitting diode chip 100 of the foregoing first embodiment or the micro light emitting diode chip 300 of the foregoing second embodiment, which has an N electrode 43a and a P electrode 43b , and the N electrode 43 a and the P electrode 43 b are respectively electrically connected to the electrodes 411 and 413 in the corresponding electrode structure through the solder 42 .
  • the micro light-emitting diode chip 43 when the micro light-emitting diode chip 43 is replaced by a vertical structure Micro-LED chip from the flip-chip Micro-LED chip shown in FIG. 4 , one of its N electrode and P electrode One can be electrically connected to one of the electrodes 411 and 413 in the electrode structure by soldering, and the other can be electrically connected to the other of the electrodes 411 and 413 in the electrode structure by wire bonding. It is worth noting that the display device 40 of this embodiment can achieve higher display brightness or lower power consumption by using micro light-emitting diode chips with higher light extraction efficiency.

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Abstract

本发明公开一种微型发光二极管芯片，例如包括外延结构。所述外延结构包括第一掺杂类型半导体层、第二掺杂类型半导体层、和位于第一掺杂类型半导体层与第二掺杂类型半导体层之间的有源层，第一掺杂类型半导体层之远离有源层的出光侧设置有图案化结构，以及微型发光二极管芯片的长边a、微型发光二极管芯片的厚度b与图案化结构的峰-谷高度差c满足条件：0.01≤b/a≤6、且0.01≤c/b≤0.3。本发明通过对微型发光二极管芯片的结构尺寸和/或形状进行设计，例如将图案化结构的峰-谷高度差进行设计成满足条件0.01≤c/b≤0.3，从而可以使得激光剥离的功率下降、工艺窗口加大且具有提升光取出效率的作用。本发明还提供采用所述微型发光二极管芯片的显示装置。

Description

微型发光二极管芯片及显示装置 技术领域
本发明涉及固态发光器件技术领域，尤其涉及一种微型发光二极管芯片以及采用该种微型发光二极管芯片的显示装置。
背景技术
微型发光二极管(Micro-LED)芯片通常是指其长度(length)、宽度(width)、厚度(thickness)均小于100微米(μm)的半导体发光二极管芯片。为打破全反射以提升Micro-LED芯片的光取出效率(或称出光效率)，相关技术有采用传统图案化蓝宝石衬底(Patterned Sapphire Substrate，PSS)工艺来制作Micro-LED芯片；但是在激光剥离(Laser Lift-off，LLO)传统图案化蓝宝石衬底的过程中，其所需的激光能量较高且工艺窗口小，进而容易导致激光剥离良率低、或是芯片损坏或破裂。
发明内容
因此，为克服现有技术存在的至少部分缺陷与不足，本发明实施例提供一种微型发光二极管芯片以及采用该种微型发光二极管芯片的显示装置。
具体地，本发明一个实施例提出的一种微型发光二极管芯片，包括外延结构；其中，所述外延结构包括第一掺杂类型半导体层、第二掺杂类型半导体层、和位于所述第一掺杂类型半导体层与所述第二掺杂类型半导体层之间的有源层，所述第一掺杂类型半导体层之远离所述有源层的出光侧设置有图案化结构，以及所述微型发光二极管芯片的长边a、所述微型发光二极管芯片的厚度b与所述图案化结构的峰-谷高度差c满足条件：0.01≤b/a≤6、且0.01≤c/b≤0.3。
在本发明的一个实施例中，所述图案化结构的所述峰-谷高度差c满足条件：c<1μm。
在本发明的一个实施例中，所述图案化结构的所述峰-谷高度差c满足条件：0.1μm≤c<1μm。
在本发明的一个实施例中，所述图案化结构的所述峰-谷高度差c满足条件：c<0.1μm。
在本发明的一个实施例中，所述微型发光二极管芯片的长边a小于100μm，微型发光二极管芯片的厚度b小于20μm。
在本发明的一个实施例中，所述图案化结构为二维光子晶体结构。
在本发明的一个实施例中，所述图案化结构的所述峰-谷高度差小于或等于1.5μm。
在本发明的一个实施例中，所述图案化结构为通过采用形成有图案化结构的生长衬底经由图形转移方式设置在所述第一掺杂类型半导体层之远离所述有源层的所述出光侧。
在本发明的一个实施例中，所述图案化结构为在激光剥离生长衬底后采用干法蚀刻方式设置在所述第一掺杂类型半导体层之远离所述有源层的所述出光侧。
再者，本发明另一实施例提出的一种微型发光二极管芯片，包括已去除生长衬底且无键合基板支撑的外延结构，所述外延结构包括第一掺杂类型半导体层、第二掺杂类型半导体层、和位于所述第一掺杂类型半导体层与所述第二掺杂类型半导体层之间的有源层，所述第一掺杂类型半导体层之远离所述有源层的出光侧设置有图案化结构、且所述图案化结构的峰-谷高度差小于1微米，所述微型发光二极管芯片的长边小于100微米，所述微型发光二极管芯片的厚度小于或等于10 微米，以及所述微型发光二极管芯片的所述厚度b与所述图案化结构的所述峰-谷高度差c满足条件：0.01≤c/b≤0.3。
另外，本发明实施例提出的一种显示装置，其包括：线路基板，设置有多个电极结构且每一个所述电极结构包括成对设置的电极；以及多个如前述任一实施例所述的微型发光二极管芯片，设置在所述线路基板上、且分别与所述多个电极结构形成电性连接。
由上可知，本发明实施例通过对微型发光二极管芯片100的结构尺寸和/或形状进行设计，例如将图案化结构的峰-谷高度差设计成满足条件0.01≤c/b≤0.3，甚至可以搭配光子晶体设计将取光效率做到最优化设计，从而可以使得激光剥离的功率下降、工艺窗口加大、不损伤芯片且具有提升光取出效率的作用。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施例的一种微型发光二极管芯片的结构示意图。
图2A-2E为相关于本发明第一实施例的微型发光二极管芯片的一种制作方法的过程结构示意图。
图3为本发明第二实施例的一种微型发光二极管芯片的结构示意图。
图4是本发明第三实施例的一种显示装置的结构示意图。
具体实施方式
为了使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图对 本发明实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本发明的部分实施例，而不是全部实施例。基于本发明描述的实施例，本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例，都属于本发明的保护范围。
需要说明，本发明实施例中所有方向性指示(诸如上、下、左、右、前、后)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
在本发明实施例中如涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。
【第一实施例】
参见图1，本发明第一实施例提供的一种微型发光二极管芯片100，其包括已去除生长衬底(growth substrate)且无键合基板支撑的外延结构(epitaxial structure)110，此处的键合基板通常是指通过键合工艺(例如金属键合工艺)与外延结构形成连接的基板。所述外延结构110包括：第一掺杂类型半导体层112、第二掺杂类型半导体层116和位于所述第一掺杂类型半导体层112与所述第二掺杂类型半导体层116之间的有源层114例如多量子阱(multiple quantum well，MQW)层，且所述第一掺杂类型半导体层112之远离所述有源层114的一侧(也即微型发光二极管芯片100的出光侧)设置有图案化结构113例如微结构阵列。当然，可以理解的是，本实施例的微型发光二极管100除了所述外延结构110之外，例如还设置有与所述第一掺杂类型半导体层112形成电性连接的第一电极(图1未绘出)和与所述第二掺杂类型半导体层116形成电性连接的第二电极(图1未绘出)， 只是本发明实施例为便于重点描述具有所述图案化结构113的外延结构110，下文将省略对第一电极和第二电极的具体描述。此外，值得一提的是，以蓝光Micro-LED芯片为例，本实施例的外延结构110还可以根据实际需要增设其他功能层，例如非有意掺杂氮化镓层(u-GaN)、位于N型半导体层与多量子阱层之间的应力释放层、位于多量子阱层与P型半导体层之间的电子阻挡层(EBL,Electron Blocking Layer)等，本发明实施例并不以此为限。
以蓝光Micro-LED芯片为例，所述第一掺杂类型半导体层112例如是N型GaN(gallium nitride，氮化镓)层，所述第二掺杂类型半导体层116例如是P型GaN层，所述有源层114例如是InGaN/GaN多量子阱层。当然，本实施例的微型发光二极管芯片100并不限于蓝光Micro-LED芯片，其也可以是其他颜色光Micro-LED芯片，例如绿光Micro-LED芯片、红光Micro-LED芯片等，相应地所述外延结构110中各个层的构成及材料需要做必要调整，但其为现有成熟技术，故在此不再赘述。
承上述，针对相关技术中采用传统图案化蓝宝石衬底(Patterned Sapphire Substrate，PSS)结构、且PSS结构上的微结构阵列的峰-谷高度差大于2.5μm之Micro-LED芯片制作工艺，其制作F-COC(Free-standing Chip on Carrier)结构时，需要使用微黏性胶将芯片表面微粘接以暂时固定、再使用激光剥离将衬底去除；在此过程中，因为传统PSS结构的表面微结构阵列的峰-谷高度差较大，需要激光剥离的激光能量较高且工艺窗口小，其容易导致激光剥离良率低、或是芯片损坏或破裂；本实施例为降低激光剥离的激光能量、增大工艺窗口以克服相关技术中容易出现的激光剥离良率低或是芯片损伤或破裂的技术问题，对所述微型发光二极管芯片100的结构尺寸和/或形状进行设计，例如所述微型发光二极管芯片 100的长边a(例如图1中X方向的长度a)、所述微型发光二极管芯片100的厚度b(也即图1中Z方向上的高度，未标示)与所述图案化结构113的峰-谷高度差c(也即图1中Z方向上的高度c)满足条件：0.01≤b/a≤6，0.01≤c/b≤0.3；其中b定义为微型发光二极管芯片100在Z方向上的整体厚度，b/a主要是说明微型发光二极管芯片100本身的尺寸规格(典型地，b/a≤1)，且厚度b的取值可藉由外延结构110的厚度、微型发光二极管芯片100的电极厚度、半导体层蚀刻深度(例如Mesa蚀刻深度)来决定。条件0.01≤b/a≤6表征所述微型发光二极管芯片100的长边a可以大于厚度b(例如0.01≤b/a<1)以使得微型发光二极管芯片100的形状看起来比较长但比较薄从而有利于采用该种微型发光二极管芯片100的显示装置的薄型化，也可以小于厚度b(例如1<b/a≤3)以使得所述微型发光二极管芯片100的形状看起来比较短但比较厚从而有利于采用该种微型发光二极管芯片100的显示装置达成高像素密度。条件0.01≤c/b≤0.3可以避免所述微型发光二极管芯片100因表面粗化高低落差太大而导致芯片容易破损、同时可以保证有提高光取出效率的作用。
优选地，所述图案化结构113的峰-谷高度差c的具体尺寸设置为小于或等于1.5μm，更优选为次微米级甚至是纳米级，此处的次微米级是指所述图案化结构113的峰-谷高度差c(也即图1中Z方向上的高度差，或称表面粗化高低落差)满足条件：0.1μm≤c<1μm，此处的纳米级是指所述图案化结构113的峰-谷高度差c满足条件：c<0.1μm(也即小于100纳米)。举例来说，在某一具体实施例中，a<100μm(甚至可以小于10μm)、b<20μm(更具体地可为b≤10μm)、c≤1.5μm、所述外延结构110的厚度小于10μm(具体地可为2～6μm，例如3～5μm)，但本发明实施例并不以此为限。
此外，对于所述图案化结构113中各个微结构可以是条状(stripe)、圆顶状(dome)、柱状(columnar)等，在此不做具体限制，只要其能够打破全反射以提升微型发光二极管芯片100的光取出效率(或称出光效率)均可。
另外，为便于更清楚地理解本实施例的微型发光二极管芯片100，下面以蓝光Micro-LED芯片为例对本实施例的微型发光二极管芯片100的一种示例性制作方法进行简要说明，具体地：
首先，如图2A所示，采用图案化蓝宝石衬底200作为生长衬底，此处的图案化蓝宝石衬底200是指表面形成有图案化结构202的蓝宝石衬底。
其次，如图2B所示，在所述图案化蓝宝石衬底200的形成有图案化结构202的表面依次外延生长缓冲层1121、N型半导体层1120、有源层1140(例如MQW层)和P型半导体层1160。
然后，进行Micro-LED芯片(COW,chip on wafer)制作，例如利用ICP(Inductive Coupled Plasma，电感耦合等离子体)干法蚀刻方式先进行Mesa结构制作再进行Isolation(隔离)结构制作，具体可为：利用ICP蚀刻所述P型半导体层1160和所述有源层1140直至移除部分所述N型半导体层1120以形成台面结构(mesa structure)藉此暴露部分所述N型半导体层1120，之后再利用ICP蚀刻至图案化蓝光石衬底200以形成Isolation结构来定义出多个Micro-LED芯片。当然，也可以先进行Isolation结构制作再进行Mesa结构制作。在形成Mesa结构和Isolation结构之后，形成与N型半导体层1120(对应第一掺杂类型半导体层112)和P型半导体层1160(对应第二掺杂类型半导体层116)分别形成电性连接例如欧姆接触的N电极118a和P电极118b，如图2C所示。
接下来，使用微黏性胶将前述形成有Mesa结构、Isolation结构和N电极118a 及P电极118b的COW结构与临时基板400暂时固定，如图2D所示。
最后，使用激光剥离去除所述图案化蓝宝石衬底200、同时缓冲层1121会被激光烧蚀掉，进而可以得到与临时基板400暂时固定的多个Micro-LED芯片，也即与临时基板400暂时固定的多个微型发光二极管芯片100，如图2E所示；此处需要说明的是，图2E中所示的微型发光二极管芯片100与图1所示的微型发光二极管芯片100为相同元件，只是图1所示微型发光二极管芯片100省略了N电极118a和P电极118b的绘制。本实施例中，所述图案化蓝宝石衬底200的所述图案化结构202的负图案被转移至所述N型半导体层(第一掺杂类型半导体层112)的出光侧以形成所述图案化结构113(如图1或2E所示)，并且所述图案化结构113的峰-谷高度差优选为小于或等于1.5μm，更优选为次微米级或纳米级。而且，从图2E中可知，所述图案化结构113与所述N型半导体层112为一体结构，也即所述图案化结构113直接形成于所述N型半导体层112上并具有相同的材料。
【第二实施例】
参见图3，本发明第二实施例提供的一种微型发光二极管芯片300，其包括已去除生长衬底且无键合基板支撑的外延结构310。所述外延结构310包括：第一掺杂类型半导体层312、第二掺杂类型半导体层316和位于所述第一掺杂类型半导体层312与所述第二掺杂类型半导体层316之间的有源层314例如多量子阱层，且所述第一掺杂类型半导体层312之远离所述有源层314的一侧(也即微型发光二极管芯片300的出光侧)设置有图案化结构313例如二维光子晶体结构。当然，可以理解的是，本实施例的微型发光二极管300除了所述外延结构310之外，例如还设置有与所述第一掺杂类型半导体层312形成电性连接的第一电极(图3未绘出)和与所述第二掺杂类型半导体层316形成电性连接的第二电极(图3未绘出)，只 是本发明实施例为便于重点描述具有所述图案化结构313的外延结构310，下文将省略对第一电极和第二电极(可参考图2E中的N电极118a和P电极118b)的具体描述。此外，值得一提的是，以蓝光Micro-LED芯片为例，本实施例的外延结构310还可以根据实际需要增设其他功能层，例如非有意掺杂氮化镓层(u-GaN)、位于N型半导体层与多量子阱层之间的应力释放层、位于多量子阱层与P型半导体层之间的电子阻挡层等，本发明实施例并不以此为限。
以蓝光Micro-LED芯片为例，所述第一掺杂类型半导体层312例如是N型GaN层，所述第二掺杂类型半导体层316例如是P型GaN层，所述有源层314例如是InGaN/GaN多量子阱层。当然，本实施例的微型发光二极管芯片300并不限于蓝光Micro-LED芯片，其也可以是其他颜色光Micro-LED芯片，例如绿光Micro-LED芯片、红光Micro-LED芯片等，相应地所述外延结构310中各个层的构成及材料需要做必要调整，但其为现有成熟技术，故在此不再赘述。
承上述，本实施例对所述微型发光二极管芯片300的结构尺寸和/或形状进行设计，例如所述微型发光二极管芯片300的长边a(例如图3中X方向的长度a)、所述微型发光二极管芯片300的厚度b(也即图3中Z方向上的高度，未标示)与所述图案化结构313(二维光子晶体结构)的峰-谷高度差c(也即图3中Z方向上的高度c)满足条件：0.01≤b/a≤6，0.01≤c/b≤0.3；其中b定义为微型发光二极管芯片300在Z方向上的整体厚度，b/a主要是说明微型发光二极管芯片300本身的尺寸规格(典型地，b/a≤1)，且厚度b的取值可藉由外延结构310的厚度、微型发光二极管芯片300的电极厚度、半导体层蚀刻深度(例如Mesa蚀刻深度)来决定。条件0.01≤b/a≤6表征所述微型发光二极管芯片300的长边a可以大于厚度b(例如0.01≤b/a<1)以使得微型发光二极管芯片300的形状看起来比较长但比较薄从 而有利于采用该种微型发光二极管芯片300的显示装置的薄型化，也可以小于厚度b(例如1<b/a≤3)以使得所述微型发光二极管芯片300的形状看起来比较短但比较厚从而有利于采用该种微型发光二极管芯片300的显示装置达成高像素密度。条件0.01≤c/b≤0.3可以避免所述微型发光二极管芯片300因表面粗化高低落差太大而导致芯片容易破损、同时可以保证有提高光取出效率的作用。
优选地，所述图案化结构313(二维光子晶体结构)的峰-谷高度差的具体尺寸设置为小于或等于1.5μm，更优选为次微米级甚至是纳米级，此处的次微米级是指所述图案化结构313的峰-谷高度差c(也即图3中Z方向上的高度差，或称表面粗化高低落差)满足条件：0.1μm≤c<1μm，此处的纳米级是指所述图案化结构313的峰-谷高度差c满足条件：c<0.1μm。
此外，对于作为图案化结构313的二维光子晶体结构，其晶格类型可以是正方晶格、三角晶格或蜂窝晶格等，在此不做具体限制，只要其能够提升微型发光二极管芯片300的光取出效率均可。此处值得说明的是，光子晶体结构具有光子的能阶，可以提升光取出效率，同时还可以根据需求改变/控制光型(出光方向)、控制光的波段。
另外，为便于更清楚地理解本实施例的微型发光二极管芯片300，下面以蓝光Micro-LED芯片为例对本实施例的微型发光二极管芯片300的一种示例性制作方法进行简要说明，具体地：
首先，制作形成有二维光子晶体结构的蓝宝石衬底，具体为：在蓝宝石衬底上采用CVD工艺沉积二氧化硅层，采用电子束曝光技术在二氧化硅层上光刻形成二维光子晶体的图案，再利用干法蚀刻去除图案中周期性分布的微孔区域的二氧化硅以暴露出蓝宝石衬底，即在蓝宝石衬底上形成二维光子晶体结构，也即得 到表面具有图案化结构(例如二维光子晶体结构)的蓝宝石衬底。
其次，在形成有二维光子晶体结构的蓝宝石衬底上依次外延生长非有意掺杂GaN层(u-GaN)、N型GaN层、InGaN/GaN多量子阱层和P型GaN层，其中u-GaN首先填满周期性分布的微孔区域。
然后，进行Micro-LED芯片(COW)制作，例如利用ICP干法蚀刻方式先进行Mesa结构制作再进行Isolation结构制作，具体可为：利用ICP蚀刻所述P型GaN层和所述InGaN/GaN多量子阱层直至移除部分所述N型GaN层以形成台面结构来暴露部分所述N型GaN层，之后再利用ICP蚀刻至蓝光石衬底以形成Isolation结构来定义出多个Micro-LED芯片。当然，也可以先进行Isolation结构制作再进行Mesa结构制作。在形成Mesa结构和Isolation结构之后，形成与N型GaN层和P型GaN层分别形成电性连接的N电极和P电极。
接下来，使用微黏性胶将前述形成有Mesa结构、Isolation结构和N-P电极的COW结构与临时基板暂时固定。
再者，采用248nm KrF准分子激光剥离去除蓝宝石衬底，以暴露出二氧化硅与u-GaN共存的界面；
最后，使用干法蚀刻同时去除暴露区域的u-GaN层及二氧化硅层直至蚀刻到N型GaN层，具体为利用GaN与二氧化硅不同的蚀刻比(例如6:1)、以二氧化硅层作为掩膜层在N型GaN层(第一掺杂类型半导体层312)的出光侧形成如图3所示的图案化结构313，藉此可以得到与临时基板暂时固定且设置有图案化结构313的多个Micro-LED芯片，也即与临时基板暂时固定的多个如图3所示的微型发光二极管300。本实施例中，所述形成有二维光子晶体结构的蓝宝石衬底的二维光子晶体的图案被转移至位于所述N型GaN层的出光侧的u-GaN层，并且所述图 案化结构313的峰-谷高度差小于或等于1.5μm，优选为次微米级或纳米级。而且，所述图案化结构313(二维光子晶体结构)与所述N型GaN层(对应第一掺杂类型半导体层312)为相互接触的两个层结构。
值得说明的是，本发明前述实施例是采用表面具有图案化结构的生长衬底(例如蓝宝石衬底)来制作微型发光二极管芯片100/300，以将生长衬底表面的图案化结构的图案转移至微型发光二极管芯片100/300的出光侧，也即采用图形转移(pattern transfer)方式得到位于微型发光二极管芯片100/300的出光侧的图案化结构113/313；但本发明实施例并不以此为限，也可以先采用平片衬底作为生长衬底，外延生长半导体层来制作无图案化结构的微型发光二极管芯片，在激光剥离平片衬底之后再利用干法蚀刻方式(例如ICP蚀刻)在微型发光二极管芯片的出光侧进行粗化处理以形成图案化结构，其同样可以得到如图1或图3所示的微型发光二极管芯片100/300。此处干法蚀刻方式的采用可以避免相关技术中需要使用强酸强碱药水进行表面粗化而导致微黏性胶受到破坏、进而容易导致芯片脱落而不利于后续芯片转移工艺等技术问题，同时可以提升微型发光二极管芯片的光取出效率。
此外，值得说明的是，本发明前述实施例的示例性制作方法是以制作倒装Micro-LED芯片作为举例进行说明，但本发明实施例的微型发光二极管芯片并不限于倒装Micro-LED芯片，其也可以是垂直结构Micro-LED芯片，也即P电极和N电极分别位于Micro-LED芯片的上下方。
【第三实施例】
图4是本发明第三实施例的一种显示装置的结构示意图。如图4所示，所述显示装置40包括线路基板41和多个(图4仅示出三个作为举例)微型发光二极管 芯片43。其中，所述线路基板41上设置有多个(图4仅示出三个作为举例)电极结构、且每一个所述电极结构包括成对设置的电极411及413；所述多个微型发光二极管芯片43设置在所述线路基板41上、且分别与所述多个电极结构形成电性连接。更具体地，所述线路基板41例如是互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，CMOS)基板、硅基液晶(Liquid Crystal on Silicon，LCOS)基板、薄膜晶体管(Thin Film Transistor，TFT)基板或是其他具有工作电路的基板，在此并不加以限制；所述多个微型发光二极管芯片43可以采用相同颜色Micro-LED芯片、或者采用多种不同颜色(例如R、G、B)Micro-LED芯片；每一个所述微型发光二极管芯片43例如是前述第一实施例的微型发光二极管芯片100或者是前述第二实施例的微型发光二极管芯片300，其具有N电极43a和P电极43b，且所述N电极43a和P电极43b分别通过焊锡42与相对应的电极结构中的电极411及413分别形成电性连接。此外，可以理解的是，在其他实施例中，当微型发光二极管芯片43由图4所示的倒装Micro-LED芯片替换成垂直结构Micro-LED芯片时，则其N电极和P电极之一者可以通过焊锡与电极结构中的电极411及413之一者形成电性连接，另一者通过打线(wire bonding)与电极结构中的电极411及413之另一者形成电性连接。值得说明的是，本实施例的显示装置40通过采用具有较高出光效率的微型发光二极管芯片，其可以实现较高的显示亮度或者较低的功耗。
另外，可以理解的是，前述各个实施方式仅为本发明的示例性说明，在技术特征不冲突、结构不矛盾、不违背本发明的发明目的前提下，各个实施方式的技术方案可以任意组合、搭配使用。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制； 尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (11)

  1. 一种微型发光二极管芯片，包括外延结构；其特征在于，所述外延结构包括第一掺杂类型半导体层、第二掺杂类型半导体层、和位于所述第一掺杂类型半导体层与所述第二掺杂类型半导体层之间的有源层，所述第一掺杂类型半导体层之远离所述有源层的出光侧设置有图案化结构，以及所述微型发光二极管芯片的长边a、所述微型发光二极管芯片的厚度b与所述图案化结构的峰-谷高度差c满足条件：0.01≤b/a≤6、且0.01≤c/b≤0.3。
  2. 如权利要求1所述的微型发光二极管芯片，其特征在于，所述图案化结构的所述峰-谷高度差c满足条件：c<1μm。
  3. 如权利要求2所述的微型发光二极管芯片，其特征在于，所述图案化结构的所述峰-谷高度差c满足条件：0.1μm≤c<1μm。
  4. 如权利要求2所述的微型发光二极管芯片，其特征在于，所述图案化结构的所述峰-谷高度差c满足条件：c<0.1μm。
  5. 如权利要求2至4任意一项所述的微型发光二极管芯片，其特征在于，所述微型发光二极管芯片的长边a小于100μm，所述微型发光二极管芯片的厚度b小于20μm。
  6. 如权利要求1所述的微型发光二极管芯片，其特征在于，所述图案化结构为二维光子晶体结构。
  7. 如权利要求1所述的微型发光二极管芯片，其特征在于，所述图案化结构的所述峰-谷高度差小于或等于1.5μm。
  8. 如权利要求1所述的微型发光二极管芯片，其特征在于，所述图案化结构 为通过采用形成有图案化结构的生长衬底经由图形转移方式设置在所述第一掺杂类型半导体层之远离所述有源层的所述出光侧。
  9. 如权利要求1所述的微型发光二极管芯片，其特征在于，所述图案化结构为在激光剥离生长衬底后采用干法蚀刻方式设置在所述第一掺杂类型半导体层之远离所述有源层的所述出光侧。
  10. 一种微型发光二极管芯片，其特征在于，包括已去除生长衬底且无键合基板支撑的外延结构，所述外延结构包括第一掺杂类型半导体层、第二掺杂类型半导体层、和位于所述第一掺杂类型半导体层与所述第二掺杂类型半导体层之间的有源层，所述第一掺杂类型半导体层之远离所述有源层的出光侧设置有图案化结构、且所述图案化结构的峰-谷高度差小于1微米，所述微型发光二极管芯片的长边小于100微米，所述微型发光二极管芯片的厚度小于或等于10微米，以及所述微型发光二极管芯片的所述厚度b与所述图案化结构的所述峰-谷高度差c满足条件：0.01≤c/b≤0.3。
  11. 一种显示装置，包括：
    线路基板，设置有多个电极结构且每一个所述电极结构包括成对设置的电极；以及
    多个如权利要求1至10任意一项所述的微型发光二极管芯片，设置在所述线路基板上、且分别与所述多个电极结构形成电性连接。
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CN112993116A (zh) * 2020-12-09 2021-06-18 重庆康佳光电技术研究院有限公司 发光器件制作方法、发光器件以及显示器件

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