GB2547123A

GB2547123A - LED vertical chip structure with special coarsening morphology and preparation method therefor

Info

Publication number: GB2547123A
Application number: GB1704361.3A
Authority: GB
Inventors: Tong Ling; Zhang Qiong; Lv Mengyan; Zhang Yu; Li Qiming
Original assignee: Enraytek Optoelectronics Co Ltd
Current assignee: Enraytek Optoelectronics Co Ltd
Priority date: 2014-09-15
Filing date: 2015-09-14
Publication date: 2017-08-09
Anticipated expiration: 2035-09-14
Also published as: GB2547123B; GB201704361D0; DE112015004200T5; CN104218134A; WO2016041471A1; CN104218134B

Abstract

A method for improving luminous efficiency of an LED in a vertical structure. First, an LED vertical chip structure with a special coarsening morphology is provided, and micron-scale holes (311) are formed in the surface of an epitaxial structure layer (300) and submicron-scale holes (312) are formed at the bottom of the micron-scale holes. The light emitting surface structure can increase the emission probability of light inside a device, and can greatly improve the light emission efficiency. Also provided is a preparation method for the chip structure. Micron-scale holes (311) are formed in an epitaxial structure layer (300) by stripping a growth substrate (100) with micron-scale bumps, and submicron-scale holes (312) are formed at the bottom of the micron-scale holes (311) by means of etching. The method is simple in process, can be applied to large-scale industrial production, and can greatly improve the luminous efficiency of the LED in the vertical structure.

Description

LED VERTICAL CHIP STRUCTURE WITH SPECIAL COARSENING MORPHOLOGY AND PREPARATION METHOD THEREFOR

TECHNICAL FIELD

The present invention relates to the field of semiconductors and, in particular, to a vertical LED chip structure with a special roughened profile and a method for fabricating the structure.

BACKGROUND

Structurally, light-emitting diodes (LEDs) can be categorized into face-up, flip-chip and vertical structures. Vertical LEDs are significantly improved in some critical issues such as low heat dissipation efficiency and current blockage that face-up and flip-chip LEDs suffer from and have higher light-emission efficiency, light intensities and densities. They also offer a number of advantages including good heat dissipation, ability to carry large currents, high luminous intensities, less power consumption and long service lives and have therefore found extensive use in general lighting, landscape lighting, special lighting, automotive lighting and other applications. Vertical LEDs are attracting increasing attention and research interest and considered as an inevitable trend in the development of semiconductor lighting technology.

In a vertical LED, the sapphire substrate is removed and a reflective layer can be directly disposed on a P-epitaxial layer so that any light randomly generated within the device and not transmitting toward the light-exit surface can be reflected by the reflective layer. The reflective layer is typically a metal layer or a Bragg layer made of a dielectric material. This can minimize the degradation of light extraction efficiency caused by random light emissions from the device’s active area not travelling toward the light-exit surface. Light extraction efficiency of GaN-based LEDs is subject to limitations arising from the huge difference between refractive indices of GaN and the air. As taught by the Snell’s Law, only light beams with an angle of incidence within a critical range (about 23°) can go out into the air, with the rest incident at an angle not within the range being reflected back and forth within the GaN material and finally adsorbed therein.

For face-up and flip-chip LEDs, patterned substrates formed during the fabrication of the devices are widely used for enhancement of light extraction efficiency of the LEDs. This is because the substrate pattern can be embodied on the surface of the N-epitaxial layer and thus serves as a light-exit feature of an LED which increases the refractive index of the light-exit surface. However, as such patterned substrates need to be removed from vertical LEDs, these vertical LEDs are faced with the problem of how to improve the light extraction efficiency.

SUMMARY OF THE INVENTION

It is an objective of the present invention to solve the low light extraction efficiency problem existing among the conventional vertical LEDs by presenting a vertically-structured LED and a fabrication method thereof.

To this end, the present invention provides a vertical LED chip structure with a special roughened profile, including: a conductive support substrate; a metal bond electrode layer formed on the conductive support substrate; a metal reflective electrode layer formed on the metal bond electrode layer; a contact layer formed on the metal reflective electrode layer; an epitaxial structure layer formed on the contact layer, the epitaxial structure layer comprising a P-GaN layer, an N-GaN layer and an active area layer between the P-GaN layer and the N-GaN layer, wherein a plurality of micron pores are formed in a surface of the epitaxial structure layer and a plurality of sub-micron pores are formed at bottoms of the plurality of micron pores; and an N-electrode bonded to the surface of the epitaxial structure layer.

Optionally, each of the plurality of micron pores may have a diameter of 2 pm to 3 pm and a depth of 1 pm to 3 pm; and each of the plurality of sub-micron pores may have a diameter of 300 nm to 800 nm and a depth of 1 pm to 2 pm.

Optionally, the metal bond electrode layer may be an Au/Sn eutectic layer. Optionally, the metal reflective electrode layer may be an Ag layer.

Optionally, the contact layer may be an ITO or a Ni layer.

The present invention also provides a method for fabricating a vertical LED chip structure with a special roughened profile, including: providing a growth substrate, etching a surface of the growth substrate to form a plurality of micron bumps thereon and forming an epitaxial structure layer on the growth substrate; sequentially forming, on the epitaxial structure layer, a contact layer, a metal reflective electrode layer and a metal bond electrode layer; forming a conductive support substrate on the metal bond electrode layer; removing the growth substrate to form a plurality of micron pores in a surface of the epitaxial structure layer; etching the surface of the epitaxial structure layer to form a plurality of sub-micron pores at bottoms of the plurality of micron pores; and forming an N-electrode on the epitaxial structure layer.

Optionally, etching the surface of the epitaxial structure layer may include: depositing a silicon dioxide layer on the epitaxial structure layer; performing a dry etching process using the silicon dioxide layer as a mask to form the plurality of sub-micron pores at the bottoms of the plurality of micron pores; and removing a remainder of the silicon dioxide layer.

Optionally, after etching the surface of the growth substrate to form the plurality of micron bumps, an unintentionally doped layer may be formed on the surface of the growth substrate and the epitaxial structure layer may be formed on the unintentionally doped layer; and after removing the growth substrate, the plurality of micron pores may be formed in a surface of the unintentionally doped layer and the unintentionally doped layer may be then etched away with the plurality of micron pores being transferred into the epitaxial structure layer, followed by etching of the surface of the epitaxial structure layer and thereby forming the plurality of sub-micron pores at the bottoms of the plurality of micron pores.

Optionally, after the plurality of micron pores are formed in the surface of the unintentionally doped layer, the formation of the plurality of sub-micron pores may be accomplished by: performing a dry etching process to remove the unintentionally doped layer and transfer the plurality of micron pores into the surface of the epitaxial structure layer; depositing a silicon dioxide layer on the epitaxial structure layer; removing a portion of the silicon dioxide layer using photolithographic and etching processes to form a trench between adjacent LED chip structures, the trench exposing the underlying epitaxial structure layer; subjecting the epitaxial structure layer and the silicon dioxide layer simultaneously to a dry etching process to expose the contact layer in the trench and to form the plurality of sub-micron pores at the bottoms of the plurality of micron pores; and removing the silicon dioxide layer.

Optionally, the epitaxial structure layer may have a thickness of from 5 pm to 8 pm; the unintentionally doped layer may have a thickness of from 1 pm to 3 pm; and the silicon dioxide layer may be deposited on the epitaxial structure layer to a thickness of from 1000 nm to 2000 nm.

Optionally, after the plurality of micron pores are formed in the surface of the unintentionally doped layer, the formation of the plurality of sub-micron pores may be accomplished by: depositing a silicon dioxide layer on the unintentionally doped layer; removing a portion of the silicon dioxide layer using photolithographic and etching processes to form a trench between adjacent LED chip structures, the trench exposing the underlying unintentionally doped layer; and subjecting the silicon dioxide layer and the unintentionally doped layer exposed in the trench simultaneously to a dry etching process to expose the contact layer in the trench, and to remove a portion of the silicon dioxide layer and a portion of the unintentionally doped layer out of the trench, thereby forming the plurality of micron pores in the surface of the epitaxial structure layer and the plurality of sub-micron pores at the bottoms of the plurality of micron pores.

Optionally, the epitaxial structure layer may have a thickness of from 5 pm to 8 pm; the unintentionally doped layer may have a thickness of from 1 pm to 3 pm, and the silicon dioxide layer may be deposited on the unintentionally doped layer to a thickness ranging of from 500 nm to 1000 nm.

Optionally, the method may further include roughening the surface of the epitaxial structure layer prior to forming the N-electrode.

In the vertical LED chip structure with the special roughened profile according to the present invention, micron pores are formed in the surface of the epitaxial structure layer and sub-micron pores are formed at bottoms of the micron pores. Such a light-exit surface allows more light to exit from the device and hence leads to a significant improvement in its light extraction efficiency. In addition, in the method for fabricating the chip structure according to the present invention, the micron pores are formed in the epitaxial structure layer by stripping off the growth substrate on which the micron bumps are formed, and the sub-micron pores are formed at the bottoms of the micron pores by etching. The method is simple and suitable for mass production with greatly enhanced vertical LED light-emission efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a flow chart graphically illustrating a method for fabricating a vertical LED chip structure with a special roughened profile in accordance with one embodiment of the present invention.

Figs. 2 to 8 are cutaway views of structures during a method for fabricating a vertical LED chip structure with a special roughened profile in accordance with one embodiment of the present invention.

Figs. 9A to 9D are cutaway views of structures during a process for fabricating the structure of Fig. 6 from that of Fig. 5.

Figs. 10A and 10B are cutaway views of structures during another process for fabricating the structure of Fig. 6 from that of Fig. 5.

Fig. 11 shows SEM images illustrating a top view (left) and a side view (right) of a structure resulting from removal of the growth substrate.

Fig. 12 shows SEM images illustrating a top view (left) and a side view (right) of the structure of Fig. 9A.

Fig. 13A shows SEM images illustrating a top view (left) and a side view (right) of the structure resulting from the process shown in Figs. 9A to 9D.

Fig. 13B shows SEM images illustrating a top view (left) and a side view (right) of the structure resulting from the process shown in Figs. 10A and 10B.

DETAILED DESCRIPTION

The present invention will be described below in greater detail with reference to particular embodiments and the accompanying drawings. Features and advantages of the invention will become more apparent from the following detailed description, and from the appended claims. Note that the accompanying drawings are provided in a very simplified form not necessarily presented to scale, with the only intention of facilitating convenience and clarity in explaining the embodiments of the invention.

The present invention provides a vertical LED chip structure with a special roughened profile. As shown in Fig. 8, the vertical LED chip structure includes: a conductive support substrate 700; a metal bond electrode layer 600 formed on the surface of the conductive support substrate 700; a metal reflective electrode layer 500 formed on the surface of the metal bond electrode layer 600; a contact layer 400 formed on the surface of the metal reflective electrode layer 500; an epitaxial stmcture layer 300 formed on the surface of the contact layer 400; and an N-electrode 800 formed on the surface of the epitaxial structure layer 300.

The epitaxial structure layer 300 includes a P-GaN layer 330, an N-GaN layer 310 and an active area layer 320 between the P-GaN layer 330 and the N-GaN layer 310. There are micron pores 311 in the surface of the epitaxial structure layer 300 and sub-micron pores 312 at the bottoms of the micron pores. As used herein, the terms “micron” and “sub-micron” describe the sizes (diameters) of the pores. Providing the smaller-sized sub-micron pores 312 at the bottoms of the micron pores 311 can facilitate the enhancement of light extraction efficiency. In preferred embodiments, the micron pores have a diameter of 2 pm to 3 pm and a depth of 1 pm to 3 pm, and the sub-micron pores have a diameter of 300 nm to 800 nm and a depth of 1 pm to 2 μιη. Between adjacent micron pores 311 in the surface of the N-GaN layer 310, protrusions are formed resulting from a roughening process.

In particular, the conductive support substrate 700 may be silicon, copper, aluminum, tungsten, or one of a variety of alloys, with silicon, a tungsten-copper alloy or copper-molybdenum alloy that is highly conductive both electrically and thermally being preferred. The metal bond electrode layer 600 may be an Au/Sn eutectic material. The metal reflective electrode layer 500 may be an Ag layer. The contact layer 400 may be formed of indium tin oxide (ITO) or Ni. The N-electrode 800 may be fabricated from, for example, a Ni/Au alloy, an Al/Ti/Pt/Au alloy or a Cr/Pt/Au alloy.

The present invention also provides a method for fabricating such a vertical LED chip structure with a special roughened profile. The steps for fabricating such a vertical LED chip structure are described in detail with reference to Figs. 1 to 8.

At first, in step SI, a growth substrate is provided and etched to form micron bumps on the surface of the growth substrate, followed by forming an epitaxial structure layer on the growth substrate.

In one embodiment, etching the growth substrate is accomplished using a wet etching process or a dry etching process to form micron bumps such that special micron bumps are formed on the surface of the growth substrate 100. The substrate may be implemented as a sapphire substrate or a silicon substrate, without limitation.

Subsequently, an N-GaN layer 310, an active area layer 320 and a P-GaN layer 330 are sequentially grown over the growth substrate 100 so that the epitaxial structure layer 300 is formed. In a preferred implementation of the embodiment, the N-GaN layer 310 is grown on the growth substrate 100 by metal organic chemical vapor deposition (MOCVD) with trimethyl gallium ((CFb^Ga) serving as a Ga source, ammonia (NH3) as an nitrogen (N) source and silane (SiFL) as an N-dopant.

The InGaN/GaN active layer 320 is deposited on the N-GaN layer 310 by a MOCVD process using trimethyl indium ((CH3)3ln) as an In source, (CH3)3Ga as a Ga source and NH3 an N source. In addition, the P-GaN layer 330 is deposited on the active layer 320 by a MOCVD process using (CFb^Ga as a Ga source, NH3 as an N source and magnesocene (MgCCsHs^) as a P-dopant.

As shown in Fig. 2, in a preferred implementation of the embodiment, following the etching of the growth substrate 100 and formation of the micron bumps, an unintentionally doped layer 200 is formed on the growth substrate 100 and the epitaxial structure layer 300 is formed on the unintentionally doped layer 200. The unintentionally doped layer 200 is a non-doped GaN layer which can serve to facilitate the subsequent formation of the epitaxial structure layer 300.

In step S2, a contact layer, a metal reflective electrode layer and a metal bond electrode layer are sequentially formed on the epitaxial structure layer.

As shown in Fig. 3, the contact layer 400 may be vapor-deposited on the P-GaN layer 330, and the contact layer 400 is then fused with the P-GaN layer 330 to form an ohmic contact. After that, the metal reflective electrode layer 500 is vapor-deposited on the contact layer 400 such that an optically reflective surface is formed between the contact layer 400 and the metal reflective electrode layer 500, followed by the formation of the metal bond electrode layer 600.

In step S3, a conductive support substrate is formed on the metal bond electrode layer.

As shown in Fig. 4, the metal reflective electrode layer 500 is bonded to the conductive support substrate 700 through the metal bond electrode layer 600. The conductive support substrate 700 may be silicon, copper, aluminum, tungsten, or a selection from a variety of alloys, with silicon, a tungsten-copper alloy or a copper-molybdenum alloy that is highly conductive both electrically and thermally being preferred. The metal bond electrode layer 600 may be formed of an Au/Sn eutectic material. The metal reflective electrode layer 500 may be an Ag layer. The contact layer 400 may be formed of ITO or Ni. The N-electrode 800 may be fabricated from, for example, a Ni/Au, an Al/Ti/Pt/Au alloy or a Cr/Pt/Au alloy.

In step S4, the growth substrate is removed so that micron pores are formed in the surface of the epitaxial structure layer.

As shown in Fig. 5, the growth substrate 100 may be removed using a laser lift-off technique, with the micron pores being formed in the surface of the N-GaN layer 310 in the epitaxial structure layer 300 with the aid of the micron bumps on the growth substrate 100. Surface profile of the epitaxial structure layer after the growth substrate 100 has been removed is shown in Fig. 11, in which a top view (left) and a side view (right) of a structure resulting from removal of the growth substrate 100 are shown.

In a preferred implementation of the embodiment, as the unintentionally doped layer 200 and the epitaxial structure layer 300 are sequentially formed on the growth substrate 100 after the growth substrate is etched to form the micro bumps on the surface thereof, the micron pores 210 are formed in the unintentionally doped layer 200 after the removal of the growth substrate 100.

In step S5, the surface of the epitaxial structure layer is etched such that sub-micron pores are formed at the bottoms of the micron pores.

Etching the surface of the epitaxial structure layer may include: depositing a silicon dioxide layer on the epitaxial structure layer; performing a dry etching process using the silicon dioxide layer as a mask such that the sub-micron pores are formed at the bottoms of the micron pores; and removing the remainder of the silicon dioxide layer.

Specifically, deposition of the silicon dioxide layer may be accomplished by a chemical vapor deposition (CVD) process. It is noted that due to characteristics of the CVD process, the silicon dioxide is predominantly deposited between the numerous micron pores on the surface of the epitaxial structure layer, with a relatively small amount thereof deposited at the bottom of the pores. Therefore, with the silicon dioxide layer serving as a mask for the dry etching process, the part of the silicon dioxide deposited within the micron pores are removed first so that the process continues to form the sub-micron pores at the bottoms of the micron pores, during which the material between the micron pores is protected by the overlying thicker silicon dioxide.

In a preferred implementation of the embodiment, following the etching of the growth substrate 100 and formation of the micron bumps, an unintentionally doped layer 200 is formed on the growth substrate and the epitaxial structure layer 300 on the unintentionally doped layer 200, and as mentioned above, the micron pores 210 is formed in the unintentionally doped layer 200 after the removal of the growth substrate 100. In this case, as shown in Fig. 6, the unintentionally doped layer 200 may be etched away with the micron pores being transferred into the epitaxial structure layer 300, followed by etching the surface of the epitaxial structure layer 300 to form the sub-micron pores 312 at the bottoms of the micron pores 311.

At last, in step S6, an N-electrode is formed on the epitaxial structure layer.

As shown in Fig. 7, in a preferred implementation of the embodiment, before the formation of the N-electrode 800, the surface of the epitaxial structure layer 300 may be finished by roughening such that a multitude of protrusions 313 are formed on the surface of the N-GaN layer 310 between the micron pores 311. As such, as shown in Fig. 8, the N-electrode 800 is formed on the surface of the epitaxial structure layer 300.

Specifically, the roughening may be accomplished by a wet etching process using a KOH, H3PO4 or other solution. The N-electrode 800 may be formed by vapor deposition of, for example, a Ni/Au, an Al/Ti/Pt/Au or a Cr/Pt/Au alloy.

As described above, a preferred embodiment of the method for fabricating the vertical LED chip structure with a special roughened profile involves an overall substrate process taking into account trenches between a plurality of such vertical LED chip structures. The trenches form gaps between the vertical LED chip structures fabricated on the same substrate. In this embodiment, after the micron pores are formed in the surface of the unintentionally doped layer 200, it is needed to transfer these pores in the epitaxial structure layer 300 and form the sub-micron pores on the epitaxial structure layer 300, i.e., the section of the overall substrate process corresponding to the transformation from the surface profile of Fig. 5 to that of Fig. 6. This transformation can be accomplished using either of the two approaches as specified below.

Approach 1:

As shown in Fig. 5, with the growth substrate 100 having been removed, the micron pores 210 are formed in the unintentionally doped layer 200.

Referring to Fig. 9A, a dry etching process is performed on the unintentionally doped layer 200 to remove the unintentionally doped layer 200 and transfer the micron pores 210 from the unintentionally doped layer 200 to the epitaxial structure layer 300. Preferably, the epitaxial structure layer 300 has a thickness of 5 pm to 8 pm, and the unintentionally doped layer 200 has a thickness of 1 pm to 3 pm. The dry etching process is performed in about 30 min to completely remove the unintentionally doped layer 200 which has a thickness of from 1 pm to 3 pm. The surface profile of the resulting structure is shown in Fig. 12, in which the scanning electron microscope (SEM) images of a top view (left) and a side view (right) of the structure of Fig. 9A are shown.

Afterward, with reference to Fig. 9B, the sihcon dioxide layer 10 is deposited over the epitaxial structure layer 300. As discussed above, due to characteristics of the CVD process, the silicon dioxide is predominantly deposited between the numerous micron pores on the surface of the epitaxial structure layer 300, with a relatively small amount of the sihcon dioxide deposited in lower portions of the micron pores. Preferably, the silicon dioxide layer 10 overlying the epitaxial structure layer 300 has a thickness between 1000 nm and 2000 nm. The thickness of the silicon dioxide layer 10 herein refers to the thickness of the silicon dioxide layer 10 deposited between the micron pores.

Referring to Fig. 9C, a photolithographic process is carried out to remove portions of the silicon dioxide layer 10, resulting in trenches between the vertical LED chip structures in which epitaxial structure layer 300 is exposed, with the remainder of the silicon dioxide layer indicated by silicon dioxide layers 10' overlying the respective vertical LED chip structures. As mentioned above, the trenches form gaps between the vertical LED chip structures fabricated on the same substrate.

The photolithographic process may include: coating a photoresist layer on the silicon dioxide layer 10; patterning the photoresist layer by exposure and development so as to expose the portions of the silicon dioxide layer 10 corresponding to the trenches; etching the silicon dioxide layer 10 with the patterned photoresist layer serving as a mask to expose the underlying epitaxial structure layer 300; removing the remainder of the photoresist layer, resulting in the structure shown in Fig. 9C. The etching of the sihcon dioxide layer 10 may be accomplished by a wet etching process using a BOE solution.

Referring to Fig. 9D, the epitaxial structure layer 300 and the silicon dioxide layers 10' are simultaneously subjected to a dry etching process which is so conditioned that the contact layer 400 is exposed in the trenches and the sub-micron pores 312 are formed at the bottoms of the micron pores 311 after the etch. At the time when the sub-micron pores 312 have been formed, the silicon dioxide layers 10' are not completely etched away, with the remaining silicon dioxide layer 10" protecting the underlying epitaxial structure layer 300.

Lastly, a wet etching process using a BOE solution is carried out to remove the remaining silicon dioxide layer 10", resulting in the surface profile as shown in Fig. 6, i.e., removal of the remaining silicon dioxide layer 10" and resulting in the micron pores 311 and the sub-micron pores 312 in the epitaxial structure layer 300. The profile of the resulting structure from the approach is shown in Fig. 13 A, in which the SEM images of a top view (left) and a side view (right) of the structure resulting from the process of Figs. 9A to 9D are shown.

Approach 2:

Referring to Fig. 10A, the silicon dioxide layer 20 is deposited on the unintentionally doped layer 200. In one preferred embodiment, the epitaxial structure layer 300 has a thickness of 5 pm to 8 pm, and the unintentionally doped layer 200 has a thickness between 1 pm and 3pm. The silicon dioxide layer 20 overlying the unintentionally doped layer 300 has a maximum thickness in the range of from 500 nm to 1000 nm. The maximum thickness herein refers to the thickness of the silicon dioxide 20 deposited between the micron pores.

Referring to Fig. 10B, a photolithographic process is carried out to remove portions of the silicon dioxide layer 20, resulting in trenches between the vertical LED chip structures in which the unintentionally doped layer 200 is exposed, with the remainder of the silicon dioxide layer indicated by silicon dioxide layers 20' overlying the respective vertical LED chip structures.

The photolithographic process may include: coating a photoresist layer on the silicon dioxide layer 20; patterning the photoresist layer by exposure and development so as to expose the portions of the silicon dioxide layer 20 corresponding to the trenches; etching the silicon dioxide layer 20 with the patterned photoresist layer serving as a mask to expose the underlying unintentionally doped layer 200; and removing the remainder of the photoresist layer, resulting in the structure shown in Fig. 10B. The etching of the silicon dioxide layer 20 may be accomplished by a wet etching process using a BOE solution.

After that, the silicon dioxide layers 20' and the unintentionally doped layer 300 exposed in the trenches are simultaneously subjected to a dry etching process which is so controlled that after the etching: the contact layer 400 is exposed in the trenches; the portions of the silicon dioxide layer 20' and of the unintentionally doped layer 200 out of the trenches (i.e., overlying the vertical LED chip structures) are removed; the micron pores 311 are formed in the surface of the epitaxial structure layer 300; and the sub-micron pores 312 are formed at the bottoms of the micron pores, resulting in the surface profile shown in Fig. 6. The profile of the resulting structure from the approach is shown in Fig. 13B, in which the SEM images of a top view (left) and a side view (right) of the structure resulting from the process of Figs. lOAand 10B are shown.

In this approach, during the formation of the silicon dioxide layer 20, the dry etching process performed prior to the removal of the unintentionally doped layer 200 can entirely remove the silicon dioxide layer 20 concurrently with the formation of the micron pores 311 and the sub-micron pores 312. This eliminates the need for subsequent silicon dioxide removal and makes the approach more easily implementable. However, it raises the requirements for control precision and the sub-micron pores 312 resulting from it are not as fine as those from Approach 1.

In the vertical LED chip structure with the special roughened profile according to the present invention, micron pores are formed in the surface of the epitaxial stmcture layer and sub-micron pores are formed at the bottoms of the micron pores. Such a light-exit surface allows more light to exit from the device and hence leads to a significant improvement in its light extraction efficiency and quality. In addition, in the method for fabricating the above-mentioned vertical LED chip structure according to the present invention, the micron pores are formed in the epitaxial structure layer by stripping off the growth substrate on which the micron bumps are formed, and the sub-micron pores are formed at the bottoms of the micron pores by etching. The method is simple and suitable for mass production with greatly enhanced vertical LED light-emission efficiency.

Apparently, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope thereof. It is therefore intended that the invention embraces all such modifications and variations as fall within the scope of the appended claims and equivalents thereof.

Claims

1. A vertical LED chip structure with a special roughened profile, comprising: a conductive support substrate; a metal bond electrode layer formed on the conductive support substrate; a metal reflective electrode layer formed on the metal bond electrode layer; a contact layer formed on the metal reflective electrode layer; an epitaxial structure layer formed on the contact layer, the epitaxial structure layer comprising a P-GaN layer, an N-GaN layer and an active area layer between the P-GaN layer and the N-GaN layer, wherein a plurality of micron pores are formed in a surface of the epitaxial structure layer and a plurality of sub-micron pores are formed at bottoms of the plurality of micron pores; and an N-electrode bonded to the surface of the epitaxial structure layer.

2. The vertical LED chip structure of claim 1, wherein each of the plurality of micron pores has a diameter of 2 pm to 3 pm and a depth of 1 pm to 3 pm; and each of the plurality of sub-micron pores has a diameter of 300 nm to 800 nm and a depth of 1 pm to 2 pm.

3. The vertical LED chip structure of claim 1, wherein the metal bond electrode layer is an Au/Sn eutectic layer.

4. The vertical LED chip structure of claim 1, wherein the metal reflective electrode layer is an Ag layer.

5. The vertical LED chip structure of claim 1, wherein the contact layer is an ITO or a Ni layer.

6. A method for fabricating a vertical LED chip structure with a special roughened profile, comprising: providing a growth substrate, etching a surface of the growth substrate to form a plurality of micron bumps thereon and forming an epitaxial structure layer on the growth substrate; sequentially forming, on the epitaxial structure layer, a contact layer, a metal reflective electrode layer and a metal bond electrode layer; forming a conductive support substrate on the metal bond electrode layer; removing the growth substrate to form a plurality of micron pores in a surface of the epitaxial structure layer; etching the surface of the epitaxial structure layer to form a plurality of sub-micron pores at bottoms of the plurality of micron pores; and forming an N-electrode on the epitaxial structure layer.

7. The method for fabricating a vertical LED chip structure of claim 6, wherein etching the surface of the epitaxial structure layer comprises: depositing a silicon dioxide layer on the epitaxial structure layer; performing a dry etching process using the silicon dioxide layer as a mask to form the plurality of sub-micron pores at the bottoms of the plurality of micron pores; and removing a remainder of the silicon dioxide layer.

8. The method for fabricating a vertical LED chip structure of claim 6, wherein: after etching the surface of the growth substrate to form the plurality of micron bumps thereon, an unintentionally doped layer is formed on the surface of the growth substrate and the epitaxial structure layer is formed on the unintentionally doped layer; and after removing the growth substrate, the plurality of micron pores are formed in a surface of the unintentionally doped layer and the unintentionally doped layer is then etched away with the plurality of micron pores being transferred into the epitaxial stmcture layer, followed by etching of the surface of the epitaxial structure layer and thereby forming the plurality of sub-micron pores at the bottoms of the plurality of micron pores.

9. The method for fabricating a vertical LED chip structure of claim 8, wherein after the plurality of micron pores are formed in the surface of the unintentionally doped layer, the formation of the plurality of sub-micron pores is accomplished by: performing a dry etching process to remove the unintentionally doped layer and transfer the plurality of micron pores into the surface of the epitaxial structure layer; depositing a silicon dioxide layer on the epitaxial structure layer; removing a portion of the silicon dioxide layer using photolithographic and etching processes to form a trench between adjacent LED chip structures, the trench exposing the underlying epitaxial structure layer; subjecting the epitaxial structure layer and the silicon dioxide layer simultaneously to a dry etching process to expose the contact layer in the trench and to form the plurality of sub-micron pores at the bottoms of the plurality of micron pores; and removing the silicon dioxide layer.

10. The method for fabricating a vertical LED chip structure of claim 9, wherein: the epitaxial structure layer has a thickness of from 5 pm to 8 pm; the unintentionally doped layer has a thickness of from 1 pm to 3 pm; and the silicon dioxide layer is deposited on the epitaxial structure layer to a thickness of from 1000 nm to 2000 nm.

11. The method for fabricating a vertical LED chip structure of claim 8, wherein after the plurality of micron pores are formed in the surface of the unintentionally doped layer, the formation of the plurality of sub-micron pores is accomplished by: depositing a silicon dioxide layer on the unintentionally doped layer; removing a portion of the silicon dioxide layer using photolithographic and etching processes to form a trench between adjacent LED chip structures, the trench exposing the underlying unintentionally doped layer; and subjecting the silicon dioxide layer and the unintentionally doped layer exposed in the trench simultaneously to a dry etching process to expose the contact layer in the trench, and to remove a portion of the silicon dioxide layer and a portion of the unintentionally doped layer out of the trench, thereby forming the plurality of micron pores in the surface of the epitaxial structure layer and the plurality of sub-micron pores at the bottoms of the plurality of micron pores.

12. The method for fabricating a vertical LED chip structure of claim 11, wherein: the epitaxial structure layer has a thickness of from 5 pm to 8 pm; the unintentionally doped layer has a thickness of from 1 pm to 3 pm; and the silicon dioxide layer is deposited on the unintentionally doped layer to a thickness of from 500 nm to 1000 nm.

13. The method for fabricating a vertical LED chip structure of claim 6, further comprising roughening the surface of the epitaxial structure layer prior to forming the N-electrode.