US20160351576A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20160351576A1
US20160351576A1 US15/159,021 US201615159021A US2016351576A1 US 20160351576 A1 US20160351576 A1 US 20160351576A1 US 201615159021 A US201615159021 A US 201615159021A US 2016351576 A1 US2016351576 A1 US 2016351576A1
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Prior art keywords
insulator
semiconductor
transistor
equal
oxide
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Abandoned
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US15/159,021
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English (en)
Inventor
Shunpei Yamazaki
Tomoaki Atsumi
Yuta ENDO
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMAZAKI, SHUNPEI, ATSUMI, TOMOAKI, ENDO, YUTA
Publication of US20160351576A1 publication Critical patent/US20160351576A1/en
Priority to US17/236,115 priority Critical patent/US11963360B2/en
Priority to US18/613,222 priority patent/US20240315038A1/en
Abandoned legal-status Critical Current

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    • H01L27/1157—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H01L27/11573—
    • H01L27/11582—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

  • the present invention relates to, for example, a semiconductor, a transistor, and a semiconductor device.
  • the present invention relates to, for example, a method for manufacturing a semiconductor, a transistor, and a semiconductor device.
  • the present invention relates to, for example, a semiconductor, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, and an electronic device.
  • the present invention relates to a method for manufacturing a semiconductor, a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.
  • the present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.
  • a semiconductor device generally means a device that can function by utilizing semiconductor characteristics.
  • a display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.
  • a memory device including a semiconductor has attracted attention as a high capacity memory device included in a computer and the like.
  • the integration degree of a NAND flash memory is easily heightened because the NAND flash memory has a small number of wirings or electrodes per memory cell.
  • Storage capacity has been increased year by year because of realization of technology such as multivalued memory.
  • two-dimensional memory cell arrangement has approached limits on higher integration and is being replaced with technology of three-dimensional memory cell arrangement (see Patent Document 1).
  • Patent Document 1 Japanese Published Patent Application No. 2011-96340
  • An object is to provide a highly integrated semiconductor device. Another object is to provide a semiconductor device with three-dimensional memory cell arrangement. Another object is to provide a semiconductor device with large storage capacity. Another object is to provide a semiconductor device with a long retention period.
  • Another object is to provide a module including any of the above semiconductor devices. Another object is to provide an electronic device including any of the above semiconductor devices or the module. Another object is to provide a novel semiconductor device. Another object is to provide a novel module. Another object is to provide a novel electronic device.
  • Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor having a low leakage current in an off state. Another object is to provide a transistor having a small subthreshold swing value. Another object is to provide a transistor having a small short-channel effect. Another object is to provide a transistor having excellent electrical characteristics. Another object is to provide a transistor having high reliability. Another object is to provide a transistor with high frequency characteristics.
  • One embodiment of the present invention is a semiconductor device that includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series.
  • the prism-like insulator is provided over the substrate, and the memory cell string is provided on the side surface of the prism-like insulator.
  • One embodiment of the present invention is a semiconductor device that includes a substrate, a prism-like insulator, a plurality of memory cell strings.
  • the plurality of memory cell strings each comprise a plurality of transistors connected in series.
  • the prism-like insulator is provided over the substrate, and the plurality of memory cell strings each are provided on a side surface of the prism-like insulator.
  • One embodiment of the present invention is the semiconductor device according to (1) or (2), in which the plurality of transistors each include a gate insulator and a gate electrode, the gate insulator includes a first insulator, a second insulator, and a charge accumulation layer, and the charge accumulation layer is positioned between the first insulator and the second insulator.
  • One embodiment of the present invention is the semiconductor device according to any one of (1) to (3), in which the plurality of transistors include an oxide semiconductor.
  • One embodiment of the present invention is the semiconductor device according to (4), in which the oxide semiconductor contains indium, an element M (aluminum, gallium, yttrium, or tin), and zinc.
  • the oxide semiconductor contains indium, an element M (aluminum, gallium, yttrium, or tin), and zinc.
  • One embodiment of the present invention is the semiconductor device according to any one of (1) to (5) which further includes a first transistor and a second transistor provided over the substrate.
  • a source terminal of the first transistor is electrically connected to a first terminal of the memory cell string and a drain terminal of the second transistor is electrically connected to a second terminal of the memory cell string.
  • One embodiment of the present invention is the semiconductor device according to (6), in which the first transistor and the second transistor include single crystal silicon.
  • a highly integrated semiconductor device can be provided.
  • a semiconductor device with three-dimensional memory cell arrangement can be provided.
  • a semiconductor device with large storage capacity can be provided.
  • a semiconductor device with a long retention period can be provided.
  • a module including any of the above semiconductor devices can be provided.
  • An electronic device including any of the above semiconductor devices or the module can be provided.
  • a novel semiconductor device can be provided.
  • a novel module can be provided.
  • a novel electronic device can be provided.
  • a transistor having normally-off electrical characteristics can be provided.
  • a transistor having a low leakage current in an off state can be provided.
  • a transistor having a small subthreshold swing value can be provided.
  • a transistor having a small short-channel effect can be provided.
  • a transistor having excellent electrical characteristics can be provided.
  • a transistor having high reliability can be provided.
  • a transistor with high frequency characteristics can be provided.
  • FIGS. 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device of one embodiment of the present invention
  • FIGS. 2A and 2B are a schematic view and a cross-sectional view illustrating operation of a semiconductor device of one embodiment of the present invention
  • FIGS. 3A and 3B are circuit diagrams illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 4 is a circuit diagram illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 5 is a circuit diagram illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 6 is a circuit diagram illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 7 is a circuit diagram illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 8 is a circuit diagram illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 9 is a circuit diagram illustrating operation of a semiconductor device of one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of a semiconductor device of one embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of a semiconductor device of one embodiment of the present invention.
  • FIG. 12 is a band diagram of a channel formation region in a transistor of one embodiment of the present invention and its vicinity thereof;
  • FIG. 13 is a triangular diagram for explaining composition of an In-M-Zn oxide
  • FIGS. 14A to 14E show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD and selected-area electron diffraction patterns of a CAAC-OS;
  • FIGS. 15A to 15E show a cross-sectional TEM image and plan-view TEM images of a CAAC-OS and images obtained through analysis thereof:
  • FIGS. 16A to 16D show electron diffraction patterns and a cross-sectional TEM image of an nc-OS
  • FIGS. 17A and 17B show cross-sectional TEM images of an a-like OS.
  • FIG. 18 shows a change of crystal parts of an In—Ga—Zn oxide owing to electron irradiation.
  • film and “layer” can be interchanged with each other.
  • a voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a source potential or a ground potential (GND)).
  • a voltage can be referred to as a potential and vice versa.
  • a potential is relative and is determined depending on the difference relative to a reference potential. Therefore, even a “ground potential,” for example, is not necessarily 0 V.
  • a “ground potential” is the lowest potential in a circuit.
  • a “ground potential” is a moderate potential in a circuit.
  • a positive potential and a negative potential are set using the potential as a reference.
  • ordinal numbers such as “first” and “second” are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second,” “third,” or the like as appropriate.
  • ordinal numbers in this specification and the like do not correspond to the ordinal numbers which specify one embodiment of the present invention in some cases.
  • an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor.
  • an element with a concentration of lower than 0.1 atomic % is an impurity.
  • the density of states (DOS) may be formed in a semiconductor, the carrier mobility may be decreased, or the crystallinity may be decreased, for example.
  • examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (hydrogen is included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example.
  • oxygen vacancy may be formed by entry of impurities such as hydrogen.
  • impurities such as hydrogen.
  • examples of an impurity which changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
  • the description “A has a shape such that an end portion extends beyond an end portion of B” may indicate, for example, the case where at least one of end portions of A is positioned on an outer side than at least one of end portions of B in a top view or a cross-sectional view.
  • the description “A has a shape such that an end portion extends beyond an end portion of B” can be alternately referred to as the description “one of end portions of A is positioned on an outer side than one of end portions of B in a top view,” for example.
  • the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to ⁇ 10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to ⁇ 5° and less than or equal to 5°.
  • a term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to ⁇ 30° and less than or equal 15 to 30°.
  • the term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also indicates that the angle formed between two straight lines is greater than or equal to 85° and less than or equal to 95°.
  • a term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.
  • trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.
  • a semiconductor device of one embodiment of the present invention will be described below.
  • transistor is assumed to be of an n-channel type below.
  • a term, a reference numeral, or the like may be replaced with an appropriate one in the following description when a p-channel transistor is used.
  • FIG. 1A is a cross-sectional view of a semiconductor device of one embodiment of the present invention.
  • FIG. 1B is a circuit diagram of the semiconductor device in FIG. 1A .
  • the semiconductor device in FIG. 1A includes a substrate 100 , an insulator 120 , an insulator 122 , an insulator 124 , an insulator 126 , an insulator 128 , an insulator 130 , a conductor 140 , a conductor 142 , a conductor 144 , a conductor 146 , a conductor 148 , a conductor 132 , a conductor 134 , a conductor 136 , a conductor 138 , a transistor Tr_S 1 , a transistor Tr_S 2 , and transistors Tr_to Tr_ 2 n (n is an integer of 2 or more).
  • the transistors Tr_S 1 and Tr_S 2 are provided to the substrate 100 .
  • the transistor Tr_S includes a pair of impurity regions 166 provided in the substrate 100 , a channel formation region placed between the impurity regions 166 , a conductor 154 including a region overlapping with the channel formation region, and an insulator 162 placed between the channel formation region and the conductor 154 .
  • the conductor 154 has a function as a gate electrode and the insulator 162 has a function as a gate insulator.
  • the conductor 154 which serves as a gate electrode of the transistor Tr_S 1 , is electrically connected to a wiring SEL_ 1 .
  • the conductor 154 which serves as a gate electrode of the transistor Tr_S 2 , is electrically connected to a wiring SEL_ 2 .
  • the transistor Tr_S 2 has the same structure as that of the transistor Tr_S 1 , and the description of its structure is omitted; however, the transistor Tr_S 2 may have a different structure.
  • the transistors Tr_S 1 and Tr_S 2 are isolated by the insulator 120 .
  • As the element isolation method a shallow trench isolation (STI) method, a local oxidation of silicon (LOCOS) method, or the like can be used.
  • the structures of the transistors Tr_S 1 and Tr_S 2 are not limited to the structures illustrated in FIG. 1A .
  • a transistor provided over a silicon on insulator (SOI) substrate or a FIN-type transistor may be used.
  • the insulator 122 is provided over the transistors Tr_S 1 and Tr_S 2 .
  • the insulator 130 , and the conductors 144 , 146 , and 148 are provided over the insulator 122 .
  • the insulator 130 has a prism-like shape or a wall-like shape and is provided with the transistors Tr_ 1 to Tr_ 2 n (n is an integer of 2 or more) on the sides thereof. Note that the channel length direction of each of the transistors Tr_ 1 to Tr_n is parallel to the direction perpendicular to a top surface of the substrate and the channel length direction of each of the transistors Tr_n+1 to Tr_ 2 n is parallel to the direction perpendicular to the top surface of the substrate.
  • the insulator 130 does not necessarily have a prism-like shape or a wall-like shape, and may be a cylinder shape, for example.
  • One side of the insulator 130 is provided with the transistors Tr_ 1 to Tr_n, and the other side is provided with the transistors Tr_n+1 to Tr_ 2 n .
  • n may be 2, 4, 8, 16, 32, 64, or 128.
  • the conductor 132 has a region facing the transistors Tr_ 1 to Tr_ 2 n with the insulator 130 therebetween.
  • the conductor 132 has a function as a back gate electrode of the transistors Tr_ 1 to Tr_ 2 n (also referred to as a second gate electrode) and is electrically connected to a wiring BGL.
  • the transistor Tr_ 1 includes an insulator 106 a , a semiconductor 106 b , an insulator 106 c , a conductor 116 a , a conductor 116 b , an insulator 112 a , a charge accumulation layer 112 b , an insulator 112 c , and a conductor 104 .
  • the insulator 106 a is provided along the side of the insulator 130 .
  • the semiconductor 106 b is provided along the side of the insulator 130 with the insulator 106 a therebetween.
  • the insulator 106 c is provided along the side of the insulator 130 with the semiconductor 106 b and the insulator 106 a therebetween.
  • the insulator 112 a , the conductor 116 a , and the conductor 116 b each include a region facing the insulator 130 with the insulator 106 c , the semiconductor 106 b , and the insulator 106 a therebetween. Note that the insulator 112 a is placed between the conductor 116 a and the conductor 116 b .
  • the charge accumulation layer 112 b has a region facing the insulator 130 with the insulator 112 a , the insulator 106 c , the semiconductor 106 b , and the insulator 106 a therebetween.
  • the insulator 112 c has a region facing the insulator 130 with the charge accumulation layer 112 b , the insulator 112 a , the insulator 106 c , the semiconductor 106 b , and the insulator 106 a therebetween.
  • the conductor 104 has a region facing the insulator 130 with the insulator 112 c , the charge accumulation layer 112 b , the insulator 112 a , the insulator 106 c , the semiconductor 106 b , and the insulator 106 a therebetween.
  • the semiconductor 106 b has a function as a channel formation region
  • the conductor 104 has a function as a gate electrode
  • the insulator 112 a , the charge accumulation layer 112 b , and the insulator 112 c each have a function as a gate insulator
  • the conductor 116 a has a function as a source electrode
  • the conductor 116 b has a function as a drain electrode.
  • the insulator 106 a and the insulator 106 c have functions of reducing the density of defect states at the interfaces between the semiconductor 106 b and the insulator 106 a and between the semiconductor 106 b and the insulator 106 c .
  • the conductor 104 which serves as the gate electrode of the transistor Tr_ 1 , is electrically connected to a wiring WL_ 1 .
  • the wiring WL_ 1 has a function as a word line.
  • the transistor Tr_ 1 is not limited to the structure illustrated in FIG. 1A .
  • some components such as the insulators 106 a and 106 c are not necessarily provided.
  • the transistor Tr_ 1 includes the charge accumulation layer 112 b between the conductor 104 and the semiconductor 106 b .
  • the threshold voltage of the transistor Tr_ 1 corresponds to the polarity and amount of charge included in the charge accumulation layer 112 b .
  • the threshold voltage of the transistor Tr_ 1 can be controlled by the charge accumulation layer 112 b ; therefore, the transistor Tr_ 1 can serve as a memory cell (also referred to as a memory element) which stores data corresponding to the threshold voltage.
  • the threshold voltage of the transistor Tr_ 1 is negative when electrons are not accumulated in the charge accumulation layer 112 b .
  • the threshold voltage changes to cancel an electric field generated by the electrons, and then the threshold voltage becomes positive as shown in the right of FIG. 2A . That is, the transistor Tr_ 1 takes data “1” because it is on when electrons are not accumulated in the charge accumulation layer 112 b , and takes data “0” because of non-conduction when electrons are accumulated in the charge accumulation layer 112 b .
  • a multivalued memory cell of three values or more may be used. Note that electron injection into the charge accumulation layer 112 b will be described later.
  • the transistors Tr_ 2 to Tr_ 2 n have the same structures as that of the transistor Tr_ 1 .
  • Each of the gate electrodes of the transistors Tr_ 2 to Tr_ 2 n is electrically connected to corresponding wirings WL_ 2 to WL_ 2 n .
  • the wirings WL_ 2 to WL_ 2 n each have a function as a word line.
  • the transistors Tr_ 1 to Tr_ 2 n each have a function as a memory cell.
  • the transistors Tr_ 1 to Tr_ 2 n are connected in series; thus, they can be collectively called one memory cell string.
  • Memory cell strings can be arranged in matrix over the substrate 100 , for example.
  • Each of the memory cell strings is electrically connected to a selection transistor.
  • the memory cell strings are arranged over points of intersection of a plurality of straight lines extending in a first direction and a plurality of straight lines extending in a second direction over the substrate 100 .
  • the angle between the first direction and the second direction may be typically 45° or 90°.
  • the angle may be in the range of greater than or equal to 10° and less than or equal to 90°, greater than or equal to 30° and less than or equal to 90°, greater than or equal to 45° and less than or equal to 90°, or greater than or equal to 60° and less than or equal to 90°, for example.
  • the arrangement of the memory cell strings is preferably dense, and it depends on the shape of the memory cell strings.
  • a wiring SL and a wiring BL provided along the first direction, for example, can be shared between the memory cell strings formed along the first direction. Note that the arrangement of the memory cell strings is not limited to a matrix arrangement.
  • the wiring SL has a function as a source line.
  • the wiring BL has a function as a bit line.
  • the plurality of memory cell strings are collectively called a block.
  • One block is supposed to include a ⁇ b memory cell strings, a is the number of memory cell strings in the first direction (a is a natural number) and b is the number of memory cell strings in the second direction (b is a natural number). Note that the blocks may have different numbers of memory cell strings. A rule of how to form the blocks may be determined as appropriate.
  • the wiring BGL is electrically connected to the conductor 132 , for example.
  • the conductors 132 are electrically isolated from the wirings BGL between the blocks.
  • wirings WL_ 1 to WL_ 2 n provided along the second direction for example, can be shared between the memory cell strings formed along the second direction.
  • the wirings WL_ 1 to WL_ 2 n may be provided for each of the blocks or may be shared between the blocks arranged along the second direction. Memory cells sharing the wirings WL_ 1 to WL_ 2 n are collectively called a page. Note that the wirings BL and SL can be shared between blocks arranged along the first direction.
  • a source terminal of the transistor Tr_S 1 is electrically connected to the wiring SL, and its drain terminal of the transistor Tr_S 1 is electrically connected to a first terminal of the memory cell string.
  • a drain terminal of the transistor Tr_S 2 is electrically connected to the wiring BL, and its source terminal of the transistor Tr_S 2 is electrically connected to a second terminal of the memory cell string.
  • the transistors Tr_S 1 and Tr_S 2 can be called selection transistors because the transistors control conduction or non-conduction between the memory cell string and the wirings.
  • a reset operation When data is written to each of the memory cells, data is preferably deleted (data “1” is preferably written) in advance of the writing operation.
  • the operation of deleting data is also referred to as a reset operation.
  • the reset operation is performed in each block.
  • a reset operation can be performed in the following manner: a block storing data to be deleted is selected, an erasing potential V E (e.g., 15 V) is applied to the wiring BGL electrically connected to the conductor 132 , a low potential (a potential such as 0 V, at which the transistors Tr_ 1 to Tr_ 2 n are turned off) is applied to the wirings WL_ 1 to WL_ 2 n , and the transistors Tr_S 1 and Tr_S 2 are turned on as shown in FIG.
  • V E e.g. 15 V
  • a low potential a potential such as 0 V, at which the transistors Tr_ 1 to Tr_ 2 n are turned off
  • a reset operation can also be performed by an erasing potential V E applied to the wirings SL and BL. Electrons stored in the charge accumulation layer 112 b of each of the transistors Tr_ 1 to Tr_ 2 n can be extracted through the reset operation.
  • the electrical connection between the conductor 132 and the wiring BGL is cut off so that an erasing potential V E is not to be applied to the conductor 132 .
  • a potential such as an erasing potential V E at which the transistors Tr_ 1 to Tr_ 2 n are turned on, may be applied to the wirings WL_ 1 to WL_ 2 n electrically connected to a block from which data is not deleted. That is, the charge accumulation layer 112 b is not applied with a difference in potential which leads electron extraction.
  • data in a memory cell which is not subjected to rewriting is preferably stored in a different region in advance of the reset operation of the block.
  • a writing operation of data can be performed for each of the above pages.
  • a writing potential e.g., 15 V
  • a positive potential a potential such as 3 V, at which a transistor is turned on
  • a writing potential is applied to the wiring WL_ 1 first, and then positive potentials are applied to the wirings WL_ 2 to WL_ 2 n .
  • the transistor Tr_S 1 electrically connected to the wiring SL is off, and the transistor Tr_S 2 electrically connected to the wiring BL is on.
  • a potential of the wiring BL is applied to the memory cell of the page subjected to writing.
  • Data corresponding to the potential of the wiring BL is written to the memory cell.
  • a potential of the wiring BL is a low potential such as 0 V
  • electrons are injected into the charge accumulation layer 112 b because a difference between the potential of the wiring BL and the writing potential applied to the wiring WL_ 1 is increased.
  • the potential of the wiring BL is a positive potential
  • electrons are not injected into the charge accumulation layer 112 b because a difference between the potential of the wiring BL and the writing potential applied to the wiring WL_ 1 is decreased. That is, data “0” is written to the memory cell when a low potential is applied to the wiring BL, and the memory cell keeps data “1” when a positive potential is applied.
  • Data writing can be performed page by page in such a manner that each of the wirings BL is applied with a potential required in the corresponding memory cell string. As shown in FIGS. 5 and 6 , the same data writing is performed also for the wirings WL_ 2 to WL_ 2 n , so that data writing can be performed for the block or the whole of the semiconductor device.
  • data other than the data “0” or data “1” can also be written to the memory cell.
  • the amount of electrons injected into the charge accumulation layer 112 b can be controlled on the basis of a potential of the wiring BL or the like or a potential applying period.
  • a reading operation of data can also be performed for each of the pages.
  • a low potential such as 0 V is applied to a word line of a page subjected to reading, and then a positive potential (a potential such as 3 V, at which a transistor is turned on) is applied to a word line of a page which is not subjected to reading.
  • a low potential is applied to the wiring WL_ 1 first, and then positive potentials are applied to the wirings WL_ 2 to WL_ 2 n .
  • the transistor Tr_S 1 electrically connected to the wiring SL and the transistor Tr_S 2 electrically connected to the wiring BL are on.
  • a reading potential such as 1 V is applied to the wiring BL, and a low potential such as 0 V is applied to the wiring SL.
  • a current is supplied to the memory cell string if the memory cell has data “1,” and a current is not supplied to the memory cell string if the memory cell has data “0.” Accordingly, data of the memory cell can be read by detection of the current value at that time or by detection of a potential drop of the wiring BL.
  • Data in each of the memory cell strings is output to the wiring BL; thus, data per page can be read.
  • the same data reading is performed for the wirings WL_ 2 to WL_ 2 n , so that data reading subjected to the block or the whole of the semiconductor device can be performed.
  • the semiconductor device of one embodiment of the present invention has high integration due to the three-dimensional arrangement of the memory cells.
  • the semiconductor device has a large storage capacity per footprint.
  • the semiconductor device has a storage capacity of 1 Tbyte or more, 3 Tbyte or more, or 10 Tbyte or more.
  • the semiconductor device can also be called a semiconductor device including a nonvolatile or substantially nonvolatile memory element because it can store data for a long period.
  • the semiconductor device of one embodiment of the present invention is suited for a storage device for computers because the semiconductor device is capable of rewriting and storing data for a long period, and has a large storage capacity.
  • the semiconductor device can be used in a main storage device (also referred to as a main memory or a memory) that stores data inside a computer, an external storage device (also referred to as a storage or a second storage device) that stores data outside a computer, or the like.
  • the external storage device include a memory card and a solid state drive (SSD).
  • the structure of the semiconductor device of one embodiment of the present invention is not limited to the structure in FIG. 1A .
  • the insulator 106 c may be provided to have a shape along the insulator 130 with the semiconductor 106 b and the insulator 106 a therebetween as shown in FIG. 10 .
  • the insulator 112 a may be provided to have a shape along the insulator 130 with the insulator 106 c , the semiconductor 106 b , and the insulator 106 a therebetween.
  • the charge accumulation layer 112 b may be provided to have a shape along the insulator 130 with the insulator 112 a , the insulator 106 c , the semiconductor 106 b , and the insulator 106 a therebetween.
  • the conductors 116 a and 116 b in FIG. 1A can be omitted.
  • the transistors Tr_S 1 and Tr_S 2 may be FIN-type transistors as shown in FIG. 11 .
  • the insulators 120 , 122 , 124 , 126 , 128 , and 130 may each be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • silicon oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.
  • a “silicon oxynitride film” refers to a film that includes oxygen at a higher proportion than nitrogen
  • a “silicon nitride oxide film” refers to a film that includes nitrogen at a higher proportion than oxygen.
  • the insulators 120 , 122 , 124 , 126 , 128 , and 130 have functions of isolating adjacent elements, wirings, and the like in some cases; thus, an insulator with a low dielectric constant is preferably used.
  • an insulator with a dielectric constant of 5 or lower, preferably 4 or lower, or further preferably 3 or lower is used.
  • an insulator containing silicon and oxygen or an insulator containing fluorine in addition to silicon and oxygen, or the like is preferably used.
  • At least one of the insulators 120 , 122 , 124 , 126 , 128 , and 130 may be a space.
  • At least one of the insulators 120 , 122 , 124 , 126 , 128 , and 130 preferably contains an insulator having a function of blocking oxygen and impurities such as hydrogen (a function of not transmitting oxygen or impurities such as hydrogen).
  • an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistors Tr_ 1 to Tr_ 2 n , the electrical characteristics of the transistors Tr_ 1 to Tr_ 2 n can be stable.
  • the adjacent insulator 130 or/and insulator 126 be an insulator including excess oxygen.
  • the excess oxygen can be used to reduce oxygen vacancy in the oxide semiconductor. Note that excess oxygen means oxygen in an insulator or the like which does not bond with (which is liberated from) the insulator or the like or has low bonding energy with the insulator or the like.
  • An insulator including excess oxygen may release oxygen, the amount of which is higher than or equal to 1 ⁇ 10 18 atoms/cm 3 , higher than or equal to 1 ⁇ 10 19 atoms/cm 3 , or higher than or equal to 1 ⁇ 10 20 atoms/cm 3 (converted into the number of oxygen atoms) in thermal desorption spectroscopy (TDS) analysis in the range of a surface temperature of 100° C. to 700° C. inclusive or 100° C. to 500° C. inclusive.
  • TDS thermal desorption spectroscopy
  • the total amount of gas released from a measurement sample in TDS analysis is proportional to the integral value of the ion intensity of the released gas. Then, comparison with a reference sample is made, whereby the total amount of released gas can be calculated.
  • the number of oxygen molecules (N O2 ) released from a measurement sample can be calculated according to the following formula using the TDS results of a silicon substrate containing hydrogen at a predetermined density, which is a reference sample, and the TDS results of the measurement sample.
  • all gases having a mass-to-charge ratio of 32 which are obtained in the TDS analysis are assumed to originate from an oxygen molecule.
  • CH 3 OH which is a gas having the mass-to-charge ratio of 32, is not taken into consideration because it is unlikely to be present.
  • an oxygen molecule including an oxygen atom having a mass number of 17 or 18 which is an isotope of an oxygen atom is not taken into consideration either because the proportion of such a molecule in the natural world is negligible.
  • N O2 N H2 /S H2 ⁇ S O2 ⁇
  • the value N H2 is obtained by conversion of the number of hydrogen molecules desorbed from the reference sample into densities.
  • the value S H2 is the integral value of ion intensity when the reference sample is subjected to the TDS analysis.
  • the reference value of the reference sample is set to N H2 /S H2 .
  • the value S O2 is the integral value of ion intensity when the measurement sample is analyzed by TDS.
  • the value a is a coefficient affecting the ion intensity in the TDS analysis. Refer to Japanese Published Patent Application No. H6-275697 for details of the above formula.
  • the amount of released oxygen was measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W, using a silicon substrate containing a certain amount of hydrogen atoms as the reference sample.
  • oxygen is partly detected as an oxygen atom.
  • the ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of the oxygen molecules. Note that, since the above a includes the ionization rate of the oxygen molecules, the number of the released oxygen atoms can also be estimated through the measurement of the number of the released oxygen molecules.
  • N O2 is the number of the released oxygen molecules.
  • the number of released oxygen in the case of being converted into oxygen atoms is twice the number of the released oxygen molecules.
  • an insulator from which oxygen is released by heat treatment may contain a peroxide radical.
  • the spin density attributed to the peroxide radical is greater than or equal to 5 ⁇ 10 17 spins/cm 3 .
  • the insulator containing a peroxide radical may have an asymmetric signal with a g factor of approximately 2.01 in electron spin resonance (ESR).
  • the insulator 122 preferably includes an insulator having a low oxygen-transmitting property so that the excess oxygen does not enter the transistors Tr_S 1 or Tr_S 2 .
  • the insulator 122 preferably includes an insulator having a low hydrogen-transmitting property.
  • a low-density insulator has a high hydrogen-transmitting property.
  • a high-density insulator has a low hydrogen-transmitting property.
  • the density of a low-density insulator is not always low throughout the insulator; an insulator including a low-density part is also referred to as a low-density insulator. This is because the low-density part serves as a hydrogen path.
  • a density that allows hydrogen to be transmitted is not limited, it is typically lower than 2.6 g/cm 3 .
  • Examples of a low-density insulator include an inorganic insulator such as silicon oxide or silicon oxynitride and an organic insulator such as polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, or acrylic.
  • Examples of a high-density insulator include magnesium oxide, aluminum oxide, germanium oxide, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Note that a low-density insulator and a high-density insulator are not limited to these insulators.
  • the insulators may contain one or more of boron, nitrogen, fluorine, neon, phosphorus, chlorine, and argon.
  • An insulator having crystal grain boundaries can have a high hydrogen-transmitting property.
  • hydrogen is less likely to be transmitted through an insulator having no grain boundaries or few grain boundaries.
  • a non-polycrystalline insulator e.g., an amorphous insulator
  • An insulator having a high hydrogen-bonding energy has a low hydrogen-transmitting property in some cases.
  • the insulator can be in the category of an insulator having a low hydrogen-transmitting property.
  • an insulator which forms a hydrogen compound at higher than or equal to 200° C. and lower than or equal to 1000° C., higher than or equal to 300° C. and lower than or equal to 1000° C., or higher than or equal to 400° C. and lower than or equal to 1000° C. has a low hydrogen-transmitting property in some cases.
  • An insulator which forms a hydrogen compound and which releases hydrogen at higher than or equal to 200° C. and lower than or equal to 1000° C., higher than or equal to 300° C. and lower than or equal to 1000° C., or higher than or equal to 400° C. and lower than or equal to 1000° C. has a low hydrogen-transmitting property in some cases.
  • An insulator which forms a hydrogen compound and which releases hydrogen at higher than or equal to 20° C. and lower than or equal to 400° C., higher than or equal to 20° C. and lower than or equal to 300° C., or higher than or equal to 20° C. and lower than or equal to 200° C. has a high hydrogen-transmitting property in some cases. Hydrogen which is released easily and liberated can be referred to as excess hydrogen.
  • the charge accumulation layer 112 b may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • the insulators 112 a and 112 c may each be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.
  • the charge accumulation layer 112 b is provided between the insulators 112 a and 112 c .
  • the charge accumulation layer 112 b has a function of accumulating electrons.
  • an insulator including an electron trap is suitable for the charge accumulation layer 112 b .
  • the electron trap can be formed by addition of impurities, application of damages, or the like.
  • the electron trap may be formed at an interface between the charge accumulation layer 112 b and the insulator 112 a or at an interface between the charge accumulation layer 112 b and the insulator 112 c .
  • junction of different kinds of materials is preferably formed between the charge accumulation layer 112 b and the insulator 112 a and between the charge accumulation layer 112 b and the insulator 112 c .
  • the insulator 112 c is not necessarily provided in some cases.
  • the interface between the charge accumulation layer 112 b and the insulator 112 c includes an electron trap, the insulator 112 a is not necessarily provided in some cases.
  • electrons are preferably less likely to move in the charge accumulation layer 112 b because the charge accumulation layer 112 b is shared with the adjacent memory cells. Note that when the adjacent memory cells and the charge accumulation layer 112 b are separated, electrons can move in the charge accumulation layer 112 b . That is, the charge accumulation layer 112 b may be a semiconductor or a conductor.
  • the insulators 112 a and 112 c each preferably have a thickness which leads to electron tunneling by the gate voltage or the back gate voltage so that electrons are injected to the charge accumulation layer 112 b .
  • the thickness is preferably such a thickness that electron tunneling does not occur when the gate voltage or the back gate voltage is not applied. Note that it is difficult to totally eliminate electron tunneling; therefore, the insulators 112 a and 112 c may have a thickness at which data can be stored and electron tunneling does not occur.
  • the thickness of the insulators 112 a and 112 c may be greater than or equal to 3 nm and less than or equal to 15 nm, preferably greater than or equal to 4 nm and less than or equal to 10 nm.
  • An insulator with a large energy gap is preferably used so that electron leakage is prevented.
  • the energy gaps of the insulators 112 a and 112 c are, for example, larger than or equal to 6 eV and smaller than or equal to 10 eV, preferably larger than or equal to 7 eV and smaller than or equal to 10 eV, further preferably larger than or equal to 8 eV and smaller than or equal to 10 eV.
  • silicon nitride, silicon nitride oxide, or hafnium oxide that has high density of defect states is preferably used for the charge accumulation layer 112 b .
  • Silicon oxide or silicon oxynitride is preferably used for the insulators 112 a and 112 c.
  • the conductors 154 , 140 , 142 , 144 , 146 , 148 , 104 , 116 a , 116 b , 132 , 134 , 136 , and 138 each may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds of, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten.
  • An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.
  • the insulator 106 a , the semiconductor 106 b , and the insulator 106 c will be described below.
  • Placing the insulator 106 a under the semiconductor 106 b and placing the insulator 106 c over the semiconductor 106 b can improve electrical characteristics of the transistor in some cases.
  • the insulator 106 a , the semiconductor 106 b , and the insulator 106 c each preferably include a CAAC-OS.
  • the semiconductor 106 b is an oxide containing indium, for example.
  • the semiconductor 106 b can have high carrier mobility (electron mobility) by containing indium, for example.
  • the semiconductor 106 b preferably contains an element M.
  • the element M is preferably aluminum, gallium, yttrium, tin, or the like.
  • Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. Note that two or more of the above elements may be used in combination as the element M in some cases.
  • the element M is an element having a high bonding energy with oxygen, for example.
  • the element M is an element whose bonding energy with oxygen is higher than that of indium.
  • the element M is an element that can increase the energy gap of the oxide, for example.
  • the semiconductor 106 b preferably contains zinc. When containing zinc, the oxide is easily crystallized in some cases.
  • the semiconductor 106 b is not limited to the oxide containing indium.
  • the semiconductor 106 b may be, for example, an oxide which does not contain indium and contains zinc, gallium, tin, or the like such as a zinc tin oxide or a gallium tin oxide.
  • the semiconductor 106 b is formed using, for example, an oxide with a wide energy gap.
  • the energy gap of the semiconductor 106 b is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, further preferably greater than or equal to 3 eV and less than or equal to 3.5 eV.
  • the insulators 106 a and 106 c are each an oxide containing one or more or two or more elements contained in the semiconductor 106 b other than oxygen, for example. Since the insulators 106 a and 106 c each contain one or more or two or more elements contained in the semiconductor 106 b other than oxygen, a defect state is less likely to be formed at the interface between the insulator 106 a and the semiconductor 106 b and the interface between the semiconductor 106 b and the insulator 106 c.
  • the insulator 106 a , the semiconductor 106 b , and the insulator 106 c preferably contain at least indium.
  • the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than 75 atomic %, respectively.
  • the proportions of In and M are preferably set to be greater than 25 atomic % and less than 75 atomic %, respectively, and further preferably greater than 34 atomic % and less than 66 atomic %, respectively.
  • the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than 75 atomic %, respectively.
  • the insulator 106 c may be an oxide that is of the same type as the oxide of the insulator 106 a .
  • the insulator 106 a and/or the insulator 106 c do/does not necessarily contain indium in some cases.
  • the insulator 106 a and/or the insulator 106 c may be gallium oxide.
  • the atomic ratio between the elements contained in the insulator 106 a , the semiconductor 106 b , and the insulator 106 c is not necessarily a simple integer ratio.
  • an oxide having an electron affinity higher than those of the insulators 106 a and 106 c is used.
  • an oxide having an electron affinity higher than those of the insulators 106 a and 106 c by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, and further preferably 0.15 eV or higher and 0.4 eV or lower is used.
  • the electron affinity refers to an energy difference between the vacuum level and the bottom of the conduction band.
  • the insulator 106 c preferably includes an indium gallium oxide.
  • the gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, further preferably higher than or equal to 90%.
  • the stack including the insulator 106 a , the semiconductor 106 b , and the insulator 106 c has a band structure where energy is changed continuously at each interface and in the vicinity of the interface (continuous junction) (see FIG. 12 ). Note that boundaries of the insulator 106 a , the semiconductor 106 b , and the insulator 106 c are not clear in some cases.
  • the insulator 106 a and the insulator 106 c can exhibit a property of any of a conductor, a semiconductor, and an insulator when existing alone.
  • the transistor When the transistor operates, they each, however, have a region where a channel is not formed. Specifically, a channel is formed only in a region near the interface between the insulator 106 a and the semiconductor 106 b and a region near the interface between the insulator 106 c and the semiconductor 106 b , whereas a channel is not formed in the other region.
  • the insulator 106 a and the insulator 106 c can be called insulators when the transistor operates, and are thus referred to as, not semiconductors or conductors, but insulators in this specification.
  • the insulator 106 a , the semiconductor 106 b , and the insulator 106 c are separately called semiconductor or insulator only because of the relative difference in physical property. Therefore, for example, an insulator that can be used as the insulator 106 a or the insulator 106 c can be used as the semiconductor 106 b in some cases.
  • the on-state current of the transistor can be increased. For example, in the case where there is no factor in inhibiting electron movement, electrons are assumed to be moved efficiently. Electron movement is also inhibited, for example, in the case where physical unevenness in a channel formation region is large.
  • root mean square (RMS) roughness with a measurement area of 1 ⁇ m ⁇ 1 ⁇ m of the top or bottom surface of the semiconductor 106 b (a formation surface; here, the top surface of the insulator 106 a ) is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm.
  • the average surface roughness (also referred to as Ra) with the measurement area of 1 ⁇ m ⁇ 1 ⁇ m is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm.
  • the maximum difference (also referred to as P ⁇ V) with the measurement area of 1 ⁇ m ⁇ 1 ⁇ m is less than 10 nm, preferably less than 9 nm, further preferably less than 8 nm, still further preferably less than 7 nm.
  • RMS roughness, Ra, and P ⁇ V can be measured using, for example, a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc.
  • the thickness of the insulator 106 c is preferably as small as possible to increase the on-state current of the transistor.
  • the insulator 106 c is formed to include a region having a thickness of less than 10 nm, preferably less than or equal to 5 nm, further preferably less than or equal to 3 nm.
  • the insulator 106 c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 106 b where a channel is formed. For this reason, it is preferable that the insulator 106 c have a certain thickness.
  • the insulator 106 c is formed to include a region having a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, further preferably greater than or equal to 2 nm.
  • the insulator 106 c preferably has an oxygen blocking property to suppress outward diffusion of oxygen released from the other insulators.
  • the insulator 106 a is preferably thick and the insulator 106 c is preferably thin.
  • the insulator 106 a includes a region with a thickness of, for example, greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 40 nm, still further preferably greater than or equal to 60 nm.
  • a thickness of the insulator 106 a is made large, a distance from an interface between the adjacent insulator and the insulator 106 a to the semiconductor 106 b in which a channel is formed can be large.
  • the insulator 106 a has a region with a thickness of, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, further preferably less than or equal to 80 nm.
  • SIMS secondary ion mass spectrometry
  • the semiconductor 106 b includes a region with a hydrogen concentration measured by SIMS of higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 2 ⁇ 10 20 atoms/cm 3 , preferably higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 5 ⁇ 10 19 atoms/cm 3 , further preferably higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 1 ⁇ 10 19 atoms/cm 3 , and still further preferably higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 5 ⁇ 10 18 atoms/cm 3 .
  • the insulator 106 a and the insulator 106 c each include a region with a hydrogen concentration measured by SIMS of higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 2 ⁇ 10 20 atoms/cm 3 , preferably higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 5 ⁇ 10 19 atoms/cm 3 , further preferably higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 1 ⁇ 10 19 atoms/cm 3 , and still further preferably higher than or equal to 1 ⁇ 10 16 atoms/cm 3 and lower than or equal to 5 ⁇ 10 18 atoms/cm 3 .
  • the semiconductor 106 b includes a region with a nitrogen concentration measured by SIMS of higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 5 ⁇ 10 19 atoms/cm 3 , preferably higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 5 ⁇ 10 18 atoms/cm 3 , further preferably higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 1 ⁇ 10 18 atoms/cm 3 , and still further preferably higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 5 ⁇ 10 17 atoms/cm 3 .
  • the insulator 106 a and the insulator 106 c each include a region with a nitrogen concentration measured by SIMS of higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 5 ⁇ 10 19 atoms/cm 3 , preferably higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 5 ⁇ 10 18 atoms/cm 3 , further preferably higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 1 ⁇ 10 18 atoms/cm 3 , and still further preferably higher than or equal to 1 ⁇ 10 15 atoms/cm 3 and lower than or equal to 5 ⁇ 10 17 atoms/cm 3 .
  • the above three-layer structure is an example.
  • a two-layer structure including the semiconductor 106 b and the insulator 106 a or including the semiconductor 106 b and the insulator 106 c may be employed.
  • a four-layer structure in which any one of the semiconductors described as examples of the insulator 106 a , the semiconductor 106 b , and the insulator 106 c is provided under or over the insulator 106 a or under or over the insulator 106 c may be employed.
  • n-layer structure (n is an integer of 5 or more) may be employed in which one of the semiconductors described as examples of the insulator 106 a , the semiconductor 106 b , and the insulator 106 c is provided at two or more of the following positions: over the insulator 106 a , under the insulator 106 a , over the insulator 106 c , and under the insulator 106 c.
  • the composition of an In-M-Zn oxide will be described below.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like.
  • FIG. 13 is a triangular diagram whose vertices represent In, M, and Zn.
  • [In] means the atomic concentration of In
  • [M] means the atomic concentration of the element M
  • [Zn] means the atomic concentration of Zn.
  • a crystal of an In-M-Zn oxide is known to have a homologous structure and is represented by InMO 3 (ZnO) m (m is a natural number). Since In and M can be interchanged, the crystal can also be represented by In 1+ ⁇ M 1 ⁇ O 3 (ZnO) m ( ⁇ 1 ⁇ 1).
  • the bold lines on the dashed lines represent, for example, the compositions that each allow oxides (raw materials) to be a solid solution when the oxides are mixed and subjected to baking at 1350° C.
  • the crystallinity can be increased.
  • the composition of a target is different from the composition of the deposited film in some cases.
  • a composition of a target may be selected in consideration of a change in the composition.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and the other, a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
  • an oxide semiconductor is classified into an amorphous oxide semiconductor and the other, a crystalline oxide semiconductor.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and not have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.
  • a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic e.g., an oxide semiconductor that has a periodic structure in a microscopic region
  • an a-like OS which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.
  • a CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • This peak is derived from the (009) plane of the InGaZnO 4 crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or the top surface of the CAAC-OS film.
  • a peak sometimes appears at a 2 ⁇ of around 36° in addition to the peak at a 2 ⁇ of around 31°.
  • the peak at a 2 ⁇ of around 36° is derived from a crystal structure classified into the space group Fd ⁇ 3m. Therefore, it is preferable that the CAAC-OS do not show the peak.
  • a CAAC-OS analyzed by electron diffraction will be described.
  • a diffraction pattern also referred to as a selected-area electron diffraction pattern
  • spots derived from the (009) plane of an InGaZnO 4 crystal are included.
  • the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS.
  • FIG. 14E shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 14E , a ring-like diffraction pattern is observed.
  • the electron diffraction using an electron beam with a probe diameter of 300 nm also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular orientation.
  • the first ring in FIG. 14E is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO 4 crystal.
  • the second ring in FIG. 14E is considered to be derived from the (110) plane and the like.
  • a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM)
  • TEM transmission electron microscope
  • a boundary between pellets, that is, a grain boundary is not clearly observed in some cases.
  • a reduction in electron mobility due to the grain boundary is less likely to occur.
  • FIG. 15A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface.
  • the high-resolution TEM image is obtained with a spherical aberration corrector function.
  • the high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 15A shows pellets in which metal atoms are arranged in a layered manner.
  • FIG. 15A proves that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc).
  • the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC).
  • a pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS, and is parallel to the formation surface or the top surface of the CAAC-OS.
  • FIGS. 15B and 15C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface.
  • FIGS. 15D and 15E are images obtained through image processing of FIGS. 15B and 15C .
  • the method of image processing is as follows. The image in FIG. 15B is subjected to fast Fourier transform (FFT), so that an FFT image is obtained. Then, mask processing is performed such that a range of from 2.8 nm ⁇ 1 to 5.0 nm ⁇ 1 from the origin in the obtained FFT image remains. After the mask processing, the FFT image is processed by inverse fast Fourier transform (IFFT) to obtain a processed image. The image obtained in this manner is called an FFT filtering image.
  • the FFT filtering image is a Cs-corrected high-resolution TEM image from which a periodic component is extracted, and shows a lattice arrangement.
  • FIG. 15D a portion where a lattice arrangement is broken is shown by a dashed line.
  • a region surrounded by the dashed line is one pellet.
  • the portion denoted with the dashed line is a junction of pellets.
  • the dashed line draws a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases.
  • a dotted line denotes a boundary between a region with a regular lattice arrangement and another region with a regular lattice arrangement.
  • a clear crystal grain boundary cannot be observed even in the vicinity of the dotted line.
  • a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, pentagon, and/or heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of the atomic arrangement in an a-b plane direction, an interatomic bond distance changed by substitution of a metal element, and the like.
  • the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion.
  • the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element specifically, silicon or the like
  • a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • Impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources, for example.
  • oxygen vacancy in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source when hydrogen is captured therein.
  • the CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, lower than 8 ⁇ 10 11 /cm 3 , preferably lower than 1 ⁇ 10 11 /cm 3 , further preferably lower than 1 ⁇ 10 10 /cm 3 , and is higher than or equal to 1 ⁇ 10 ⁇ 9 /cm 3 ).
  • Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • a CAAC-OS has a low impurity concentration and a low density of defect states.
  • the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.
  • nc-OS Analysis of an nc-OS by XRD will be described.
  • a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.
  • FIG. 16A shows a ring-like diffraction pattern (a nanobeam electron diffraction pattern) shown in FIG. 16A.
  • FIG. 16B shows a diffraction pattern obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. As shown in FIG. 16B , a plurality of spots are observed in a ring-like region. In other words, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm.
  • an electron diffraction pattern in which spots are arranged in an approximately hexagonal shape is observed in some cases as shown in FIG. 16C when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm.
  • an nc-OS has a well-ordered region, i.e., a crystal, in the range of less than 10 nm in thickness.
  • an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions.
  • FIG. 16D shows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed from the direction substantially parallel to the formation surface.
  • an nc-OS has a region in which a crystal part is observed, such as the part indicated by additional lines in FIG. 16D , and a region in which a crystal part is not clearly observed.
  • the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or specifically, greater than or equal to 1 nm and less than or equal to 3 nm.
  • an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor.
  • a grain boundary is not always found clearly.
  • a crystal part of the nc-OS may be referred to as a pellet in the following description.
  • a microscopic region for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm
  • a microscopic region has a periodic atomic arrangement.
  • the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.
  • the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).
  • RNC random aligned nanocrystals
  • NANC non-aligned nanocrystals
  • the nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
  • An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.
  • FIGS. 17A and 17B are high-resolution cross-sectional TEM images of an a-like OS.
  • FIG. 17A is the high-resolution cross-sectional TEM image of the a-like OS at the start of the electron irradiation.
  • FIG. 17B is the high-resolution cross-sectional TEM image of the a-like OS after the electron (e ⁇ ) irradiation at 4.3 ⁇ 10 8 e ⁇ /nm 2 .
  • FIGS. 17A and 17B show that stripe-like bright regions extending vertically are observed in the a-like OS from the start of the electron irradiation. It can be also found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region.
  • the a-like OS has an unstable structure because it contains a void.
  • an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation will be described below.
  • An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.
  • a unit cell of an InGaZnO 4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Accordingly, the spacing between these adjacent layers is equivalent to the lattice spacing (also referred to as d value) on the (009) plane. The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO 4 in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO 4 crystal.
  • FIG. 18 shows change in the average size of crystal parts (at 22 points to 30 points) in each sample. Note that the crystal part size corresponds to the length of the lattice fringe. FIG. 18 indicates that the size of the crystal part in the a-like OS increases with an increase in the cumulative electron dose in obtaining TEM images, for example. As shown in FIG. 18 , a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e ⁇ ) dose of 4.2 ⁇ 10 8 e ⁇ /nm 2 .
  • e ⁇ cumulative electron
  • the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2 ⁇ 10 8 e ⁇ /nm 2 .
  • the crystal part sizes in an nc-OS and a CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose.
  • a Hitachi H-9000NAR transmission electron microscope was used for observation of electron beam irradiation and TEM.
  • the conditions of electron beam irradiations were as follows: the accelerating voltage was 300 kV; the current density was 6.7 ⁇ 10 5 e ⁇ /(nm 2 ⁇ s); and the diameter of irradiation region was 230 nm.
  • the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
  • the a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void.
  • the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition.
  • the density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.
  • the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm 3 and lower than 6.3 g/cm 3 .
  • the density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.
  • oxide semiconductors have various structures and various properties.
  • an oxide semiconductor may be a stacked layer including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

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