US20040178429A1 - Thin film transistor and method for manufacturing same - Google Patents

Thin film transistor and method for manufacturing same Download PDF

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US20040178429A1
US20040178429A1 US10/793,845 US79384504A US2004178429A1 US 20040178429 A1 US20040178429 A1 US 20040178429A1 US 79384504 A US79384504 A US 79384504A US 2004178429 A1 US2004178429 A1 US 2004178429A1
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thin film
silicon thin
polycrystalline silicon
insulating film
hydrogen
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Hiroaki Tanaka
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NEC Corp
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NEC LCD Technologies Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Definitions

  • the present invention relates to a thin film transistor (TFT) and a method for manufacturing the same and more particularly to the TFT using a polycrystalline semiconductor thin film formed on an insulating substrate as an active layer and to the method for manufacturing the TFT.
  • TFT thin film transistor
  • Silicon is widely used as a semiconductor material for manufacturing a semiconductor device typified by an LSI (Large Scale Integrated) circuit.
  • LCD liquid crystal display
  • contact-type image sensor and a like.
  • a TFT for a pixel being connected to a liquid crystal pixel placed in a matrix form is employed.
  • Such the TFT has a MOS (Metal Oxide Semiconductor) -type structure in which an amorphous silicon thin film deposited at temperatures being lower than those employed when a single crystal silicon is deposited, or a polycrystalline silicon is deposited on a transparent insulating substrate such as a glass substrate (hereinafter may referred simply to as an “insulating substrate”), and a source region and a drain region are formed by implanting an impurity using an ion doping method.
  • MOS Metal Oxide Semiconductor
  • An amorphous silicon thin film as described above, has an advantage in that it can be deposited at relatively low temperatures, which enables the TFT to be manufactured by using, as the insulating substrate, a low-priced glass substrate having low heat resistance and in that it is excellent in mass productivity. Therefore, such the amorphous silicon thin film is widely used in LCDs, or a like.
  • the amorphous silicon thin film has a disadvantage. That is, since the amorphous silicon thin film has no crystalline property, which causes its crystal grain to be small, it provides low carrier mobility.
  • a driving TFT used in a driving circuit of an LCD is manufactured using such the amorphous silicon thin film at the same time when the TFT to be used for a pixel as above is manufactured, driving capability and operation speed of the driving circuit become low. Because of this, in an LCD using an amorphous silicon thin film as a TFT for a pixel, in many cases, a driving TFT in the driving circuit is employed in a form of an externally mounted component. In recent years, however, in an LCD, a need for being made thin and small-sized is increasing due to diversity of its applications and, as a result, a connecting pitch between the LCD and driving circuit on an insulating substrate becomes narrow and small. Therefore, if the driving circuit uses a driving TFT in a form of an externally mounted component, constraints are added when the connecting pitch has to be made narrow and small, which makes it difficult to achieve a large-screen and high-definition LCD.
  • the polycrystalline silicon thin film instead of an amorphous silicon thin film, the polycrystalline silicon thin film, since it has a crystalline property to some extent, which causes its crystal grain to be larger than that of the amorphous silicon thin film, provides carrier mobility being higher than that of the amorphous silicon thin film. Therefore, in an LCD using a polycrystalline silicon thin film as a pixel TFT, by manufacturing a driving TFT using the polycrystalline silicon thin film at the same time when the pixel TFT is manufactured, driving capability and operation speed of a driving circuit can be improved.
  • the driving TFT and pixel TFT can be integrally formed on an insulating substrate, a connecting pitch between an LCD and driving circuit can be made narrow and small, thus enabling the LCD to be made thin and small sized. Therefore, a TFT using a polycrystalline silicon thin film tends to be preferably employed.
  • the dangling bond acts as a factor that increases a trap density in a grain boundary in the polycrystalline silicon, carrier mobility of the polycrystalline silicon becomes low and an increase in a threshold voltage or a like occurs, which produces a problem that a characteristic of a transistor is degraded.
  • a method of hydrogenating the dangling bond is conventionally employed in which, by feeding hydrogen to the dangling bond and diffusing hydrogen into the dangling bond, an orbit being in a nonbonded state for a polycrystalline silicon is bonded to a hydrogen atom for being terminated. More concretely, in the hydrogenation of the dangling bond, by performing heat treatment, after having formed, in advance, a hydrogen feeding layer containing, hydrogen, within a part of a TFT, or by performing heat treatment in an atmosphere containing hydrogen, hydrogen is made to be diffused into the dangling bond.
  • a TFT in which such a hydrogen feeding layer for hydrogenation as described above is formed is disclosed in, for example, in Japanese Patent Application Laid-open No. Hei 6-77484 (first conventional example).
  • the disclosed TFT 100 as shown in FIG.
  • insulating substrate 101 made up of a glass substrate, a polycrystalline silicon thin film 102 formed on the insulating substrate 101 , a source region 103 formed on one end of the polycrystalline silicon thin film 102 , a drain region 104 formed on the other end of the polycrystalline silicon thin film 102 , a channel region 105 formed between the source region 103 and drain region 104 , a gate insulating film 106 made up of a silicon dioxide film formed on the polycrystalline silicon region 102 , and a gate electrode 107 formed on the gate insulating film 106 .
  • the disclosed TFT 100 further includes an interlayer dielectric 108 made up of a silicon dioxide film formed on an entire surfaces being exposed containing a surface of the gate electrode 107 , contact holes 109 A and 109 B formed in the interlayer dielectric 108 , a source electrode 110 made up of an aluminum film formed so as to be connected to the source region 103 , a drain electrode 111 made up of an aluminum film formed so as to be connected to the drain region 104 , and a passivation film 112 made up of silicon nitride (Si 3 N 4 ) containing much hydrogen on entire surfaces being exposed including surfaces of the source electrode 110 and the drain electrode 111 .
  • an interlayer dielectric 108 made up of a silicon dioxide film formed on an entire surfaces being exposed containing a surface of the gate electrode 107 , contact holes 109 A and 109 B formed in the interlayer dielectric 108 , a source electrode 110 made up of an aluminum film formed so as to be connected to the source region 103 , a drain electrode 111 made up of
  • the hydrogenation is achieved by performing heat treatment, at 300° C. to 450° C., on the passivation film 112 serving as the hydrogen feeding layer to diffuse hydrogen contained in the hydrogen feeding layer in the dangling bond at an interface between the polycrystalline silicon thin film 102 and the gate insulating film 106 .
  • the disclosed TFT 120 includes a lower layer polycrystalline thin film 121 formed on an insulating substrate 101 , a hydrogen feeding layer 122 containing much hydrogen made up of a silicon nitride film and formed on the lower layer polycrystalline thin film 121 , and an upper layer polycrystalline thin film 123 , serving as an active layer, formed on the hydrogen feeding layer 122 in a manner to confine the hydrogen feeding layer 122 .
  • same reference numbers are assigned to components having the same functions as those shown in FIG. 9 and descriptions of them are omitted accordingly.
  • the hydrogen feeding layer 122 is formed directly below the upper polycrystalline thin film 123 serving as the active layer and, therefore, the hydrogen feeding layer 122 is placed close to the interface between the upper polycrystalline silicon thin film 123 to be used for diffusing hydrogen and the gate insulating film 106 , which enables the diffusing distance of hydrogen to be shortened. As a result, a sufficient hydrogenation process can be performed without much time being taken in the heat treatment.
  • FIGS. 11 Ato 11 E main processes of manufacturing the TFT 120 of the second conventional example are explained by referring to FIGS. 11 Ato 11 E.
  • a laser beam for example, such as an exima laser
  • the hydrogen feeding layer 122 is formed on the lower polycrystalline silicon thin film 121 made up of a silicon nitride film containing much hydrogen by using the P-CVD method.
  • FIG. 11C patterning is performed by a photolithography method on the hydrogen feeding layer 122 so as to have a desired shape.
  • the upper polycrystalline silicon thin film 123 is deposited on entire surfaces being exposed including a surface of the hydrogen feeding layer by the same method as employed when the lower polycrystalline silicon thin film 121 is deposited.
  • patterning is performed by the photolithography method on the lower polycrystalline silicon thin film 121 and the upper polycrystalline silicon film 123 at the same time so as to have a desired shape.
  • the structure as shown in FIG. 10 is obtained in which the hydrogen feeding layer 122 is confined between the lower polycrystalline thin film 121 and upper polycrystalline thin film 123 .
  • the conventional TFT and conventional method for manufacturing the same disclosed in Japanese Patent Application Laid-open No. Hei 6-77484 described above have a problem in that, in the disclosed technology, the photolithgraphy process required to form the hydrogen feeding layer are increased, which causes a rise in manufacturing costs. That is, as described above, to manufacture the conventional TFT 20 as shown in FIG. 10, by using the manufacturing processes shown in FIGS. 11A to 11 E, the structure has to be formed in which the hydrogen feeding layer 122 is confined between the lower polycrystalline silicon thin film 121 and the upper polycrystalline silicon thin film 123 . However, as shown in FIG. 11C, to perform patterning on the hydrogen feeding layer 122 so as to have a desired shape, it is necessary to use additional photolithography processes.
  • the lower polycrystalline silicon thin film 121 has to be deposited, which requires additional P-CVD processes. Such the increase in manufacturing processes causes reduction in yields, thus causing a rise in costs of manufacturing TFTs.
  • a thin film transistor including:
  • a gate electrode formed on the polycrystalline silicon thin film with a gate insulating film interposed between the polycrystalline silicon thin film and the gate electrode;
  • a hydrogen feeding layer to feed hydrogen into an interface between the polycrystalline silicon thin film and the gate insulating film is formed in a position between the gate insulating film and the gate electrode.
  • a preferable mode is one wherein configurations of the hydrogen feeding layer are approximately same as those of the gate electrode.
  • a preferable mode is one wherein the gate insulating film is made up of a silicon dioxide film.
  • a method for manufacturing a thin film transistor having a source region and a drain region formed in a polycrystalline silicon thin film and a gate electrode formed on the polycrystalline silicon thin film with a gate insulating film interposed between the polycrystalline silicon thin film and the gate electrode including:
  • a preferable mode is one wherein the process of feeding hydrogen is performed in an atmosphere containing hydrogen plasma.
  • a preferable mode is one that wherein includes a process of forming, after the process of feeding hydrogen, contact holes in the first insulating film and the gate insulating film in a manner to expose the source region and the drain region and forming a source electrode to be connected to the source region through one of the contact holes and a drain electrode to be connected to the drain region through the other of the contact holes and a process of forming a second insulating film on entire surfaces being exposed containing surfaces of the source electrode and the drain electrode.
  • a preferable mode is one wherein processes following the process of forming the micro-crystalline silicon thin film are performed at a temperature being lower than about 400° C.
  • a preferable mode is one wherein the gate insulating film includes a silicon dioxide film.
  • a method for manufacturing a thin film transistor having a source region and a drain region formed on a polycrystalline silicon thin film and a gate electrode formed in the polycrystalline silicon thin film with a gate insulating film interposed between the polycrystalline silicon thin film and the gate electrode including:
  • the process of forming the first insulating film is performed at 300° C. to 400° C. to feed hydrogen from the hydrogen feeding layer into an interface between the polycrystalline silicon thin film and the gate insulating film.
  • a preferable mode is one wherein a step in an atmosphere containing hydrogen plasma is contained in the process of forming the first insulating film to feed hydrogen.
  • a method for manufacturing a thin film transistor having a source region and a drain region formed on a polycrystalline silicon thin film and a gate electrode formed in the polycrystalline silicon thin film with a gate insulating film interposed between the polycrystalline silicon thin film and the gate electrode including:
  • a preferable mode is one wherein a step in an atmosphere containing hydrogen plasma is contained in the process of forming the first insulating film to feed hydrogen or in the process of forming the second insulating film.
  • a method for manufacturing a thin film transistor having a source region and a drain region formed on a polycrystalline silicon thin film and a gate electrode formed in the polycrystalline silicon thin film with a gate insulating film interposed between the polycrystalline silicon thin film and the gate electrode including:
  • a process of selectively implanting a desired impurity of a conductive type on the polycrystalline silicon thin film to form the source region and the drain region wherein any one of processes following processes of forming the micro-crystalline silicon thin film is performed at 300° C. to 400° C. to feed hydrogen from the hydrogen feeding layer into an interface between the polycrystalline silicon thin film and the gate insulating film.
  • the hydrogen feeding layer to diffuse hydrogen into an interface between the polycrystalline silicon thin film and the gate insulating film is formed in a position between the gate insulating film and the gate electrode and, therefore, diffusing distance of hydrogen at a period of time during hydrogenation can be made short.
  • the micro-crystalline silicon thin film and the metal thin film are sequentially deposited on the gate insulating film and then the tungsten silicide thin film and metal thin film are sequentially and selectively etched to form the gate electrode and the hydrogen feeding layer and, therefore, an independent process of photolithography to form the hydrogen feeding layer is not needed.
  • the hydrogen feeding layer can be formed in a position where diffusing distance of hydrogen can be made short without causing an increase in the processes of photolithography.
  • FIG. 1 is a cross-sectional view showing configurations of a TFT according to a first embodiment of the present invention
  • FIGS. 2A to 2 C are process diagrams showing a method for manufacturing the TFT according to the first embodiment in order of processes
  • FIGS. 3D to 3 F are process diagrams showing the method for manufacturing the TFT according to the first embodiment in order of processes
  • FIGS. 4G to 4 I are process diagrams showing the method for manufacturing the TFT according to the first embodiment in order of processes
  • FIGS. 5J to 5 I are process diagrams showing the method for manufacturing the TFT according to the first embodiment in order of processes
  • FIG. 6 is a process diagram showing a main process being employed in a method of manufacturing a TFT according to a second embodiment of the present invention.
  • FIG. 7 is a process diagram showing a main process being employed in the method of manufacturing a TFT according to a third embodiment of the present invention.
  • FIG. 8 is a process diagram showing a main process being employed in a method of manufacturing a TFT according to a fourth embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of a conventional TFT (first conventional example).
  • FIG. 10 is a cross-sectional view showing configuration of another conventional TFT (second conventional example).
  • FIGS. 11A to 11 E are cross-sectional view showing main processes being used in a method manufacturing the other conventional TFT (second conventional example).
  • FIG. 1 is a cross-sectional view showing a configuration of a TFT according to a first embodiment of the present invention.
  • FIGS. 2A to 5 L are process diagrams showing a method for manufacturing the TFT according to the first embodiment in order of processes.
  • a TFT 10 of the first embodiment includes an insulating substrate 1 , an underlying insulation film 2 , an N-type source region 4 , an N-type drain region 5 , a channel region 6 , a gate insulating film 7 , a hydrogen feeding layer 8 and a gate electrode 9 .
  • the insulating substrate 1 is made up of, for example, an “OA2 substrate” (brand name of a substrate produced by Nippon Electric Glass Co., Ltd.).
  • the underlying insulation film 2 is made up of a silicon dioxide film having its film thickness of 80 nm to 120 nm.
  • a polycrystalline silicon thin film 3 having its film thickness of 70 nm to 80 nm, in one end region of which an N-type source region 4 is formed, in another end region of which an N-type drain region 5 is formed, and in a center region of which a channel region 6 is formed between the N-type source region 4 and the N-type drain region 5 .
  • the gate insulating film 7 is made up of a silicon dioxide film having its film thickness of 35 nm to 45 nm formed on the polycrystalline silicon thin film 3 .
  • the hydrogen feeding layer 8 is formed on the gate insulating film 7 and made up of a micro-crystalline silicon thin film having its film thickness of 60 nm to 80 nm.
  • the gate electrode 9 is formed on the hydrogen feeding layer 8 and made up of a tungsten silicide thin film having its film thickness of 80 nm to 120 nm.
  • the TFT 10 also includes an interlayer dielectric (first interlayer dielectric) 11 formed on entire surfaces of lower layers thereof including a surface of the gate electrode 9 and made up of a silicon nitride film having its film thickness of 280 nm to 320 nm, a source electrode 13 made up of an aluminum film having its film thickness of 370 nm to 430 nm and formed so that it is connected to the source region 4 through a contact hole 12 A formed in the interlayer dielectric 11 and gate insulating film 7 , a drain electrode 14 made up of an aluminum film having its film thickness of 370 nm to 430 nm and formed so that it is connected to the drain region 5 through a contact hole 12 B formed in the interlayer dielectric 11 and gate insulating film 7 , and a passivation film (second insulating film) 15 made up of a silicon nitride film having its film thickness of 250 nm to 280 nm and formed on entire surfaces of lower layers thereof
  • the hydrogen feeding layer 8 for performing hydrogenation is formed in a position between the gate insulating film 7 and gate electrode 9 , a distance between the hydrogen feeding layer 8 and an interface between the polycrystalline silicon thin film 3 to be used for diffusion of hydrogen and the gate insulating film 7 is made short. Therefore, since diffusing distance of hydrogen is shortened at a period of time during the hydrogenation, it becomes possible to perform a sufficient hydrogenation without taking much time in the heat treatment. As a result, since a trap density in a grain boundary in the polycrystalline silicon becomes small, a decrease in carrier mobility of the polycrystalline silicon can be prevented and since a threshold voltage drops, a transistor characteristic is improved.
  • the insulating substrate 1 made up of, for example, “OA2 substrate” (brand name of a substrate produced by Nippon Electric Glass Co., Ltd.) is prepared and an underlying insulation film 2 made up of a silicon dioxide film having its film thickness of 80 nm to 120 nm is deposited on the insulating substrate 1 by a P-CVD method using SiH 4 (mono-silane) and N 2 O (nitrogen oxide) as reactant gas.
  • an amorphous silicon thin film 16 having its film thickness of 70 nm to 80 nm is deposited on the underlying insulation film 2 by a low-pressure CVD method using Si 2 H 6 (di-silane) as reactant gas.
  • a laser beam such as an exima laser is applied to the amorphous silicon thin film 16 to crystallize it and to change the amorphous silicon thin film 16 to be the polycrystalline silicon thin film 3 , as shown in FIG. 2B.
  • the polycrystalline silicon thin film 3 is etched selectively to be of an island-structure having a desired shape by a dry etching method using the resist mask layer 17 with CF 4 (carbon tetrafluoride) and O 2 (oxygen) as etching gas.
  • CF 4 carbon tetrafluoride
  • O 2 oxygen
  • the gate insulating film 7 made up of a silicon dioxide having its film thickness of 35 nm to 45 nm is formed on entire surfaces being exposed including the surface of the island-structured polycrystalline silicon thin film 3 by a low-pressure CVD method using SiH 4 and O 2 as reactant gas. Then, by the P-CVD method using SiH 4 , PH 3 (phosphine), and H 2 (hydrogen) as reactant gas, a micro-crystalline silicon thin film 18 serving as a hydrogen feeding layer and having its film thickness of 60 nm to 80 nm is deposited on the gate insulating film 7 .
  • the micro-crystalline silicon thin film 18 has a phase being intermediate between an amorphous silicon and a polycrystalline silicon and contains much hydrogen.
  • a tungsten silicide thin film (metal thin film) 19 having its film thickness of 80 nm to 120 nm is deposited by a sputtering method on the micro-crystalline silicon thin film 18 .
  • the tungsten silicide thin film 19 is etched selectively to form a gate electrode 9 by a dry etching method using the resist mask layer 20 and employing CF 4 (carbon tetrafluoride) and O 2 (oxygen) as etching gas. While the gate electrode 9 is being formed, by using etching gas having compositions described above, the tungsten silicide thin film 19 can be etched at a high etching rate.
  • the micro-crystalline silicon thin film 18 is selectively etched to form the hydrogen feeding layer 8 having the same shape as the gate electrode 9 by a dry etching process using the same resist mask 20 as used in the above process, without being removed, and employing SF 6 (sulfur hexafluoride), Cl 2 (chlorine) and H 2 as etching gas.
  • SF 6 sulfur hexafluoride
  • Cl 2 chlorine
  • the etching gas to be used for dry etching on the micro-crystalline silicon thin film 18 has to have a composition which can provide a high selective etching ratio between the micro-crystalline silicon thin film 18 and silicon dioxide film making up the gate insulating film 7 formed directly below the micro-crystalline silicon thin film 18 .
  • a high selective etching ratio being as high as about 20 or more can be obtained and, therefore, the micro-crystalline silicon thin film 18 only can be etched selectively.
  • the etching gas described above has an excellent capability of removing a residue of tungsten silicide.
  • the dry etching methodemployed to form the gate electrode 9 and the hydrogen feeding layer 8 described above have an advantage in that, by switching each of the etching gases in the mid-course of the etching process, a same vacuum system can be used, serving to raise a throughput.
  • the process of photolithography is not needed. That is, the hydrogen feeding layer 8 can be formed without causing an increase in the process of photolithography.
  • an interlayer dielectric 11 made up of a silicon nitride film having its film thickness of 280 nm to 320 nm is deposited on entire surfaces being exposed including a surface of the gate electrode 9 by a P-CVD method using SiH 4 , NH 3 (ammonia), and H 2 as reactant gas.
  • P phosphorus
  • PH 3 as an impurity source
  • the gate electrode 9 as a mask
  • the interlayer insulating film 11 and the gate insulating film 7 are selectively etched using the resist mask layer by a dry etching method using CF 4 and H 2 as etching gas to form contact holes 12 A and 12 B which expose the source region 4 and the drain region 5 respectively.
  • the TFT 10 of the embodiment is obtained by depositing the passivation film 15 made up of a silicon nitride film having its film thickness of 250 nm to 280 nm on entire surfaces being exposed containing surfaces of the source electrode 13 and drain electrode 14 by a P-CVD method using SiH 4 , NH 3 , and H 2 as reactant gas.
  • the micro-crystalline silicon thin film 18 and the tungsten silicide thin film 19 are sequentially formed on the gate insulating film 7 and the tungsten silicide thin film 19 and micro-crystalline silicon thin film 18 are sequentially and selectively etched, by commonly using the resist mask layer 20 having a desired shape deposited on the tungsten silicide thin film 19 , to form the gate electrode 9 and the hydrogen feeding layer 8 and, therefore, the process of photolithography to form the hydrogen feeding layer 8 is not needed.
  • a lower layer polycrystalline silicon thin film 121 and the P-CVD process to form the lower layer polycrystalline silicon thin film 121 shown in the conventional processes in FIGS. 1A to 11 E are not required. Therefore, a decrease in yields caused by an increase in the processes can be avoided, which enables reduction in manufacturing costs.
  • the method of manufacturing the TFT of the first embodiment by performing the heat treatment on the insulating substrate 1 at 300° C. to 400° C. in the atmosphere containing hydrogen plasma, diffusion of hydrogen into the dangling bond can be carried out by using hydrogen not only fed from the hydrogen feeding layer 8 but also provided in the atmosphere containing hydrogen plasma and, therefore, an efficiency of hydrogenation can be improved.
  • the hydrogen feeding layer 8 to diffuse hydrogen into an interface between the polycrystalline silicon thin film 3 and the gate insulating film 7 is formed in a position between the gate insulating film 7 and the gate electrode 9 , a diffusing distance of hydrogen at a period of time during the hydrogenation can be shortened.
  • the micro-crystalline silicon thin film 18 and the tungsten silicide thin film 19 are sequentially formed on the gate insulating film 7 and the tungsten silicide thin film 19 and micro-crystalline silicon thin film 18 are sequentially and selectively etched, by commonly using the resist mask layer 20 having a desired shape deposited on the tungsten silicide thin film 19 , to form the gate electrode 9 and the hydrogen feeding layer 8 and, therefore, the process of photolithography to form the hydrogen feeding layer 8 is not needed, which can reduce manufacturing costs. Therefore, according to the TFT of the embodiment, without increasing the processes of photolithography, a hydrogen feeding layer can be formed in a position which enables diffusing distance of hydrogen to be shortened.
  • FIG. 6 is a process diagram showing a main process being employed in the method of manufacturing a TFT according to a second embodiment of the present invention.
  • the method for manufacturing the TFT of the second embodiment differs greatly from that in the first embodiment in that hydrogenation is achieved only by diffusion of hydrogen fed from a hydrogen feeding layer without using hydrogen provided in an atmosphere containing hydrogen plasma.
  • the hydrogenation is carried out by performing heat treatment on an insulating substrate 1 in the atmosphere containing hydrogen plasma using the P-CVD method in the process shown in FIG.
  • the hydrogenation is carried out by performing heat treatment on the insulating substrate 1 at about 400° C. by using a heating system being ordinarily used as shown in FIG. 6.
  • a heating system being ordinarily used as shown in FIG. 6.
  • the heat treatment by the heating system to release hydrogen from a hydrogen feeding layer 8 to have the hydrogen be diffused into a dangling bond existing at an interface between the polycrystalline silicon thin film 3 and the silicon dioxide film serving as a gate insulating film 7 , an orbit being in an unbonded state of the polycrystalline silicon is connected to an atom of hydrogen for termination.
  • it is preferable that the above heat treatment is performed within a temperature range of 300° C. to 400° C.
  • the heat treatment is performed at a temperature being lower than about 400° C.
  • the hydrogenation is achieved by diffusion of hydrogen fed only from the hydrogen feeding layer 8 without using hydrogen to be provided in an atmosphere containing hydrogen plasma, the hydrogenation can be carried out only by using the heat system being ordinarily used without using the P-CVD process, which enables the hydrogenation to be achieved in a simply way.
  • processes following the process shown in FIG. 5J may be repeated in almost the same way as employed in the first embodiment.
  • FIG. 7 is a process diagram showing a main process being employed in the method of manufacturing a TFT according to a third embodiment of the present invention.
  • the method for manufacturing the TFT of the third embodiment differs greatly from that of the first embodiment in that a process of formation of an interlayer dielectric (first insulating film) and a process of hydrogenation are performed at the same time.
  • a process of formation of an interlayer dielectric first insulating film
  • a process of hydrogenation are performed at the same time.
  • the hydrogenation is carried out by performing heat treatment in the process shown in FIG.
  • the formation of an interlayer dielectric 11 as used in the first embodiment shown in FIG. 4G and the hydrogenation by performing heat treatment on an insulating substrate 1 at about 400° C. are achieved at the same time as shown in FIG. 7.
  • the heat treatment to form the interlayer dielectric 11 and, at the same time, to release hydrogen from a hydrogen feeding layer 8 to have the hydrogen be diffused into a dangling bond existing at an interface between the polycrystalline silicon thin film 3 and the silicon dioxide film serving as a gate insulating film 7 an orbit being in an unbonded state of the polycrystalline silicon is connected to an atom of hydrogen for termination.
  • the above heat treatment is performed within a temperature range of 400° C. to 300° C.
  • the heat treatment is performed at a temperature being lower than about 400° C.
  • an efficiency of the hydrogenation can be further improved.
  • FIG. 8 is a process diagram showing a main process being employed in a method of manufacturing a TFT according to a fourth embodiment of the present invention.
  • the method for manufacturing a TFT of the fourth embodiment differs greatly from that employed in the first embodiment in that both a formation process of a passivation film (second insulating film) and a hydrogenation process are performed at the same time.
  • the hydrogenation is carried out by performing heat treatment in the process shown in FIG.
  • the formation of the passivation film 15 as used in the first embodiment shown in FIG. 5L and the hydrogenation by performing heat treatment on the insulating substrate 1 at about 400° C. are achieved at the same time as shown in FIG. 8.
  • the heat treatment to form the passivation film 15 and, at the same time, to release hydrogen from the hydrogen feeding layer 8 to have the hydrogen be diffused into a dangling bond existing at an interface between the polycrystalline silicon thin film 3 and the silicon dioxide film serving as the gate insulating film 7 an orbit being in an unbonded state of the polycrystalline silicon is connected to an atom of hydrogen for termination.
  • the above heat treatment is performed within a temperature range of 400° C. to 300° C.
  • the heat treatment is performed at a temperature being lower than about 400° C.
  • an efficiency of the hydrogenation can be further improved.
  • each of the underlying insulation film, polycrystalline silicon thin film, gate insulating film, hydrogen feeding layer, gate electrode, interlayer dielectric, source electrode, drain electrode, various insulating films such as the passivation film, film thickness of the conductive film, deposition method, or a like described in the above embodiments is one example of components or conditions that can be applied to the present invention and, therefore, each of them may be changed depending on a purpose, application, or a like.
  • the example is shown in which a silicon nitride film is used for the interlayer dielectric or the passivation film, however, instead of the silicon nitride film, a silicon dioxide film may be used. Insulating films other than described in the above embodiment such as a stacked film consisting of both a silicon nitride film and a silicon dioxide film may be employed.
  • an example in which aluminum is used for the source electrode and drain electrode is described in the above embodiment, however, instead of aluminum, other conductive materials such as an aluminum alloy containing aluminum as a main component, copper, a copper alloy containing copper as a main component, or a like may be employed.
  • the conductive type of the source region and drain region to be formed on the polycrystalline silicon thin film may be not only of an N-type but also of a P-type.

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JP5344205B2 (ja) 2006-03-22 2013-11-20 Ｎｌｔテクノロジー株式会社 積層配線、該積層配線を用いた半導体装置及びその製造方法
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SG138446A1 (en) 2008-01-28
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