US20020096694A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20020096694A1
US20020096694A1 US09/310,580 US31058099A US2002096694A1 US 20020096694 A1 US20020096694 A1 US 20020096694A1 US 31058099 A US31058099 A US 31058099A US 2002096694 A1 US2002096694 A1 US 2002096694A1
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Prior art keywords
imaginary line
edge
disposed
pads
semiconductor device
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US09/310,580
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Inventor
Kouichirou Noda
Shigenobu Kato
Goro Kitsukawa
Michihiro Mishima
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Individual
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Priority to US09/966,085 priority Critical patent/US20020008255A1/en
Priority to US09/966,084 priority patent/US20020008254A1/en
Publication of US20020096694A1 publication Critical patent/US20020096694A1/en
Priority to US10/330,054 priority patent/US20030089926A1/en
Priority to US11/196,267 priority patent/US7400034B2/en
Priority to US12/146,654 priority patent/US7638871B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Definitions

  • the present invention relates to a technology for laying out semiconductor devices and more specifically to a technology effectively applicable to the disposition of pads for efficiently laying out a large capacity memory such as a DRAM and a synchronous DRAM (SDRAM).
  • a DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • a step-down system or a voltage regulator is often adopted in the late high integrated memories, so that a variety of power source lines are required within a chip. They include VDD, VSS, VDDQ and VSSQ as the external power source lines and VPERI (for a peripheral circuit), VDL (for a memory array), VPP (for a boost word driver) and VBB (for biasing an array substrate) as the internal power source lines. Still more, the power source lines may be divided into those for the memory arrays (VDDA, VSSA), for the general peripheral circuits (VDD, VSS) and for the input circuits (VDDI, VSSI) as measures to counter noises. Thus, it has become difficult to dispose the pads adequately due to the increase of the pads owing to the multiplication of bits and the variety of power source lines have come to be required due to the high integration in the memories such as the DRAM and SDRAM.
  • Japanese Patent Laid-Open No. 116865/1991 has disclosed a semiconductor memory device in which direct peripheral circuits are disposed in a region between two memory cell arrays along the respective memory cell arrays, in-direct peripheral circuits are disposed in a region between the direct peripheral circuits along one direct peripheral circuit, external terminals are disposed in the region between the direct peripheral circuits along the other direct peripheral circuit and a substrate voltage generating circuit is disposed in a region between the indirect peripheral circuit and the external terminal.
  • U.S. Pat. No. 5,579,256 (corresponding Japanese Patent Laid-Open No. 134568/1998) has disclosed a semiconductor device in which bonding pads, a voltage converter, a substrate voltage generating circuit and others are disposed at the center part of the chip.
  • U.S. Pat. No. 5,473,198 (corresponding Japanese Patent Laid-Open No. 350052/1994) has disclosed a semiconductor device in which axially symmetrical data input/output pads are disposed in two rows in parallel at the center part of the semiconductor chip.
  • U.S. Pat. 5,640,362 (corresponding Japanese Patent Laid-Open No. 128973/1997) has disclosed a synchronous semiconductor memory device having a plurality of data input/output pad groups 20 positioned at the right and left sides based on the center of a semiconductor chip 100 , disposed in a row horizontally between upper and lower memory bank arrays 0 through 7 and having the same number with the memory array banks 0 through 7 to input/output information to/from the memory array banks 0 through 7 .
  • U.S. Pat. No. 5,619,472 (corresponding Japanese Patent Laid-Open No. 139287/1996) has disclosed a center pad disposed type semiconductor memory device in which an IO pad array, i.e., a first pad array, is disposed between a core block 1 and a core block 2 and an address pad array, i.e., a second pad array, is disposed between a core block 3 and a core block 4 .
  • U.S. Pat. No. 5,627,792 (corresponding Japanese Patent Laid-Open No. 125143/1996) has disclosed a semiconductor memory device in which respective pins (power souce pins, ground pins, data input/output pins, control system signal pins, address system signal pins) of a lead frame are connected to bonding pad groups disposed along a center line in the center part of a semiconductor substrate by bonding wires 55 .
  • FIG. 8 shows the disposition of the pins of a 64 M SDRAM.
  • data signal pins DQ*
  • address and clock signal system pins A*, CLK, CKE, /RAS, /CAS etc.
  • A*, CLK, CKE, /RAS, /CAS etc. address and clock signal system pins
  • FIG. 9 shows the disposition of the conventional LOC assembling pads.
  • the bonding pads PS and PD are disposed almost at the center of the indirect peripheral circuit region, electrostatic protecting elements and input/output circuits are disposed in the vicinity of the bonding pads PS and PD and internal circuits such as a control circuit and a pre-decoder are disposed between the regions at the both upper and lower sides of the bonding pads PS and PD and memory array regions UL, UR, DL and DR.
  • the internal circuit groups are divided vertically by the bonding pads PS and PD in this disposition, it becomes difficult to exchange those large number of signals. Still more, there might be a problem when the circuit blocks are divided into the upper and lower parts that a power source line region is wasted because two sets of power source bus lines are required for them.
  • bonding pad groups are put not at the center but aside to the upper or lower side between memory array regions firstly in disposing the pads in a large capacity memory such as a DRAM and an SDRAM having the large number of bonding pads. Secondly, the disposition of the bonding pads is staggered on the right and left and the right bonding pads on the data signal side are put back to the center more or less.
  • indirect peripheral circuits are disposed collectively on the other side in the semiconductor device described above according to the first feature, it allows a number of signals exchanged between the upper and lower sides by using the gap between the bonding pads to be reduced. It also requires only one set of power source buses necessary for the indirect peripheral circuits.
  • the second feature allows a large number of signal channels to be assured on the address and clock signal side.
  • the data signal side requires not so many signal channels as compared to the address and clock signal side, large output transistors may be suitably placed adjoining the bonding pad thereabove and therebelow. While special power sources such as power sources dedicated for the output transistors are necessary on the data signal side additionally, they may be also suitably placed.
  • the indirect peripheral circuits may be laid out efficiently on the chip as a whole and the improvement of the speed may be achieved by the reduction of the chip area and the shortening of the signal passages.
  • a semiconductor device of the invention has a first edge ( 10 - 1 ) extending in a first direction; a second edge ( 10 - 2 ) facing to the first edge; a third edge ( 10 - 3 ) extending in a second direction perpendicular to the first edge; and a fourth edge ( 10 - 4 ) facing to the third edge; and further comprises an output circuit ( 22 , 23 ); a first memory array (UR) disposed between the first edge and a first imaginary line ( 10 - 5 ); and a second memory array (DR) disposed between the second edge and the first imaginary line.
  • UR first memory array
  • DR second memory array
  • the plurality of pads (PD) are disposed on a second imaginary line ( 10 - 6 );
  • the first imaginary line is an imaginary line connecting a middle point ( 10 - 8 ) of the third edge and a middle point ( 10 - 9 ) of the fourth edge;
  • the second imaginary line is an imaginary line which is parallel with the first imaginary line and which is imaginarily disposed between the first imaginary line and the second edge;
  • the plurality of pads contain a first pad;
  • the output circuit is connected with the first pad;
  • the output circuit contains a first transistor ( 22 ) of a first conductive type and a second transistor ( 23 ) of a second conductive type;
  • the first conductive type is different from the second conductive type;
  • the first transistor is disposed between the first imaginary line and the first memory array; and the second transistor is disposed between the second imaginary line and the second memory array.
  • the above configuration allows a layout area for disposing the peripheral circuits to be largely prepared and an area occupied by the output circuits to be reduced.
  • the first and second transistors of the output circuit are PMOS and NMOS transistors
  • at least a part of a separating region for separating the PMOS and NMOS may be created by utilizing the lower part of the first pad connected to the output circuit. It then allows the area occupied by the output circuits to be reduced.
  • Another semiconductor device of the invention has a first edge extending in a first direction; a second edge facing to the first edge; a third edge extending in a second direction perpendicular to the first edge; and a fourth edge facing to the third edge; and further comprises a plurality of first pads (PD) to which data signals are supplied; a plurality of second pads (PS) to which address signals are supplied; a first memory array disposed between the first edge and a first imaginary line; and a second memory array disposed between the second edge and the first imaginary line.
  • PD first pads
  • PS second pads
  • the plurality of first pads are disposed on a second imaginary line; the plurality of second pads are disposed on a third imaginary line ( 10 - 7 ); the first imaginary line is an imaginary line connecting a middle point of the third edge and a middle point of the fourth edge; the second imaginary line is an imaginary line which is parallel with the first imaginary line and which is imaginarily disposed between the first imaginary line and the second edge; and the third imaginary line is an imaginary line which is parallel with the first imaginary line and imaginarily disposed between the second imaginary line and the second edge.
  • the above configuration allows the space for disposing the peripheral circuits such as an address buffer, an address decoder, data input/output circuits for inputting/outputting data signals and various voltage generating circuits to be prepared collectively and an area occupied by the circuits for outputting the data signals to be reduced. It also allows a large number of address signal lines to be disposed collectively.
  • a still other semiconductor device of the invention has a first edge extending in a first direction; a second edge facing to the first edge; a third edge extending in a second direction perpendicular to the first edge; and a fourth edge facing to the third edge; and further comprises a plurality of first pads; a plurality of second pads; a first memory array disposed between the first edge and a first imaginary line; and a second memory array disposed between the second edge and the first imaginary line.
  • the plurality of first pads are disposed on a second imaginary line; the plurality of second pads are disposed on a third imaginary line; the first imaginary line is an imaginary line connecting a middle point of the third edge and a middle point of the fourth edge; the second imaginary line is an imaginary line which is parallel with the first imaginary line and which is imaginarily disposed between the first imaginary line and the second edge; the third imaginary line is an imaginary line which is parallel with the first imaginary line and imaginarily disposed between the second imaginary line and the second edge; no pad exists between the plurality of first pads and the second edge; and no pad exists between the plurality of second pads and the first edge.
  • the above configuration allows the space for disposing the peripheral circuits such as an address buffer and an address decoder which receive address signals, data input/output circuits for inputting/outputting data signals and various voltage generating circuits to be prepared collectively and an area occupied by the circuits for outputting the data signals to be reduced. It also allows a large number of address signal lines to be disposed collectively. Further, because no pad exists between the plurality of first pads and the second edge and between the plurality of second pads and the first edge, many circuits may be disposed in this region and wires to be drawn around may be reduced.
  • FIGS. 1 ( a ) and 1 ( b ) are schematic layouts and a partially enlarged view showing a semiconductor memory device according to one embodiment of the invention
  • FIG. 2 is a schematic layout showing the disposition of bonding pads in the semiconductor memory device of the embodiment
  • FIG. 3 is a schematic layout showing the disposition of circuit blocks at the center part of a chip in the semiconductor memory device of the embodiment
  • FIG. 4 is a schematic layout showing the disposition of the bonding pads and power lines at the center part of the chip in the semiconductor memory device of the embodiment
  • FIG. 5 is a circuit diagram showing the surrounding of the bonding pad for address and clock signals in the semiconductor memory device of the embodiment
  • FIG. 6 is a circuit diagram showing the surrounding of the bonding pad for data signals in the semiconductor memory device of the embodiment
  • FIG. 7 is a schematic plan view showing an LOC bonding method in the semiconductor memory device of the embodiment.
  • FIG. 8 is a diagram for explaining the disposition of input/output pins in a semiconductor memory device which is a precondition of the invention.
  • FIG. 9 is a schematic layout showing the disposition of bonding pads in the semiconductor memory device which is the precondition of the invention.
  • FIGS. 1 ( a ) and 1 ( b ) are schematic layouts and a partially enlarged view showing a semiconductor memory device according to one embodiment of the invention
  • FIG. 2 is a schematic layout showing the disposition of bonding pads in the semiconductor memory device of the embodiment
  • FIG. 3 is a schematic layout showing the disposition of circuit blocks at the center part of a chip
  • FIG. 4 is a schematic layout showing the disposition of the bonding pads and power source lines at the center part of the chip
  • FIG. 5 is a circuit diagram showing the surrounding of the bonding pad of address and clock signals
  • FIG. 6 is a circuit diagram showing the surrounding of the bonding pad of data signals
  • FIG. 7 is a schematic plan view showing an LOC bonding method.
  • the semiconductor memory device of the present embodiment is formed as a large capacity memory such as a DRAM and an SDRAM.
  • Formed on one semiconductor chip 10 by the known semiconductor manufacturing technique are main row decoder regions 11 , main word driver regions 12 , column decoder regions 13 , peripheral circuit and bonding pad regions 14 , memory cell arrays 15 , sense amplifier regions 16 , sub-word driver regions 17 , intersection regions 18 and others.
  • the horizontal direction is the line direction (word line direction) and the vertical direction is the column direction (bit line direction).
  • memory array regions composed of the memory cell arrays 15 and others are disposed by being divided into four banks 0 through 3 on the right and left side in the line direction and on the upper and lower sides in the column direction of the memory chip 10 as shown in FIG. 1 for example.
  • the memory array regions disposed on the right and left sides are disposed in a pair while interposing the main row decoder region 11 disposed at the center via the main word driver regions 12 .
  • the column decoder regions 13 corresponding to the memory array regions disposed at the upper and lower sides of the memory chip 10 are disposed at the center sides of the respective memory array regions.
  • Row address buffers, column address buffers, pre-decoders, a timing generating circuit, data input/output circuits and others are disposed and bonding pads for connecting to the outside are provided further at the center thereof as the peripheral circuit and bonding pad regions 14 .
  • the sense amplifier regions 16 are disposed in the column direction of the memory cell arrays 15 while adjoining the memory cell array, the sub-word driver regions 17 are disposed in the line direction thereof while adjoining them, an FX driver (for driving the sub-word driver) and a control circuit of the sense amplifier group (such as a switching MOS transistor) are disposed in the intersection region 18 of the sense amplifier region 16 and the sub-word driver region 17 .
  • the word line is set in the line direction and the bit line is set in the column direction with respect to this memory cell array 15 . It is apparent that the invention is applicable also when this disposition is reversed.
  • the disposition of the bonding pads provided in the peripheral circuit and bonding pad regions 14 at the center of the memory array regions disposed at the upper and lower sides thereof is inventive. It will be explained below in order with reference to FIGS. 2 through 7.
  • FIG. 2 is a diagram showing the disposition of the bonding pads. Differing from one shown in FIG. 9, it has two characteristic points. Firstly, the bonding pads PS and PD are disposed not at the center but aside between the memory array regions UL and UR disposed on the upper side of the four banks of the banks 0 through 3 and the memory array regions DL and DR disposed on the lower side. They are put to the lower side in FIG. 2. Secondly, the disposition of the bonding pads PS and PD are staggered on the right and left. That is, the right-half bonding pads PD are shifted up from the bonding pads PS. The relative shift is around 30 ⁇ m.
  • the indirect peripheral circuits are disposed collectively on the upper side by shifting the bonding pads PS and PD to the lower side as a whole as the first characteristic point, a number of signals exchanged on the upper and lower sides of the bonding pads PS and PD is reduced remarkably as compared to the case of FIG. 9. Further, it requires to place only one set of power source buses which are necessary for the indirect peripheral circuits on the upper side. Although power sources for the column decoder and the main amplifier are necessary also on the lower side as a matter of course, they may be omitted because a large number of power sources are unnecessary on the lower side.
  • a large number of signal channels accompanying to X and Y address signal system and the control circuit may be assured in the indirect peripheral circuits on the left side by putting back the right bonding pads PD to the upper side more or less. While the input/output circuits accompanying to data occupy the most on the right side and require less signal channels as compared to the left side, it is preferable to shift the bonding pads PD to the upper side to place large output transistors while adjoining above and below the bonding pads PD. Further, while special power sources such as VDDQ and VSSQ dedicated for the output transistors are necessary additionally on the right side, they may be placed preferably.
  • the bonding pads PS of the address and clock signal system on the left side are disposed while leaving a space TL of around 230 ⁇ m from the center and the bonding pads PD of the data signal system is disposed while leaving a space TR of around 200 ⁇ m from the center.
  • No sense amplifier is included in the region of T, even though the main amplifier and the column decoder are included.
  • the shift between the bonding pads PS and the bonding pads PD is around 30 ⁇ m.
  • the bonding pads PS and bonding pads PD include voltage pads such as VDD and VSS.
  • FIG. 3 is an enlarged view of the center part of the chip. A well separation may be omitted and the positive side power source line may be shared by placing two indirect peripheral circuit groups so that PMOS transistors adjoin back to back.
  • a metallic three-layer wiring structure a metallic first layer is used for connecting elements within the cell and the metallic second layer and the metallic third layer are used for coupling signals and power sources in the vertical (short edge) direction and the horizontal (long edge) direction, respectively in the long edge region between the upper and lower memory array regions UL, UR, DL and DR. It is because the metallic three-layer is thick and has the lowest resistance. Because the row decoder and main word driver regions between the memory array regions UL and UR and the memory array regions DL and DR is long in the vertical direction, the metallic three-layer wire is applied in the vertical direction.
  • FIG. 4 shows the power source lines at the center part of the chip. Names of a variety of power source lines are shown in the figure.
  • VDDQ and VSSQ are the power sources dedicated for the output transistors
  • VSSI and VDDI are those for the input circuits
  • VDDA and VSSA are those for driving the sense amplifiers
  • VPERI is a step-down power source for the peripheral circuits
  • VDL is a power source for memory cell storage voltage
  • VPP is a power source for boosting the word line.
  • the metallic two-layer and the metallic three-layer lines are used in the vertical and horizontal directions, respectively.
  • FIG. 5 shows the bonding pad PS for input signals.
  • An electrostatic protecting element 21 is disposed on the bonding pad PS for the address and clock signals and the bonding pad PS is connected to an internal circuit via the electrostatic protecting element 21 .
  • the electrostatic protecting element 21 occupies a large area on one side of the bonding pad PS. A broken line in the figure implicates its approximate size.
  • FIG. 6 shows the bonding pad PD for data signals.
  • An output PMOS transistor 22 and an output NMOS transistor 23 are disposed above and below the bonding pad PD. Gates of the output PMOS transistor 22 and the output NMOS transistor 23 are connected to the internal circuit. Broken lines in the figure implicate their approximate size. Differing from the bonding pad PS for the input signals shown in FIG. 5, the bonding pad PD requires large areas thereabove and therebelow.
  • the bonding pads are to be disposed efficiently by noticing on the differences of the sizes and the wiring characteristics of the elements around the bonding pad PS in FIG. 5 and the bonding pad PD in FIG. 6, it is favorable to stagger the position of the bonding pads PS and PD up and down on the right and left sides thereof as shown in FIGS. 2, 3 and 4 .
  • the bonding pads PS and PD on the right and left sides are put on the lower side and the right bonding pads PD are disposed so as to be put back to the center more or less.
  • FIG. 7 is a plan view showing the state in which bonding has been implemented on an LOC (lead on chip) package.
  • LOC lead on chip
  • a lead frame 31 is disposed above the memory chip 10 in the figure and the bonding pads PS and PD of the memory chip 10 are connected with the edge of the lead frame 31 by means of wire bonding by using wires 32 such as gold lines.
  • the bonding may be implemented on the LOC package in the same manner with the conventional method because the bonding pads PS and PD deviate less from the whole memory chip 10 even if they are shifted.
  • FIG. 7 shows the package corresponding to one shown in FIG. 8 in which a number of input/output pins is 54 .
  • the indirect peripheral circuits are disposed collectively on the upper side by shifting the bonding pads PS and PD to the lower side as a whole, so that a number of signals exchanged between the upper and lower sides by using the gaps between the bonding pads PS and PD may be reduced. Further, it requires only one set of power source buses necessary for the indirect peripheral circuits. Still more, a large number of signal channels may be assured on the address and clock signal side by putting back the right bonding pads PD to the upper side more or less.
  • the large output PMOS transistor 22 and the output NMOS transistor 23 may be suitably placed above and below the bonding pad PD while adjoining it.
  • the special power sources such as the VDDQ and VSSQ dedicated for the transistors 22 and 23 may be also suitably placed additionally. As a result, the indirect peripheral circuits may be efficiently laid out on the chip as a whole.
  • the invention is not limited to such case and the bonding pads may be disposed by shifting to the upper side. It is preferable to dispose the data signal side bonding pads so as to be put back to the center more or less also in this case.
  • the indirect peripheral circuits may be disposed collectively on the other side by disposing the bonding pad groups not at the center but aside to the upper or lower side between the memory array regions, a number of signals exchanged between the upper and lower sides by using the gaps of the bonding pads may be reduced;
  • a large number of signal channels may be assured on the address and clock signal side by staggering the disposition of the bonding pads on the right and left sides and by disposing the data signal side bonding pads so as to be put back to the center more or less;
  • the large output transistors may be placed above and below the bonding pad while adjoining it on the data signal side by disposing the data signal side bonding pads so as to be put back to the center by the effect (3) described above;
  • the special power sources such as the power sources dedicated for the output transistors may be disposed additionally by disposing the data signal side bonding pads so as to be put back to the center by the effect (3) described above;

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US10/330,054 US20030089926A1 (en) 1998-05-12 2002-12-30 Semiconductor device
US11/196,267 US7400034B2 (en) 1998-05-12 2005-08-04 Semiconductor device
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US09/966,085 Abandoned US20020008255A1 (en) 1998-05-12 2001-10-01 Semiconductor device
US10/330,054 Abandoned US20030089926A1 (en) 1998-05-12 2002-12-30 Semiconductor device
US11/196,267 Expired - Fee Related US7400034B2 (en) 1998-05-12 2005-08-04 Semiconductor device
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US10/330,054 Abandoned US20030089926A1 (en) 1998-05-12 2002-12-30 Semiconductor device
US11/196,267 Expired - Fee Related US7400034B2 (en) 1998-05-12 2005-08-04 Semiconductor device
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US20030089926A1 (en) 2003-05-15

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