TWI582973B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI582973B TWI582973B TW102118236A TW102118236A TWI582973B TW I582973 B TWI582973 B TW I582973B TW 102118236 A TW102118236 A TW 102118236A TW 102118236 A TW102118236 A TW 102118236A TW I582973 B TWI582973 B TW I582973B
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- 239000004065 semiconductor Substances 0.000 title claims description 54
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000009413 insulation Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 300
- 239000000463 material Substances 0.000 description 78
- 238000000034 method Methods 0.000 description 22
- 238000005530 etching Methods 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 15
- 239000012535 impurity Substances 0.000 description 14
- 238000003860 storage Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000012782 phase change material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Description
本申請要求2013年1月7日提交至韓國專利局的申請號為10-2013-0001656的韓國專利申請的優先權,其全部公開內容通過引用合併於此。
各種實施例總體而言涉及一種半導體裝置及其製造方法,更具體而言,涉及一種三維半導體裝置及其製造方法。
非揮發性記憶體裝置即使在沒有供電時也可以保留其中儲存的資料。記憶體單元以單層製造在矽基板之上的二維記憶體裝置已經達到物理極限,並且不能再具有提高的集成度。因而,提出了記憶體單元沿垂直方向層疊在矽基板之上的三維(3D)非揮發性記憶體裝置。
3D非揮發性記憶體裝置包括相互交替層疊的層間絕緣層和字線以及穿通前述層間絕緣層和字線的溝道層。沿著溝道層層疊了記憶體單元。為了選擇性地驅動特定的記憶體單元,要在每個字線上形成焊盤部
分,且接觸插塞要與焊盤部分耦接。
在相互層疊的字線上形成焊盤部分以及形成接觸插塞使得接觸插塞與焊盤部分耦接是困難的。另外,可能會出現其中接觸插塞穿通焊盤部分的穿孔現象,或者由於沒有沿著接觸孔的底表面暴露出焊盤部分而導致接觸插塞和焊盤部分沒有彼此耦接。
本發明的各個實施例涉及一種能夠容易地形成焊盤部分的半導體裝置及其製造方法。
根據本發明實施例的半導體裝置包括:基板,其中限定了單元區和接觸區;焊盤結構,包括在基板的接觸區中彼此交替地形成的多個第一導電層和多個第一絕緣層;其中,前述焊盤結構的端部被圖案化為臺階狀;前述第一導電層的在前述焊盤結構的端部暴露的部分被定義為多個焊盤部分,前述多個焊盤部分具有比前述多個第一導電層的未暴露的部分大的厚度。
根據本發明實施例的半導體裝置包括:基板;多個層疊結構,包括相互交替地形成在前述基板上的多個導電層和多個絕緣層,其中前述多個層疊結構的每個端部被圖案化成臺階狀;以及將前述多個層疊結構相互分隔開的至少一個縫隙;其中前述多個導電層的在多個層疊結構的每個端部暴露的部分被定義為多個焊盤部分,而前述多個焊盤部分具有比前述多個導電層的未暴露部分更大的厚度。
ST‧‧‧層疊結構
SL1‧‧‧第一縫隙
CELL‧‧‧單元區
CONTACT‧‧‧接觸區
PS‧‧‧焊盤結構
CS‧‧‧單元結構
PAD‧‧‧焊盤部分
15‧‧‧犠牲層
11‧‧‧第一導電層
12‧‧‧第一絕緣層
13‧‧‧第二導電層
14‧‧‧第二絕緣層
21‧‧‧第一材料層
22‧‧‧第二材料層
CH‧‧‧溝道層
23‧‧‧雜質層
RC‧‧‧凹陷區
24‧‧‧層間絕緣層
SL2‧‧‧第二縫隙
26‧‧‧接觸插塞
25‧‧‧導電層
27‧‧‧阻擋層
28‧‧‧阻擋層
31‧‧‧第一材料層
32‧‧‧第二材料層
33‧‧‧緩衝層
34‧‧‧層間絕緣層
35‧‧‧導電層
36‧‧‧接觸插塞
SUB‧‧‧基板
PG‧‧‧管道閘極
WL‧‧‧字線
DSL‧‧‧汲極選擇線
SSL‧‧‧源極選擇線
P_CH‧‧‧管道溝道層
S_CH‧‧‧源極側溝道層
D_CH‧‧‧汲極側溝道層
BL‧‧‧位元線
M‧‧‧存儲線
S‧‧‧源極區
LSL‧‧‧下選擇線
USL‧‧‧上選擇線
S1‧‧‧第一源極層
S2‧‧‧第二源極層
S3‧‧‧第三源極層
IIL‧‧‧層間絕緣層
100‧‧‧存儲系統
110‧‧‧記憶體控制器
120‧‧‧非揮發性記憶體裝置
111‧‧‧SRAM
112‧‧‧CPU
113‧‧‧主機介面
114‧‧‧ECC
115‧‧‧記憶體介面
200‧‧‧計算系統
220‧‧‧CPU
230‧‧‧RAM
240‧‧‧用戶介面
260‧‧‧系統匯流排
250‧‧‧數據機
210‧‧‧存儲系統
211‧‧‧記憶體控制器
212‧‧‧非揮發性記憶體裝置
圖1A是示出根據本發明的一個實施例的半導體裝置的結構的立體圖;圖1B是示出根據本發明的另一個實施例的半導體裝置的結構的立體圖;圖2A至7B是示出根據本發明的一個實施例的製造半導體裝置的方法的視圖;圖8A至8B是示出根據本發明的一個實施例的製造半導體裝置的方法的另外製程的視圖;圖9A至11B是示出根據本發明另一個實施例的製造半導體裝置的方法的另外製程的視圖;圖12A至12D是示出根據本發明的一個實施例的半導體裝置的單元結構的立體圖;圖13是示出根據本發明的一個實施例的存儲系統的配置的框圖;以及圖14是示出根據本發明的一個實施例的計算系統的配置的框圖。
此後,將參考附圖描述本發明的各個實施例。在附圖中,為了便於說明,與部件的實際物理厚度和間隔相比,部件的厚度和距離可能會誇大。在以下描述中,會省略對已知的相關功能和構成部件的詳細描述,以避免不必要的資訊來模糊本發明的主題。在說明書和附圖中,相同的元件符號表示相同的元件。
如圖1A所示,半導體裝置可以包括基板(未示出)、層疊結構ST和至少一個第一縫隙SL1。在基板
中可以限定單元區CELL和接觸區CONTACT。層疊結構ST可以包括相互交替地形成在基板上的導電層11和13與絕緣層12和14。第一縫隙SL1可以將相鄰的層疊結構ST彼此分隔開。
層疊結構ST的端部可以被圖案化為臺階狀。被圖案化為臺階狀的層疊結構ST的每個臺階可以包括至少一個導電層11或13以及至少一個絕緣層12或14。如圖1A所示,絕緣層12或14可以位於每個臺階的頂表面。可替選地,如圖1B所示,導電層11或13可以位於每個臺階的頂表面。
層疊結構ST可以包括位於接觸區CONTACT中的焊盤結構PS和位於單元區CELL中的單元結構CS。焊盤結構PS和單元結構CS可以相互耦接。例如,焊盤結構PS可以位於單元結構CS的任意一側或兩側。
焊盤結構PS可以包括交替形成在基板的接觸區CONTACT中的第一導電層11和第一絕緣層12。焊盤結構PS的端部可以被圖案化成臺階狀。第一導電層11的沿著焊盤結構PS的臺階化端部暴露出的部分可以被定義為焊盤部分PAD。焊盤部分PAD可以具有比第一導電層11的未暴露部分更大的厚度。
另外,焊盤結構PS還可以包括犧牲層15。犧牲層15可以與第一導電層11耦接。例如,第一導電層11可以沿著經由第一縫隙SL1暴露出的焊盤結構PS的z軸而層疊在側壁上(即,在側部區域)。犧牲層15可以沿著z軸而層疊在焊盤結構PS的中心區域中。焊盤部
分PAD可以具有比犧牲層15更大的厚度。
單元結構CS可以包括相互交替形成在基板的單元區CELL中的第二導電層13和第二絕緣層14。形成在相同水平面的第一導電層11和第二導電層13可以相互耦接,形成在相同水平面的第一絕緣層12和第二絕緣層14可以相互耦接。例如,形成在相同水平面的第一導電層11和第二導電層13可以形成為單層,形成在相同水平面的第一絕緣層12和第二絕緣層14可以形成為單層。
半導體裝置還可以包括穿通單元結構CS的溝道層CH以及穿通單元結構CS的至少一個第二縫隙SL2。
根據半導體裝置的上述結構,焊盤部分PAD可以具有比第一導電層11的其他未暴露部分更大的厚度。另外,焊盤部分PAD可以具有比第二導電層13和犧牲層15更大的厚度。因此,可以在不增大層疊結構ST的高度的情況下選擇性地增加焊盤部分PAD的厚度。
圖2A至7A是立體圖,且圖2B至7B是沿著圖2A至7A的線I-I'截取的截面圖。出於說明的目的,繪製了層疊結構ST的一部分,具體是焊盤結構PS。
如圖2A和2B所示,可以相互交替地形成多個第一材料層21和多個第二材料層22。可以提供第一材料層21來形成導電層,且可以提供第二材料層22來形成絕緣層。
第一材料層21可以由相對於第二材料層22
具有高刻蝕選擇性的材料形成。例如,第一材料層21可以包括諸如多晶矽層的導電層,第二材料層22可以包括諸如氧化物層的絕緣層。在另一個例子中,第一材料層21可以包括諸如氮化物層的犧牲層,第二材料層22可以包括諸如氧化物層的絕緣層。
在本發明的一個實施例中,將會以第一材料層21包括犧牲層而第二材料層22包括絕緣層為例提供描述。
隨後,可以將包括第一材料層21和第二材料層22的中間所得結構的端部圖案化成臺階狀。中間所得結構的被圖案化成臺階狀的每個臺階可以包括單個第一材料層21和形成在第一材料層21上的單個第二材料層22。
儘管圖2A和2B沒有示出,但是可以在臺階狀地圖案化第一材料層21和第二材料層22之前或之後來執行形成記憶體單元的製程。例如,可以穿通第一材料層21和第二材料層22來形成孔,並且可以在孔中形成存儲層和溝道層CH。存儲層可以包括電荷阻擋層、資料儲存層或隧道絕緣層中的至少一個。資料儲存層可以包括:可以儲存電荷的諸如多晶矽層的浮閘極、可以俘獲電荷諸如氮化物層的電荷陷阱層、以及奈米點。在形成存儲層之前,可以在孔中形成犧牲層。另外,溝道層CH可以具有各種形狀,諸如直線形、U形和W形。溝道層CH可以形成為具有開放的中心部分的管形、具有被完全填充的中心部分的柱形或其組合。在另一個例子
中,可以在孔中順序形成閘極絕緣層、溝道層CH和相變材料層。相變材料層可以形成為具有開放的中心區域的管形、具有被完全填充的中心部分的柱形或其組合。
如圖3A和3B所示,可以將雜質注入到被圖案化成臺階狀的中間所得結構中,使得可以在第二材料層22中形成雜質區23。例如,可以通過使用離子注入製程來注入諸如N型雜質、P型雜質、氬(Ar)或氦(He)的雜質。另外,可以控制製程條件,使得離子注入製程的注射離子射程(Rp)位於第二材料層22中。
在雜質離子注入製程期間,可以使用遮罩圖案。例如,可以在第一材料層21和第二材料層22之上形成遮罩圖案,使得前述遮罩圖案可以暴露出接觸區CONTACT的側部區域並且覆蓋單元區和接觸區CONTACT的中心區域。隨後,可以使用遮罩圖案作為阻擋層來執行離子注入製程。
如圖4A和4B所示,可以去除第一材料層21來形成凹陷區RC。例如,在層間絕緣層24形成在第一材料層21和第二材料層22上之後,可以穿通層間絕緣層24、第一材料層21和第二材料層22來形成至少一個第一縫隙SL1。結果,層疊結構ST可以由第一縫隙SL1而彼此分隔開。隨後,可以通過從被第一縫隙SL1暴露出的層疊結構ST的側壁進行刻蝕,來去除經由第一縫隙SL1暴露出的第一材料層21。因此,可以沿著y軸從每個層疊結構ST的側部區域去除第一材料層21,而可以保留每個層疊結構ST的中心區域中的第一材料層
21。
當形成第一縫隙SL1時,也可以形成位於單元區CELL中的第二縫隙SL2(見圖1A和1B)。如果第二縫隙SL2形成在單元區CELL中,則可以去除經由第一縫隙SL1和第二縫隙SL2暴露出的第一材料層21。因而,可以從單元區CELL完全去除第一材料層21。
如圖5A和5B所示,可以增加凹陷區RC的端部的厚度。例如,通過使用濕法刻蝕製程,可以將被凹陷區RC暴露出的第二材料層22刻蝕到預定厚度。由於雜質區23的刻蝕速率比沒有注入雜質的區域的刻蝕速率高,因此雜質區23的刻蝕量可以大於未注入區域的刻蝕量。因此,可以延伸凹陷區RC的端部。
如上前述,在孔中形成犧牲層的例子中,在為了延伸凹陷區RC的端部而執行的刻蝕製程期間,還可以刻蝕經由凹陷區RC暴露出的犧牲層。在這個例子中,可以沿著形成在單元區CELL中的凹陷區RC來暴露出存儲層。
如圖6A和圖6B所示,可以在凹陷區RC中形成存儲層(隨後是導電層25)。每個存儲層可以包括電荷阻擋層、資料儲存層和隧道絕緣層中的至少一個。
結果,可以形成導電層25,其中在層疊結構ST的端部暴露出的焊盤部分PAD可以具有比導電層25的未暴露部分更大的厚度。
如圖7A和7B所示,可以穿通層間絕緣層24來形成接觸孔,使得可以經由接觸孔來暴露出焊盤部
分PAD,且可以在接觸孔中形成導電層。結果,可以形成接觸插塞26,使得每個接觸插塞26可以與每個焊盤部分PAD耦接。
接觸孔可以根據焊盤部分PAD的高度而形成在不同的深度。通常,由於上焊盤部分PAD的過刻蝕可能會出現穿孔(punch)現象,或者可能會出現沒有沿著接觸孔的底表面暴露出下焊盤部分PAD的未打開現象。然而,根據本發明的一個實施例,由於可以選擇性地提高焊盤部分PAD的厚度來確保刻蝕餘量(etch margin),所以可以防止上述現象。
儘管已經就接觸插塞26排列成線的例子進行了描述,但是接觸插塞26也可以排列成其他方式,例如排列成交錯圖案。
根據第一材料層21和第二材料層22的類型,可以對上述製造製程進行各種變化。
例如,第一材料層21可以包括導電層,且第二材料層22可以包括層間絕緣層。根據這個例子,在形成第一縫隙SL1之後,可以通過使用濕法刻蝕製程來刻蝕第二材料層22。由於採用比沒有注入雜質的區域更快的速率來刻蝕雜質區23,因此可以刻蝕形成在焊盤部分PAD的上部的第二材料層22以形成凹陷區域。隨後,可以在凹陷區域和第一縫隙SL1中形成金屬層,並且第一材料層21與金屬層可以相互反應以由此將第一材料層21矽化。由於第一材料層21的焊盤部分PAD可以經由凹陷區域來與金屬層的更多部分接觸和反應,因此可以
形成具有比其他區域更大厚度的矽化物層。因此,可以略去通過去除第一材料層21來形成凹陷區域RC的製程。
此後,省略對與上述製造製程採用相同方式的另外製程的內容的描述。
如圖8A所示,在執行雜質注入製程之前,可以在被圖案化成臺階狀的中間所得結構的整個表面上形成阻擋層27。可替選地,如圖8B所示,在執行雜質注入製程之前,可以將暴露在各個臺階處的第一材料層21的側壁氧化,以由此形成多個阻擋層28。
當凹陷區RC的端部被延伸時,為了確保刻蝕餘量,可以形成阻擋層27和28。具體來說,可以形成阻擋層27和28以確保層疊的導電層(焊盤部分)之間的距離。如以上參照圖5A描述的,可以執行增加凹陷區RC的端部的厚度的製程以沿著z軸延伸凹陷區RC的端部,且由此增加焊盤部分PAD的厚度。然而,在刻蝕製程期間凹陷區RC也可以在X方向上延伸。通常,層疊的導電層(焊盤部分)之間的距離可能會減小,因此可能會惡化導電層25的擊穿電壓。然而,根據本發明的一個實施例,由於通過阻擋層27和28確保了刻蝕餘量,所以可以在層疊的導電層(焊盤部分)之間確保足夠的距離,以防止任何惡化。
當形成阻擋層27和28時,可以在阻擋層27和28之上形成層間絕緣層24(未示出)。另外,在用於延伸凹陷區RC的端部的刻蝕製程期間,可以將阻擋層27
和28中的每個刻蝕到預定厚度,但是沒有被刻蝕的其他部分可以保留。例如,形成在層疊結構ST的整個表面上的阻擋層27或形成在焊盤部分PAD的側壁上的阻擋層28可以保留。
圖9A至11A是示出根據本發明的另一個實施例的製造半導體裝置的方法的立體圖,且圖9B至11B是沿著線I-I'截取的截面圖。出於說明的目的,繪製了層疊結構ST的一部分,具體是焊盤結構的一部分。此後,省略與之前描述的實施例相同內容的描述。
如圖9A和圖9B所示,可以相互交替地形成多個第一材料層31和多個第二材料層32。將針對第一材料層31包括犧牲層且第二材料層32包括絕緣層的例子進行描述。
包括第一材料層31和第二材料層32的中間所得結構中的端部可以被圖案化為臺階狀。被圖案化成臺階狀的中間所得結構中的每個臺階可以包括單個第一材料層31和形成在第一材料層31之下的單個第二材料層32。
隨後,可以在被圖案化為臺階狀的中間所得結構的整個表面上形成緩衝層33。緩衝層33可以包括相對於第一材料層31和第二材料層32具有高刻蝕選擇性的材料。例如,緩衝層33可以包括相對於第一材料層31具有高刻蝕選擇性且比第二材料層32具有更高的刻蝕速率的材料層。
另外,由於緩衝層33可以在用於延伸凹陷區
RC的端部的後續刻蝕製程期間被刻蝕到預定厚度,因此可以將緩衝層33形成為具有足夠厚度。
如圖10A和10B所示,可以去除第一材料層31以形成凹陷區RC。在第一材料層31和第二材料層32之上形成層間絕緣層34後,可以穿通層間絕緣層34、第一材料層31和第二材料層32來形成至少一個第一縫隙SL1,使得可以形成分開的層疊結構ST。隨後,可以從經由第一縫隙暴露出的層疊結構ST的側壁來刻蝕並由此去除經由第一縫隙SL1暴露出的第一材料層31。因此,可以從每個層疊結構ST的側部區域去除第一材料層31,同時第一材料層31可以保留在層疊結構ST的中心區域中。
如圖11A和11B所示,可以增加凹陷區域RC的端部的厚度。例如,可以通過凹陷區RC選擇性刻蝕緩衝層33。可以在採用比第二材料層32更高的速率來刻蝕緩衝層33的條件下,來執行刻蝕製程。結果,可以選擇性延伸凹陷區RC的端部。
隨後,可以在凹陷區RC中形成導電層35。結果,在層疊結構ST的端部暴露出的焊盤部分PAD可以具有比導電層35的其他部分更大的厚度。
隨後,可以穿通層間絕緣層34來形成接觸孔,使得焊盤部分PAD可以經由接觸孔而暴露出來,且可以在接觸孔中形成導電層。結果,每個接觸插塞36可以與每個焊盤部分PAD耦接。
圖12A至12D是示出根據本發明的一個實施
例的半導體裝置的單元結構的立體圖。然而,出於說明的目的,沒有繪製絕緣層。
圖12A示出了其中以U形方式形成溝道層的例子。
如圖12A所示,半導體裝置可以包括層疊在基板SUB上的管道閘極PG、字線WL、至少一個汲極選擇線DSL以及至少一個源極選擇線SSL。
半導體裝置還可以包括多個U形溝道層CH。溝道層CH可以包括形成在管道閘極PG中的管道溝道層P_CH、以及與管道溝道層P_CH連接的源極側溝道層S_CH和汲極側溝道層D_CH。
源極側溝道層S_CH可以穿通字線WL和源極選擇線SLL,並且汲極側溝道層D_CH可以穿通字線WL和汲極選擇線DSL。另外,源極側溝道層S_CH可以耦接到源極線SL,而汲極側溝道層D_CH可以耦接到位元線BL。
半導體裝置還可以包括插入在溝道層CH與字線WL之間的存儲層M。
根據半導體裝置的上述結構,可以在源極側溝道層S_CH與源極選擇線SSL之間的連接處形成源極選擇電晶體。可以在源極側溝道層S_CH與字線WL之間的連接處形成源極側記憶體單元。可以在管道溝道層P_CH與管道閘極PG之間的連接處形成管道電晶體。可以在汲極側溝道層D_CH與汲極選擇線DSL之間的連接處形成汲極選擇電晶體。可以在汲極側溝道層D_CH與
字線WL之間的連接處形成汲極側記憶體單元。因此,相互串聯耦接的至少一個源極選擇電晶體、多個源極側記憶體單元、管道電晶體、多個汲極側記憶體單元以及至少一個汲極選擇電晶體可以形成單個存儲串。存儲串可以採用U形方式佈置。
圖12B示出了其中採用垂直形狀方式形成溝道層的例子。
如圖12B所示,半導體裝置可以包括順序地層疊在形成有源極區S的基板SUB上的至少一個下選擇線LSL、字線WL、以及至少一個上選擇線USL。字線WL可以形成為板的形狀,上選擇線USL或下選擇線LSL中的至少任意一個可以具有直線形狀。
半導體裝置還可以包括溝道層CH。溝道層CH可以從基板SUB突出且穿通下選擇線LSL、字線WL和上選擇線USL。溝道層CH的頂部部分可以耦接到位元線BL,溝道層CH的底部部分可以耦接到源極區S。
半導體裝置還可以包括插入在溝道層CH與字線WL之間的存儲層M。
根據半導體裝置的上述結構,可以在溝道層CH與下選擇線LSL之間的相交處形成下選擇電晶體。在溝道層CH與字線WL之間的相交處形成記憶體單元。在溝道層CH和上選擇線USL之間的相交處形成上選擇電晶體。因此,相互串聯耦接的至少一個下選擇電晶體、多個記憶體單元和至少一個上選擇電晶體可以形成單個存儲串。存儲串可以採用垂直方式佈置。
圖12C示出了存儲串採用垂直方式佈置的例子。
如圖12C所示,半導體裝置可以包括順序層疊的源極層S1至S3、至少一個下選擇線LSL、字線WL和至少一個上選擇線USL。
源極層S1至S3可以包括第一源極層S1、第二源極層S2和第三源極層S3。第一源極層S1可以形成在基板SUB上。第三源極層S3可以形成在第一源極層S1中。第二源極層S2可以包圍第三源極層S3並且可以插入在第一源極層S1與第三源極層S3之間。另外,第三源極層S3可以形成為穿通第二源極層S2且與第一源極層S1耦接。第一源極層S1和第二源極層S2中的每個可以包括多晶矽層,且第三源極層S3可以包括諸如鎢(W)層的金屬層。
半導體裝置還可以包括溝道層CH。溝道層CH可以從第二源極層S2的頂表面突出,且形成為穿通下選擇線LSL、字線WL和上選擇線USL。溝道層CH可以以單體結構連接到第二源極層S2。另外,溝道層CH的頂部可以耦接到位元線BL。
半導體裝置還可以包括插入在溝道層CH與字線WL之間的存儲層M。存儲層M可以包圍第二源極層S2和溝道層CH的外表面。
根據上述結構的結構,相互串聯耦接的至少一個下選擇電晶體、記憶體單元和至少一個上選擇電晶體可以形成單個存儲串。存儲串可以採用垂直方式佈置。
圖12D示出了溝道層具有垂直形狀的例子。
如圖12D所示,半導體裝置可以包括順序層疊的層間絕緣層IIL、至少一個下選擇線LSL、字線WL和至少一個上選擇線USL。半導體裝置還可以包括第一源極層S1和第二源極層S2。第一源極層S1可以形成在層間絕緣層IIL中,並且第二源極層S2可以形成在第一源極層S1中。
半導體裝置還可以包括從第一源極層S1突出且穿通下選擇線LSL、字線WL和上選擇線USL的溝道層CH。溝道層CH可以以單體結構連接到第一源極層S1。另外,溝道層CH的頂部部分可以耦接到位元線BL。
半導體裝置還可以包括插入在溝道層CH與字線WL之間的存儲層M。存儲層M可以包圍第一源極層S1和溝道層CH的外表面。
圖12D示出了完全包圍第二源極層S2的底表面的第一源極層S1。然而,第二源極層S2的底表面的一部分也可以突出且穿通第一源極層S1。
根據半導體裝置的上述結構,相互串聯耦接的至少一個下選擇電晶體、多個記憶體單元和至少一個上選擇電晶體可以形成單個存儲串。存儲串可以採用垂直方式佈置。
通過應用上述製造方法來製造參照圖12A至12D描述的半導體裝置。省略了製造方法的詳細描述。
如圖13所示,根據本發明的一個實施例的存儲系統100可以包括非揮發性記憶體裝置120和記憶體
控制器110。
非揮發性記憶體裝置120可以具有上述結構中的任意一個。另外,非揮發性記憶體裝置120可以是包括多個快閃記憶體晶片的多晶片封裝。
記憶體控制器110可以配置成控制非揮發性記憶體裝置120。記憶體控制器110可以包括SRAM 111、CPU 112、主機介面113、ECC 114和記憶體介面115。SRAM 111可以用作CPU 112的操作記憶體。CPU 112可以執行針對記憶體控制器110的資料交換的一般控制操作。主機介面113可以包括與存儲系統100耦接的主機的資料交換協定。另外,ECC 114可以檢測和糾正從非揮發性記憶體裝置120讀取的資料中包括的錯誤。記憶體介面115可以與非揮發性記憶體裝置120接合。記憶體控制器110還可以包括儲存用於與主機接合的代碼資料的ROM。
具有上述配置的存儲系統100可以是組合了記憶體裝置120和記憶體控制器110的固態硬碟(SSD)或存儲卡。例如,當存儲系統100是SSD時,記憶體控制器110可以經由包括USB、MMC、PCI-E、SATA、PATA、SCSI、ESDI和IDE的介面協定中的一種來與外部設備(例如主機)通信。
如圖14所示,根據本發明的一個實施例的計算系統200可以包括與系統匯流排260電耦接的CPU 220、RAM 230、用戶介面240、數據機250和存儲系統210。另外,當計算系統200是移動設備時,可以進一步
包括電池來將操作電壓施加到計算系統200。計算系統200還可以包括應用晶片組、CMOS圖像處理器(CIS)和行動式DRAM。
如以上結合圖13所描述的那樣,存儲系統210可以包括非揮發性記憶體裝置212和記憶體控制器211。
通過選擇性增加導電層的焊盤部分的厚度,可以在用於形成接觸插塞的接觸孔形成製程期間保證刻蝕餘量。因此,可以防止在接觸孔形成製程中出現穿孔現象和未打開現象。
ST‧‧‧層疊結構
SL1‧‧‧第一縫隙
CH‧‧‧溝道層
SL2‧‧‧第二縫隙
13‧‧‧第二導電層
14‧‧‧第二絕緣層
CELL‧‧‧單元區
CS‧‧‧單元結構
CONTACT‧‧‧接觸區
PS‧‧‧焊盤結構
11‧‧‧第一導電層
12‧‧‧第一絕緣層
15‧‧‧犠牲層
PAD‧‧‧焊盤部分
Claims (20)
- 一種半導體裝置,包括:基板,前述基板中界定了單元區和接觸區;焊盤結構,前述焊盤結構包括彼此交替地形成在前述基板的前述接觸區中的多個第一導電層和多個第一絕緣層;其中,前述焊盤結構的端部被圖案化為臺階狀,前述第一導電層的在前述焊盤結構的端部暴露出的部分被定義為多個焊盤部分,並且前述多個焊盤部分具有比前述多個第一導電層的未暴露的部分大的厚度。
- 如申請專利範圍第1項的半導體裝置,其中,前述多個第一導電層形成在前述焊盤結構的側部區域中。
- 如申請專利範圍第2項的半導體裝置,還包括多個犧牲層,前述多個犧牲層與前述多個第一導電層耦接且形成在前述焊盤結構的中心區域。
- 如申請專利範圍第3項的半導體裝置,其中,前述焊盤部分具有比前述多個犧牲層更大的厚度。
- 如申請專利範圍第1項的半導體裝置,其中,前述焊盤結構的每個臺階包括前述多個第一導電層中的一個第一導電層和形成在該一個第一導電層之上的第一絕緣層。
- 如申請專利範圍第1項半導體裝置,其中,前述焊盤結構的每個臺階包括前述多個第一導電層中的一個第一導電層和形成在該一個第一導電層之下的第一絕緣 層。
- 如申請專利範圍第1項的半導體裝置,還包括形成在前述多個焊盤部分的側壁上的多個阻擋層。
- 如申請專利範圍第1項的半導體裝置,還包括形成在前述焊盤結構的整個表面上的緩衝層。
- 如申請專利範圍第1項的半導體裝置,還包括形成在前述焊盤結構的整個表面上的阻擋層。
- 如申請專利範圍第1項的半導體裝置,還包括多個接觸插塞,其中前述多個接觸插塞中的每個接觸插塞與前述焊盤部分中的每個焊盤部分耦接。
- 如申請專利範圍第1項的半導體裝置,還包括:單元結構,前述單元結構與前述焊盤結構耦接且包括彼此交替地形成在前述基板的單元區中的多個第二導電層和多個第二絕緣層;以及穿通前述單元結構的多個溝道層。
- 如申請專利範圍第10項的半導體裝置,其中,前述多個溝道層形成為U形或者以垂直形狀方式形成。
- 如申請專利範圍第11項的半導體裝置,其中,形成在相同水平面的前述第一導電層和前述第二導電層相互耦接,且形成在相同水平面的前述第一絕緣層和前述第二絕緣層相互耦接。
- 一種半導體裝置,包括:基板;多個層疊結構,前述多個層疊結構包括相互交替地形成在前述基板上的多個導電層和多個絕緣層,其 中前述多個層疊結構的每個端部被圖案化成臺階狀;以及將前述多個層疊結構相互分隔開的至少一個縫隙;其中前述多個導電層的每一者包含沒有被上導電層覆蓋的焊盤部分以及被前述上導電層覆蓋的剩餘部分,而前述焊盤部分具有比前述剩餘部分更大的厚度。
- 如申請專利範圍第14項的半導體裝置,其中,前述多個導電層形成在前述層疊結構的側部區域中。
- 如申請專利範圍第15項的半導體裝置,其中,前述層疊結構每個包括多個犧牲層,前述多個犧牲層耦接到前述多個導電層且形成在前述層疊結構的中心區域中。
- 如申請專利範圍第16項的半導體裝置,其中,前述焊盤部分具有比前述多個犧牲層的每一者大的厚度。
- 如申請專利範圍第14項的半導體裝置,還包括多個阻擋層,其中前述多個阻擋層的每一者形成在前述焊盤部分的側壁上。
- 如申請專利範圍第14項的半導體裝置,還包括形成在前述層疊結構的整個表面上的緩衝層。
- 如申請專利範圍第14項的半導體裝置,還包括形成在前述層疊結構的整個表面上的阻擋層。
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