TWI497594B - 低介電係數之介電材料的氣相修復與封孔 - Google Patents
低介電係數之介電材料的氣相修復與封孔 Download PDFInfo
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- TWI497594B TWI497594B TW097149366A TW97149366A TWI497594B TW I497594 B TWI497594 B TW I497594B TW 097149366 A TW097149366 A TW 097149366A TW 97149366 A TW97149366 A TW 97149366A TW I497594 B TWI497594 B TW I497594B
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- dielectric material
- nanoporous
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- nanoporous low
- dielectric constant
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- BFXIKLCIZHOAAZ-UHFFFAOYSA-N methyltrimethoxysilane Chemical compound CO[Si](C)(OC)OC BFXIKLCIZHOAAZ-UHFFFAOYSA-N 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02343—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a liquid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Description
本發明係關於奈米多孔低介電係數介電材料的處理方法,尤有關於形成在半導體基板上之奈米多孔低介電係數介電材料的氣相修復與封孔。
隨著積體電路元件的尺寸持續縮小,多個電晶體之間的傳輸信號時間延遲(亦即傳輸延遲),已成為在測定元件效能上越來越重要的參數。傳輸延遲正比於金屬互連線路之電阻(R)與層間介電絕緣材料之電容(C)的乘積(亦稱為RC延遲)。因此,為了儘量減小傳輸延遲,結合一低介電係數絕緣材料與一高導電率金屬(或低電阻率金屬)是有幫助的。低介電係數介電(LKD,Low-k dielectric)材料(k<3.0),例如有機矽酸鹽玻璃(OSG,organosilicate glass)、四乙氧基矽烷(TEOS,tetraethylorthosilicate)、氟化矽玻璃(FSG,fluorinated silica glass)及碳摻雜氧化物亦正取得作為氧化矽(k=3.8-4.0)之替代選擇物的關注。為了得到較低的介電值,LKD材料可包含一互連奈米多孔結構,其捕獲空氣(k=1)以降低塊材LKD之整體介電係數值。同樣地,銅(Cu)因其較低的電阻值(R
<2μΩ-cm),在作為更習用之鋁(Al)互連金屬(R
=3.0-5.0μΩ-cm)的替代選擇物上,已取得作為互連線路金屬相當大的關注。
因為銅不容易形成易揮發的副產物,習用的或移除性的蝕刻技術無法適用。因此,需要金屬鑲嵌製造程序來形成圖形化之銅互連線路,該製程包含在先前已圖形化之開口(例如溝渠或通孔)內沉積導電材料。因此,金屬鑲嵌製程需要在LKD材料中蝕刻先前圖形化之開口。此蝕刻係藉在遮罩層(例如光阻)中圖形化開口而在介電層上形成溝渠或通孔的形狀,隨後施以濕式或乾式蝕刻而施行。然而,LKD材料的蝕刻、灰化或清洗可能潛在地損傷LKD材料。
茲提供一種處理形成在半導體基板上之奈米多孔低介電係數介電材料的方法。該低介電係數介電材料具有蝕刻開口,該蝕刻開口具有在蝕刻開口外表面及互連孔內表面上包含矽醇基之蝕刻損傷區域。首先,將該低介電係數介電材料與一氣相觸媒接觸,該氣相觸媒的量係足以使該蝕刻損傷區域中之該觸媒及該矽醇基之間形成氫鍵,而形成一觸媒中間物。第二,使該低介電係數介電材料與一氣相烷氧矽烷修復劑接觸,該氣相烷氧矽烷修復劑的量係足以與約50%或更多之該蝕刻損傷區域中之該矽醇基反應,俾使該烷氧矽烷修復劑與該觸媒中間物反應;及/或使該低介電係數介電材料與一氣相烷氧矽烷密封劑接觸,該氣相烷氧矽烷密封劑的量係足以防止一上覆之阻隔層擴散進入該互連孔,俾使該烷氧矽烷密封劑與該觸媒中間物反應。
在另一實施例中,提供一種處理形成在半導體基板上之奈米多孔低介電係數介電材料的方法。該低介電係數介電材料具有蝕刻開口,該蝕刻開口具有在蝕刻開口外表面及互連孔內表面上包含矽醇基之蝕刻損傷區域。首先,將該低介電係數介電材料與一氣相有機酸觸媒接觸,該氣相有機酸觸媒的量係足以使該蝕刻損傷區域中之該觸媒及該矽醇基之間形成氫鍵,而形成一觸媒中間物。第二,使該低介電係數介電材料與一氣相烷氧矽烷修復劑接觸,該氣相烷氧矽烷修復劑的量係足以與約50%或更多之該蝕刻損傷區域中之該矽醇基反應,俾使該烷氧矽烷修復劑與該觸媒中間物反應;及/或將該低介電係數介電材料與一氣相烷氧矽烷密封劑接觸,該氣相烷氧矽烷密封劑的量係足以防止一上覆之阻隔層擴散進入該互連孔,俾使該烷氧矽烷密封劑與該觸媒中間物反應。
圖1係金屬鑲嵌製造程序的一例示實施例。圖1A顯示一半導體基板100與一覆蓋其上之奈米多孔LKD材料層110。使用遮罩層120,形成開口130於奈米多孔LKD材料層110中。基於例示用途,僅顯示一個開口130,其可為許多通孔或溝渠其中之一。例如,遮罩層120可為一有機光阻而開口130可由電漿蝕刻形成。在電漿蝕刻完成後,遮罩層120可立即藉由灰化(亦即在氧基電漿中之乾式蝕刻)而移除。
在圖1B中,阻隔層140可形成於開口130之側壁及底部表面上,用以保護鄰近銅配線之奈米多孔LKD材料層110,使其不受擴散進入鄰近介電材料之銅原子所毒化。例示的阻隔材料包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、釕(Ru)、釕氧化物(RuOx
)以及其合金。例如,吾人可藉由物理氣相沉積(PVD,physical vapor deposition)、原子層沉積(ALD,atomic layer deposition)或類似方式塗布阻隔材料。
圖1C中,開口130以塊材銅層150填充。例如,塊材銅層150可藉由沉積晶種層並接著進行無電銅電鍍而形成。如圖1D所例示,藉由任何合適的技術例如化學機械平坦化(CMP,chemical mechanical planarization)將該結構平坦化,以移除塊材銅層150的多餘部分。
金屬鑲嵌製造程序可為單金屬鑲嵌製程或雙金屬鑲嵌製程。就後者製程而言,可使用通孔優先法(via-first approach)或溝渠優先法(trench-first approach)。
在金屬鑲嵌結構中成功的施用奈米多孔LKD材料之前,許多障礙必須被克服。首先,藉由蝕刻及灰化移除遮罩層120而形成開口130(例如通孔及溝渠)的製程可能潛在地損傷奈米多孔LKD材料。第二,阻隔層140的材料(例如Ti、TiN、Ta、TaN、Ru或RuOx
)可能潛在地滲透進入奈米多孔LKD材料層110的互連孔,而連累其低介電值。第三,由於在許多奈米多孔LKD材料中存在互連孔,由奈米多孔LKD材料所形成的結構對於隨後的製程步驟(例如CMP)可能缺乏機械強度。因此,存在修復損傷的奈米多孔LKD材料、密封開口130的表面、及增強LKD材料的機械強度之需求。
在電漿蝕刻及灰化期間,至少一部分的含碳部分(moieties)(亦即甲基或-CH3
基)可被移除,導致產生疏水性降低的奈米多孔LKD材料。當含碳基元自奈米多孔LKD材料移除時,Si-C鍵結被Si-OH(矽醇)鍵或基所取代,而所產生之介電層喪失其疏水性,因為來自大氣或隨後的濕式清洗步驟之水分子與矽醇基形成強烈氫鍵交互作用。介電係數約70之水的存在,導致奈米多孔LKD材料的介電係數值顯著增加。例如,在奈米多孔LKD材料開口(例如通孔或溝渠)的電漿蝕刻期間,電漿損傷可延伸進入開口的側壁約30nm之深度。在進入電漿損傷的奈米多孔LKD材料約5nm深度處,約25%之甲基(-CH3
)損耗(亦即25%之Si-C鍵被Si-OH鍵或基取代)。
蝕刻損傷的奈米多孔LKD材料可以烷氧矽烷劑處理,其可與Si-OH反應。然而,使用烷氧矽烷劑有一缺點,即在縮合步驟中與表面結合Si-OH基縮合之前,需要水來水解烷氧基。因此,伴隨使用例如烷氧矽烷劑之化合物而來的其中一個挑戰為修復的一致性。上述關係到水在烷氧矽烷與Si-OH基之間的化學反應中扮演的關鍵角色。如圖2所例示,在水解步驟中與Si-OH基縮合之前,需要水來水解烷氧基。
表面上因大氣溼氣所促使之不同程度的氫鍵水,直接影響反應效率。不使用觸媒的狀況下,烷氧矽烷與Si-OH基之間的化學反應使得些許水必須存在。此外,如果需要一致的結果,各樣本之間需維持實質上相同程度的水合作用。
路易斯鹼胺類(例如氨、甲基胺、二甲基胺或三甲基胺)可用以當作觸媒,以在沒有水解步驟下增進烷氧矽烷與Si-OH基之間的縮合速率。如圖3所例示,路易斯鹼胺類藉由與Si-OH基形成觸媒中間物而供作觸媒。觸媒中間物因為路易斯鹼胺類與Si-OH基之間生成氫鍵而形成。此氫鍵的形成促使反應進行,允許Si-OH基與烷氧矽烷劑之烷氧基直接反應。觸媒中間物本身對於與烷氧矽烷劑之反應極為敏感。該反應產生作為副產物之對應醇,而胺類被釋放再與額外的Si-OH基形成氫鍵。此外,烷氧矽烷化合物可水平網狀連接而形成三維水平網狀結構,恢復奈米多孔LKD材料的機械強度。
有機酸亦可用作水解烷氧矽烷以形成Si-OH基的觸媒,其在熱能存在下與表面結合Si-OH基縮合。此外,如圖4所例示,有機酸可被用來催化水與殘留在修復及/或水平網狀連接的奈米多孔LKD材料上之實質上大部分的殘存烷氧基之間的反應。在圖4A中,有機酸催化水與殘存烷氧基之間的水解反應,其產生如圖4B所示之Si-OH基。在圖4C中,鄰近之矽烷化合物的Si-OH基隨後縮合而形成水平網絡。該有機酸可為pKa最高約為7之任何有機酸,較佳地係高達約4,最佳地係高達約3。該有機酸可包含醋酸、三氟乙酸、三氯乙酸、檸檬酸、其他完全或部分鹵化之弱酸、及其各種之結合。
吾人已證明此等路易斯鹼胺類及有機酸觸媒可在超臨界CO2
(或SCCO2
)媒介中,不經基本的水解步驟而在動力上增進烷氧矽烷與表面結合Si-OH基之間的縮合速率,如揭露於共同讓渡的美國專利申請案第11/475,206號者,其整體以參考資料方式併入。
在此說明一種修復及/或密封蝕刻損傷的奈米多孔LKD材料之新穎方法,其係使用與氣相路易斯鹼胺類或有機酸觸媒相耦合之氣相單、二、或三官能烷氧矽烷劑。修復劑及密封劑可以通式表示成Si-(R)x
(OR')y
,其中y≧1,x+y=4,R係烷基、芳香基或氫氧基而R'係烷基或芳香基,較佳地係甲基或乙基。
烷氧矽烷修復劑之特徵可為較小尺寸分子,約80至約125原子質量單位(AMU,atomic mass units),其可經由互連多孔網擴散進入奈米多孔LKD材料之塊材而與矽醇基反應。在修復完成之後,50%或更多的損耗甲基被立即以烷基(例如乙基、丙基、丁基)補充,較佳地係約75%至約90%的甲基被補充。
修復劑的例子可包含甲基三甲氧矽烷(CH3
-Si-(O-CH3
)3
)、二甲氧二甲基矽烷((CH3
)2
-Si-(OCH3
)2
)、甲氧三甲基矽烷((CH3
)3
-Si-OCH3
)或正丙基三甲氧矽烷(CH3
-CH2
-CH2
-Si-(OCH3
)3
or n-PTMS)。
烷氧矽烷密封劑之特徵可為較大尺寸分子的,自約200至約400原子質量單位。奈米多孔LKD材料的封孔係以尺寸排除的原理運作,其中較大尺寸的烷氧矽烷密封劑與表面結合Si-OH基有反應性的碰撞,而不是通過奈米多孔LKD材料的孔洞開口而進入多孔網。烷氧矽烷密封劑在小於約3至4nm的深度與表面矽醇基反應,較佳地係在約1至2nm的深度。在密封製程完成之後,開口之側壁與底部表面即被一厚度至多約2nm的膜包覆。此膜有效防止上覆之阻隔材料擴散進入奈米多孔LKD材料的互連孔;然而,必須注意的是,由於氣相觸媒之分子尺寸較小,其可繼續擴散進入奈米多孔LKD材料。
密封劑的例子可包含:雙(二甲氧基甲基)矽氧烷、雙(甲基二甲氧矽丙基)-N-甲基胺、雙(三乙氧矽基)乙烷、1,2-雙(三甲氧矽基)己烷、雙(三甲氧矽丙基)胺或雙(3-(三乙氧矽基)丙基)-二硫化物。
如圖5A所例示,帶有奈米多孔LKD材料層110之半導體基板100被置於處理室200中以處理因蝕刻及/或光阻灰化所導致之損傷。處理室200可在壓力自約1mTorr至約3750Torr(亦即約5bar)及溫度最高約達300℃下操作。
奈米多孔LKD材料層110包含先前蝕刻之開口130(例如溝渠或通孔)。由於先前之蝕刻及/或覆蓋其上之遮罩層的移除,奈米多孔LKD材料層110的曝露表面被蝕刻損傷。雖然圖5A中沒有例示,奈米多孔LKD材料層110可以例如阻隔層及導體或半導體層之中間層覆蓋其上。
奈米多孔LKD材料的例子可包含但不限於:及(由Honeywell International製造)、碳摻雜氧化物例如BLACK(由APPLIED MATERIALS製造)、(由NOVELLUS製造)、(由ASM製造)、(由Trikon製造)、LKD-5109(由JSR製造)、以及奈米叢生之氧化矽(Nano-Clustered Silica)或NCS(由FUJITSU製造)。許多奈米多孔LKD材料的一個特徵為存在互連孔結構,其具有平均孔洞尺寸約2奈米之狹窄孔洞尺寸分布。
半導體基板100可被置於基板支座210上。基板支座210可包含靜電夾盤(ESC,electrostatic chuck)、機械夾或其他夾持機構、以及一或更多用以加熱半導體基板100至最高為300℃溫度之加熱元件。
化學蒸氣傳輸系統220A、220B、220C可用以依序地分別傳輸觸媒、烷氧矽烷修復劑及烷氧矽烷密封劑至處理室200。一旦已完成利用觸媒、烷氧矽烷修復劑或烷氧矽烷密封劑的處理,可利用真空泵浦240自處理室200排空氣體。吾人藉背壓調節器250來維持處理室200中之靜氣壓,該背壓調節器之功能為在氣體壓力超過預設壓力時釋放蒸氣至化學減量系統。
圖5B顯示一液態劑(例如觸媒、烷氧矽烷修復劑或烷氧矽烷密封劑)用之化學蒸氣傳輸系統220的實施例。來自處理劑源224之液態劑222可被置於起泡器226中,起泡器被加熱至升高的溫度以蒸發液態劑222。一來自氣體源228之惰性氣體(例如氮氣或氬氣)冒泡經過液態劑222,以經由氣體線230而傳輸蒸發的處理劑至處理室200。氣體線230可被加熱以防止氣體線230內蒸發的處理劑凝結。
半導體基板100在任何修復及/或密封處理之前被置放成與氣相觸媒接觸。如上述,路易斯鹼胺類或有機酸觸媒之功用為在動力上增進烷氧矽烷與Si-OH基之間的縮合速率,在路易斯基胺類觸媒之情況下可不需一級水解步驟,而在有機酸之情況下其可加速水解作用。處理室200及基板支座210的溫度可被加熱至約60℃至約275℃之第一溫度,較佳地係約100℃至約200℃。為了防止任何氣相處理劑的凝結,整個處理從頭到尾半導體基板100的溫度較佳地係維持在較氣相處理劑為高的溫度下。
一開始,將處理室200的壓力維持在真空壓力下,以幫助觸媒蒸發(例如約0.5Torr至約10Torr)。化學蒸氣傳輸系統220A傳輸氣相觸媒至處理室200以處理半導體基板100。將半導體基板100設置成與數量足以與在蝕刻損傷區域中的矽醇基互相作用的氣相觸媒接觸。例如,氣相的觸媒可在奈米多孔LKD材料層110之開口130的外表面(亦即側壁表面)及互連孔內表面上形成次單層或單層的觸媒。在一實施例中,電漿損傷區域可延伸至進入開口130的側壁約30nm的深度。
在一實施例中,觸媒被傳輸至處理室200以增加處理室200中氣相觸媒的靜壓力至約20Torr至約1500Torr(亦即約2bar),較佳地係約100Torr至約760Torr。處理室200的體積係約1.1公升。氣相觸媒的接觸時間可約10秒至約60秒,較佳地係約20秒至約30秒。在與氣相觸媒的處理完成之後,殘餘氣相觸媒可藉由惰性氣體的動態流或真空泵浦240而自處理室200移除,直到達到低於約5Torr之壓力為止。在另一實施例中,動態真空可藉由在真空泵浦240及/或背壓調節器250同時操作時令氣相觸媒流入至處理室中而加以維持。
例示的路易斯鹼胺類可包含氨(NH3
)、甲基胺(CH3
NH2
)、二甲基胺((CH3
)2
NH)或三甲基胺(N(CH3
)3
),或對應之一級、二級、或三級乙基取代胺類。例示的有機酸可包含醋酸、三氟乙酸、三氯乙酸、檸檬酸、其他完全或部分鹵化之弱酸。在一實施例中,有機酸可與水混合以形成被蒸發之水溶液。處理室200及基板支座210的溫度及靜壓力係根據特定的路易斯鹼胺類或有機酸而選定,以防止路易斯鹼胺類觸媒或有機酸的凝結。如果使用有機酸,為了最大化烷氧矽烷與表面鍵結Si-OH基之反應,過量的氣相有機酸較佳地係在引入烷氧矽烷修復及/或密封劑之前被清除排空,以防止在氣相中有機酸及烷氧矽烷之間的反應。
在與氣相觸媒的處理完成之後,使處理室200的壓力減低至真空壓力,以幫助烷氧矽烷修復劑的蒸發(例如約0.5Torr至約10Torr)。處理室200可選擇性地在排空至真空壓力之前回填惰性氣體(例如氮氣或氬氣)。可將處理室200及基板支座210的溫度維持在約60℃至約275℃之第一溫度,較佳地係約100℃至約200℃。化學蒸氣傳輸系統220B傳輸烷氧矽烷修復劑至處理室200以處理半導體基板100。半導體基板100被置於與烷氧矽烷修復劑接觸,烷氧矽烷修復劑的量能夠有效地以烷基(例如乙基、丙基、丁基)恢復至少50%的損耗甲基,較佳地係約75%至約90%的損耗甲基。
在一實施例中,一固定量的烷氧矽烷修復劑被傳輸至處理室200,以使傳輸室200中的修復劑之靜壓力為約20Torr至約1500Torr(例如約2bar),較佳地係約100Torr至約760Torr。在第一溫度下,半導體基板100與氣相烷氧矽烷修復劑的全部接觸時間可為約10秒至約180秒,較佳地係約20秒至約60秒。在另一實施例中,動態真空可藉由在真空泵浦240及/或背壓調節器250同時操作時令氣相修復劑流入至處理室200中而加以維持。
為了增加烷氧矽烷修復劑與在奈米多孔LKD材料層110的塊材中之矽醇基之反應性,在第一溫度下與烷氧矽烷修復劑完成接觸之後,較佳狀況為使奈米多孔LKD材料層110在第二溫度下與烷氧矽烷修復劑接觸。基板支座210的溫度可由第一溫度增加至約80℃至約300℃之第二溫度,較佳地係約150℃至約250℃。在第二溫度下,半導體基板100與氣相烷氧矽烷修復劑的全部接觸時間可約10秒至約180秒,較佳地係約20秒至約60秒。
例示的烷氧矽烷修復劑可包含甲基三甲氧基矽烷(CH3
-Si-(O-CH3
)3
)、二甲氧基二甲基矽烷((CH3
)2
-Si-(OCH3
)2
)、甲氧三甲基矽烷((CH3
)3
-Si-OCH3
)、或正丙基三甲氧矽烷(CH3
-CH2
-CH2
-Si-(OCH3
)3
或n-PTMS)。處理室200及基板支座210的溫度及靜壓力係根據特定的烷氧矽烷修復劑而選定,以防止烷氧矽烷修復劑的凝結。在LKD材料表面的烷氧矽烷修復劑的凝結可能是有害的,其阻礙烷氧矽烷修復劑均勻滲透進入奈米多孔LKD材料。為確保處理劑處於其氣相狀態,使奈米多孔LKD材料在處理劑的飽和點下與其接觸(亦即在一既定溫度下之氣相壓力小於760Torr)。在此等條件下,在奈米多孔LKD材料上不發生飽和(亦即液態處理劑的形成)。
為了自半導體基板100移除過量的處理劑及反應的副產物,將真空室的壓力減低至約0.5Torr持續約30秒至約180秒。或者,可將處理室中的壓力維持在一固定程度,而可使用惰性沖洗氣體的動態流來移除殘存處理劑。
如果需要,上述氣相觸媒及氣相烷氧矽烷修復劑與奈米多孔LKD材料接觸的處理步驟,可在第二溫度下於同一半導體基板100上重複一次或多次,以增加烷氧矽烷修復劑的反應性。例如,氣相觸媒及烷氧矽烷修復劑與奈米多孔LKD材料的接觸可重複最高至十次。
一旦與氣相修復劑的處理已完成,奈米多孔LKD材料層110的表面可藉由使半導體基板100與烷氧矽烷密封劑接觸而密封。如上述,該密封步驟以厚度厚至約2nm的烷氧矽氧膜覆蓋開口的側壁及底部表面,以有效防止上覆的阻隔材料擴散進入奈米多孔LKD材料的互連孔。在密封處理之前,可選擇性地使奈米多孔LKD材料層110與氣相觸媒接觸。
密封處理與上述的修復處理完全相似,包含與氣相觸媒的處理。然而,係使用烷氧矽烷密封劑取代烷氧矽烷修復劑。例示的烷氧矽烷密封劑可包含雙(二甲氧甲基)矽氧烷、雙(甲基二甲氧矽丙基)-N-甲基胺、雙(三乙氧矽基)乙烷、1,2-雙(三甲氧矽基)己烷、雙(三甲氧矽丙基)胺或雙(3-(三乙氧矽)丙基)-二硫化物。
如果開口130的側壁及底部的電漿損傷極微小且不需修復,奈米多孔LKD材料層110的表面可藉由使表面與烷氧矽烷密封劑接觸加以密封,而不需要初始修復步驟。在此情況下,會使半導體基板100及奈米多孔LKD材料層110在密封處理之前與氣相觸媒接觸。
如果需要,在修復及/或密封處理已完成之後,可使烷氧矽烷化合物水平網狀連接而形成三維水平網狀結構,恢復奈米多孔LKD材料的機械強度。吾人可藉由以上述有機酸(例如醋酸、三氟乙酸、三氯乙酸、檸檬酸)處理LKD材料而催化水與殘存烷氧基之間的水解反應,如圖4所例示,而施行此水平網狀連接步驟。在一較佳的實施例中,可使用化學蒸氣傳輸系統220,在上述的溫度、壓力及時間範圍下,將有機酸蒸氣傳輸至處理室200。使LKD材料與足以水平網狀連接烷氧矽烷修復劑及/或密封劑之量的氣相觸媒接觸。
在與有機酸蒸氣的處理已完成之後,半導體基板100的溫度增加至約200℃至約300℃持續約60秒至約360秒。此加熱步驟可幫助鄰近的烷氧矽烷分子之間的縮合反應而形成三維水平網狀結構以恢復奈米多孔LKD材料的機械強度。此加熱步驟可發生在處理室200之內,或可移除半導體基板100並在加熱板上加熱。
在氣相修復及密封完成之後,可使半導體基板100歷經隨後的金屬鑲嵌處理步驟,包含開口130中阻隔層140的沉積、在開口130中形成塊材銅層150及整個結構的平坦化,如圖1B-1D所例示。在奈米多孔LKD材料層110中,開口130之側壁及底部表面的氣相密封可以防止用以形成阻隔層140的材料(例如Ti、TiN、Ta、TaN、Ru或RuOx
)滲透進入奈米多孔LKD材料層110的互連孔。奈米多孔LKD材料層110的氣相修復及密封產生更堅固的結構,其可抵擋包含CMP在內的進一步機械處理步驟。
在一例示實施例中,帶有蝕刻損傷之奈米多孔LKD材料層110的半導體基板100,係使用氣相甲基三甲氧基矽烷(CH3
-Si-(O-CH3
)3
)作為修復劑及氣相二乙基胺((CH3
)2
NH)作為觸媒而加以修復。
帶有蝕刻損傷之奈米多孔LKD材料層110的半導體基板100被置於處理室200的基板支座210上。處理室200被排空至低於50Torr的壓力,而基板支座210及處理室200被加熱至約100℃之第一溫度。二乙基胺蒸氣自化學蒸氣傳輸系統220A傳輸至處理室200至固定壓力700Torr。使半導體基板100與二乙基胺蒸氣接觸持續約20秒。
二乙基胺蒸氣處理已完成之後,蒸氣以真空泵浦240在動態真空下排空,以降低處理室200的壓力至約5Torr或更低,以移除殘存的胺類及幫助大氣條件下為液體的甲基三甲氧基矽烷的蒸發。
甲基三甲氧基矽烷(CH3
-Si-(O-CH3
)3
)蒸氣自化學蒸氣傳輸系統220B流入處理室200直到達到400Torr之靜壓力。使半導體基板100與甲基三甲氧基矽烷蒸氣在約100℃之第一溫度下接觸約20秒。
基板支座210的溫度由約100℃之第一溫度增加至約150℃之第二溫度,然後使半導體基板100與氣相甲基三甲氧基矽烷接觸額外的30秒。
甲基三甲氧基矽烷蒸氣處理已完成之後,以真空泵浦240在動態真空下排空蒸氣,以降低處理室200的壓力至約0.5Torr或更低持續約60秒,以移除過量的甲基三甲氧基矽烷蒸氣及反應副產物。
在另一實施例中,使用氣相雙(3-甲基二甲氧矽丙基)-N-甲基胺作為密封劑及氣相甲基胺(CH3
NH2
)作為觸媒,密封帶有蝕刻損傷之奈米多孔LKD材料層110的半導體基板100。
將帶有蝕刻損傷之奈米多孔LKD材料層110的半導體基板100置於處理室200的基板支座210上。處理室200被排空至低於50Torr的壓力,而基板支座210及處理室200被加熱至約150℃之第一溫度。甲基胺蒸氣自化學蒸氣傳輸系統220A被傳輸至處理室200達靜壓力1800Torr。使半導體基板100與甲基胺蒸氣接觸約60秒。
甲基胺蒸氣處理已完成之後,以真空泵浦240在動態真空下排空蒸氣,以降低處理室200的壓力至約300Torr或更低。
以約3000sccm下之乾燥氮氣作為載氣,將流動的雙(3-甲基二甲氧矽丙基)-N-甲基胺自化學蒸氣傳輸系統220C導引流入處理室200。壓力係藉真空泵浦240的同時運作而維持至400Torr。使半導體基板100與流動的雙(3-甲基二甲氧矽丙基)-N-甲基胺在約150℃下接觸約180秒。
雙(3-甲基二甲氧矽丙基)-N-甲基胺蒸氣處理完成之後,蒸氣以真空泵浦240在動態真空下排空,以降低處理室200的壓力至約2Torr或更低持續約60秒。
製備帶有覆蓋其上的奈米多孔LKD材料(JSR LKD-5109,由JSR Corporation製造)之矽基板樣本。將該樣本以光阻塗布、圖型化且施以反應性離子蝕刻(RIE,reactive ion etching)而形成溝渠,隨後以氧氣灰化移除光阻。RIE及光阻移除產生了圍繞圖型區中之蝕刻開口的電漿損傷區域。
在與氣相n-丙基三甲氧基矽烷(n-PTMS)修復劑接觸之前,使帶有電漿損傷之JSR LKD-5109層的第一個樣本與氣相三氟乙酸觸媒接觸。以n-PTMS修復劑及溶解於超臨界CO2
(SCCO2
)中的三氟乙酸觸媒處理帶有電漿損傷之JSR LKD-5109層的第二樣本。第三樣本係帶有未修復之電漿損傷JSR LKD-5109層的對照(control)樣本。第四樣本係帶有如上沉積的JSR LKD-5109層(亦即未施行電漿蝕刻)的另一個對照樣本。以掃描式電子顯微鏡(scanning electron microscopy)分析樣本,以沿著蝕刻溝渠側壁將修復的程度特徵化,且利用二次離子質譜儀(SIMS,secondary ion mass spectrometry)以將JSR LKD-5109層表面上至約150nm深度的碳矽比值特徵化。
將帶有電漿蝕刻損傷之JSR LKD-5109的第一樣本置於處理室200的基板支座210上。處理室200被排空至低於50Torr的壓力,而基板支座210及處理室200被加熱至約135℃之第一溫度。三氟乙酸比水3:1的混合物經蒸發而自化學蒸氣傳輸系統220A導引進入處理室200至900Torr之壓力。在處理室200被以氮氣回填且排空之前,使第一樣本與三氟乙酸蒸氣接觸約120秒。氣相n-PTMS修復劑藉化學蒸氣傳輸系統220B傳輸至處理室200,以在約1000Torr之靜壓力下處理第一樣本5分鐘。處理室200被回填以氮氣且第一樣本被維持在135℃的溫度下持續2分鐘。第一個樣本接著自處理室移出,且在約250℃下於加熱板上加熱約120秒。
將第二樣本置於一加熱的壓力容器中(亦即約140℃),隨後將其密封且以超臨界二氧化碳(SCCO2
)加壓至約97,500Torr(約130bar)。使用藉由抽取額外的SCCO2
進入容器並沖洗觸媒進入容器之高壓注射環路,將三氟乙酸比水3:1的混合物添加至容器中。添加完成後的觸媒濃度約為1%容積濃度,而最終的壓力在約140℃下為約150,000Torr(約200bar)。在約60秒時間之後,含酸觸媒的SCCO2
溶液藉添加純SCCO2
而自處理室沖洗出。在約2分鐘的時間中,該沖洗造成約6個流體周轉率(turnover)(亦即一時間週期中等同於容器體積所需的流動量)。在沖洗之後,藉由移除SCCO2
,容器中的壓力在約140℃減低至約97,500Torr(約130bar)。隨後使用高壓注射環路,藉灌注額外的SCCO2
進入容器,而將n-丙基三甲氧基矽烷(n-PTMS)修復劑添加至容器中。修復劑的濃度約2%容積濃度,而容器中最後的壓力在約140℃下為約150,000Torr(約200bar)。在5分鐘的時間之後,以一流速下之純SCCO2
沖洗該容器持續一時間,以容許在約2分鐘的時間中有8個流體周轉率。容器中的壓力被降低至大氣壓,然後移出第二樣本。
將第一樣本(亦即n-PTMS氣相修復)、第二樣本(亦即n-PTMS SCCO2
修復)以及第三樣本(亦即未修復)以SEM特徵化。將各樣本在1%HF溶液中蝕刻約60秒,然後以去離子水沖洗。由於1%HF溶液優先地蝕刻來自奈米多孔LKD材料之Si-OH基,修復的程度可藉沿著溝渠側壁的底切(undercutting)深度加以特徵化。圖6A顯示第一樣本(亦即n-PTMS氣相修復)的SEM影像,其中量測底切係在進入溝渠側壁約11nm的深度。圖6B顯示第二樣本(亦即n-PTMS SCCO2
修復)的SEM影像,其中量測底切係在進入溝渠側壁約11nm的深度。圖6C顯示第三樣本(亦即未修復)的SEM影像,其中量測底切係在進入溝渠側壁約43nm的深度。因此,圖6A-6B顯示,氣相修復在蝕刻損傷之奈米多孔LKD材料的修復上如同SCCO2
般有效。
將第一樣本(亦即n-PTMS氣相修復)、第二樣本(亦即n-PTMS SCCO2
修復)、第三樣本(亦即未修復)以及第四樣本(亦即如上沉積之JSR LKD-5109)藉由SIMS來特徵化,以測定碳矽比值(深度的函數),其中各樣本的表面被噴濺,然後以質譜儀分析噴濺期間所形成的二次離子。
如圖7所例示,如上沉積的JSR LKD-5109之第四樣本的碳矽比值(圖7中實心方形)係約0.55。就第三樣本(圖7中空心方形)而言,在溝渠蝕刻及光阻移除已完成之後,碳矽比值減小至約0.45至約0.55。然而,就第二樣本(圖7中空心圓形)而言,碳矽比值增加至約0.6至約0.8,高於在如上沉積的JSR LKD-5109的碳矽比值。這是因為修復處理將損耗之甲基(-CH3
)以丙基(-C3
H7
)取代,因此增加損傷區域的碳矽比值。就第一樣本(圖7中實心圓形)而言,有一最高約至1.45之明顯的碳矽比值增加,此可能表示氣相修復更有效地使n-PTMS及/或多孔表面密封變得緻密。
雖然本發明已詳細參照特定實施例敘述,但很明顯的,熟習此技術者在不背離後附之申請專利範疇內,可施行各種改變、調整及等效物之利用。
100...半導體基板
110...奈米多孔LKD材料層
120...遮罩層
130...開口
140...阻隔層
150...塊材銅層
200...處理室
210...基板支座
220...化學蒸氣傳輸系統
220A...化學蒸氣傳輸系統
220B...化學蒸氣傳輸系統
220C...化學蒸氣傳輸系統
222...液態劑
224...處理劑源
226...起泡器
228...氣體源
230...氣體線
240...真空泵浦
250...背壓調節器
圖1A-1D說明金屬鑲嵌製造程序之一例示實施例。
圖2說明矽烷之水解沉積。
圖3A說明在路易斯鹼胺類存在下,表面鍵結之Si-OH基與n-丙基三甲氧基矽烷(n-PTMS)之間形成矽烷化合物的反應。
圖3B說明烷氧基轉成Si-OH基之轉換。
圖3C說明鄰近矽烷化合物之間水平網絡之形成。
圖4A-4D說明在有機酸存在下,鄰近矽烷化合物之間水平網絡之形成。
圖5A說明修復及/或密封具有奈米多孔LKD材料之半導體基板用之處理室及化學蒸氣傳輸系統。
圖5B說明液態劑之蒸發及傳輸用之化學蒸氣傳輸系統。
圖6A-6C係掃描式電子顯微鏡(SEM)之影像,其沿著蝕刻溝渠側壁將氣相修復樣本、超臨界CO2
修復樣本以及未修復樣本之修復程度特徵化。
圖7說明來自二次離子質譜儀分析(SIMS)之碳矽比值(深度之函數),其係對於氣相修復樣本、超臨界CO2
修復樣本、未修復樣本及如上沉積樣本。
100...半導體基板
110...奈米多孔LKD材料層
130...開口
200...處理室
210...基板支座
220A...化學蒸氣傳輸系統
220B...化學蒸氣傳輸系統
220C...化學蒸氣傳輸系統
240...真空泵浦
250...背壓調節器
Claims (20)
- 一種處理奈米多孔低介電係數介電材料的方法,該奈米多孔低介電係數介電材料係形成在半導體基板上,該奈米多孔低介電係數介電材料包含具有蝕刻損傷區域之蝕刻開口,該蝕刻損傷區域在該蝕刻開口之外表面及互連孔之內表面上含有矽醇基,該方法包含:(a)使該奈米多孔低介電係數介電材料與處於氣相之一觸媒接觸,該觸媒的量係足以使在該蝕刻損傷區域中之該觸媒及該矽醇基之間形成氫鍵,而形成一觸媒中間物,接著進行以下步驟(b)及(c)其中至少一者:(b)使於步驟(a)中取得之該奈米多孔低介電係數介電材料與處於氣相之一烷氧矽烷修復劑接觸,該烷氧矽烷修復劑的量係足以與在該蝕刻損傷區域中約50%或更多之該矽醇基反應,俾使該烷氧矽烷修復劑與該觸媒中間物反應;(c)使於步驟(a)或(b)中取得之該奈米多孔低介電係數介電材料與處於氣相之一烷氧矽烷密封劑接觸,該烷氧矽烷密封劑的量係足以防止一上覆之阻隔層擴散進入該互連孔,俾使該烷氧矽烷密封劑與該觸媒中間物反應。
- 如申請專利範圍第1項之處理奈米多孔低介電係數介電材料的方法,其中:(i)該觸媒係一路易斯鹼胺類或一有機酸;(ii)在步驟(c)之前,重複步驟(a)及步驟(b)最多達十次;(iii)該烷氧矽烷密封劑在該蝕刻開口的該外表面上形成一最多達2nm厚度之烷氧矽烷膜;及/或(iv)該烷氧矽烷修復劑具有約80至約125之原子質量單位,而該烷氧矽烷密封劑具有約200至約400之原子質量單位。
- 如申請專利範圍第1項之處理奈米多孔低介電係數介電材料的方法,更包含在步驟(c)之前重複步驟(a)。
- 如申請專利範圍第2項之處理奈米多孔低介電係數介電材料的 方法,其中該路易斯鹼胺類係氨(NH3 )、甲基胺(CH3 NH2 )、二甲基胺((CH3 )2 NH)或三甲基胺(N(CH3 )3 );或該有機酸係醋酸、三氟乙酸、三氯乙酸或檸檬酸之水溶液。
- 如申請專利範圍第1項之處理奈米多孔低介電係數介電材料的方法,其中該觸媒係為一有機酸,該方法更包含在步驟(a)之後及步驟(b)及/或(c)之前自於步驟(a)中取得之該奈米多孔低介電係數介電材料移除該處於氣相之有機酸,以防止在:(i)該有機酸及(ii)該烷氧矽烷修復劑及/或烷氧矽烷密封劑之間的氣相反應。
- 如申請專利範圍第5項之處理奈米多孔低介電係數介電材料的方法,其中該烷氧矽烷修復劑係甲基三甲氧基矽烷(CH3 -Si-(O-CH3 )3 )、二甲氧基二甲基矽烷((CH3 )2 -Si-(OCH3 )2 )、甲氧基三甲基矽烷((CH3 )3 -Si-OCH3 )或正丙基三甲氧基矽烷(CH3 -CH2 -CH2 -Si-(OCH3 )3 或n-PTMS);及該烷氧矽烷密封劑係雙(二甲氧甲基)矽氧烷、雙(甲基二甲氧矽丙基)-N-甲基胺、雙(三乙氧矽)乙烷、1,2-雙(三甲氧矽)己烷、雙(三甲氧矽丙基)胺或雙(3-(三乙氧矽)丙基)-二硫化物。
- 如申請專利範圍第1項之處理奈米多孔低介電係數介電材料的方法,其中(a)使該奈米多孔低介電係數介電材料與該觸媒接觸之步驟包含:將該半導體基板放置於一處理室中,且排空該處理室;將該半導體基板加熱至約60℃至約275℃之第一溫度;在約20Torr至約1500Torr的壓力下,將該觸媒通入該處理室持續約10秒至約60秒的時間;及排空該處理室。
- 如申請專利範圍第7項之處理奈米多孔低介電係數介電材料的方法,其中該第一溫度係約100℃至約200℃,該壓力係約100Torr 至約760Torr,及該時間係約20秒至約30秒。
- 如申請專利範圍第7項之處理奈米多孔低介電係數介電材料的方法,其中(b)使於步驟(a)中取得之該奈米多孔低介電係數介電材料與該烷氧矽烷修復劑接觸及/或(c)使於步驟(a)中取得之該奈米多孔低介電係數介電材料與該烷氧矽烷密封劑接觸之步驟包含:將該半導體基板加熱至約60℃至約275℃之第一溫度;在約20Torr至約1500Torr的壓力下,將該烷氧矽烷修復劑或該烷氧矽烷密封劑通入該處理室計持續10秒至約180秒的時間;及排空該處理室。
- 如申請專利範圍第9項之處理奈米多孔低介電係數介電材料的方法,其中該第一溫度係約100℃至約200℃,該壓力係約100Torr至約760Torr,且該時間係約20秒至約60秒。
- 如申請專利範圍第9項之處理奈米多孔低介電係數介電材料的方法,其中(b)使於步驟(a)中取得之該奈米多孔低介電係數介電材料與該烷氧矽烷修復劑接觸及/或(c)使於步驟(a)中取得之該奈米多孔低介電係數介電材料與該烷氧矽烷密封劑接觸之步驟更包含:在排空該處理室之前,將該半導體基板加熱至約80℃至約300℃之第二溫度持續約10秒至約180秒之額外時間;及在排空該處理室之後,將該半導體基板維持在該第二溫度持續約10秒至約180秒。
- 如申請專利範圍第11項之處理奈米多孔低介電係數介電材料的方法,其中該第二溫度係約150℃至約250℃,且該額外時間係約20秒至約60秒。
- 如申請專利範圍第7項之處理奈米多孔低介電係數介電材料的方法,更包含:(d)使於步驟(b)或(c)中取得之該奈米多孔低介電係數介電材料與處於氣相之一有機酸觸媒接觸,該有機酸觸媒的量係足以水平網狀連接該烷氧矽烷修復劑及/或密封劑;以及(e)將於步驟(d)中取得之該奈米多孔低介電係數介電材料加熱至一足以水平網狀連接該烷氧矽烷修復劑及/或該烷氧矽烷密封劑之溫度。
- 如申請專利範圍第13項之處理奈米多孔低介電係數介電材料的方法,其中(d)使於步驟(b)或(c)中取得之該奈米多孔低介電係數介電材料與處於氣相之一有機酸觸媒接觸,該有機酸觸媒的量係足以水平網狀連接該烷氧矽烷修復劑及/或該烷氧矽烷密封劑之步驟包含:將該半導體基板加熱至約60℃至約275℃之第一溫度;在約20Torr至約1500Torr的壓力下,將該有機酸氣相觸媒通入該處理室持續約10秒至約60秒的時間;及排空該處理室。
- 如申請專利範圍第13項之處理奈米多孔低介電係數介電材料的方法,其中(e)將於步驟(d)中取得之該奈米多孔低介電係數介電材料加熱至一足以水平網狀連接該烷氧矽烷修復劑及/或該烷氧矽烷密封劑之溫度的步驟包含:將該半導體基板在處理室中加熱至一約200℃至約300℃之溫度持續約60秒至約180秒;或自該處理室中移出該半導體基板,並將該半導體基板置於一加熱板上,且將該半導體基板加熱至一約200℃至約300℃之溫度持續約60秒至約180秒。
- 一種處理奈米多孔低介電係數介電材料的方法,該奈米多孔低介電係數介電材料係形成在半導體基板上,該奈米多孔低介電係數介電材料包含具有蝕刻損傷區域之蝕刻開口,該蝕刻損傷區域在該蝕刻開口之外表面及互連孔之內表面上含有矽醇基,該方法包含:(a)使該奈米多孔低介電係數介電材料與處於氣相之一有機酸觸媒接觸,該有機酸觸媒的量係足以使在該蝕刻損傷區域中之該有機酸觸媒及該矽醇基之間形成氫鍵,而形成一觸媒中間物,接著進行以下步驟(b)及(c)其中至少一者:(b)使於步驟(a)中取得之該奈米多孔低介電係數介電材料與處於氣相之一烷氧矽烷修復劑接觸,該烷氧矽烷修復劑的量係足以與在該蝕刻損傷區域中約50%或更多之該矽醇基反應,俾使該烷氧矽烷修復劑與該觸媒中間物反應;(c)使該低介電係數介電材料與處於氣相之一烷氧矽烷密封劑接觸,該烷氧矽烷密封劑的量係足以防止一上覆之阻隔層擴散進入該互連孔,俾使該烷氧矽烷密封劑與該觸媒中間物反應。
- 如申請專利範圍第16項之處理奈米多孔低介電係數介電材料的方法,其中該有機酸觸媒係醋酸、三氟乙酸、三氯乙酸或檸檬酸之水溶液。
- 如申請專利範圍第16項之處理奈米多孔低介電係數介電材料的方法,其中該烷氧矽烷修復劑係甲基三甲氧基矽烷(CH3 -Si-(O-CH3 )3 )、二甲氧基二甲基矽烷((CH3 )2 -Si-(OCH3 )2 )、甲氧基三甲基矽烷((CH3 )3 -Si-OCH3 )或正丙基三甲氧基矽烷(CH3 -CH2 -CH2 -Si-(OCH3 )3 或n-PTMS);及該烷氧矽烷密封劑係雙(二甲氧基甲基)矽氧烷、雙(甲基二甲氧矽丙基)-N-甲基胺、雙(三乙氧矽)乙烷、1,2-雙(三甲氧矽)己烷、雙(三甲氧矽丙基)胺或雙(3-(三乙氧矽)丙基)-二硫化物。
- 如申請專利範圍第16項之處理奈米多孔低介電係數介電材料的方法,其中(a)使該奈米多孔低介電係數介電材料與該有機酸觸媒接觸之步驟包含:將該半導體基板放置於一處理室中且排空該處理室;將該半導體基板加熱至約60℃至約275℃之第一溫度;在約20Torr至約1500Torr的壓力下,將該有機酸觸媒通入該處理室持續約10秒至約60秒的時間;及排空該處理室。
- 如申請專利範圍第16項之處理奈米多孔低介電係數介電材料的方法,更包含:(d)使於步驟(b)或(c)中取得之該奈米多孔低介電係數介電材料與處於氣相之一有機酸觸媒接觸,該有機酸觸媒的量係足以水平網狀連接該烷氧矽烷修復劑及/或該烷氧矽烷密封劑;以及(e)將於步驟(d)中取得之該奈米多孔低介電係數介電材料加熱至一足以水平網狀連接該烷氧矽烷修復劑及/或該烷氧矽烷密封劑之溫度。
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US7678712B2 (en) * | 2005-03-22 | 2010-03-16 | Honeywell International, Inc. | Vapor phase treatment of dielectric materials |
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- 2008-12-08 KR KR1020107015900A patent/KR101542636B1/ko active IP Right Grant
- 2008-12-08 JP JP2010539431A patent/JP5449189B2/ja active Active
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- 2008-12-08 WO PCT/US2008/013471 patent/WO2009085098A1/en active Application Filing
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US6455130B1 (en) * | 1997-04-17 | 2002-09-24 | Alliedsignal Inc. | Nanoporous dielectric films with graded density and process for making such films |
TW525268B (en) * | 1998-03-25 | 2003-03-21 | Honeywell Int Inc | Nanoporous dielectric films with graded density and process for making such films |
TW514653B (en) * | 2000-05-05 | 2002-12-21 | Honeywell Int Inc | Simplified method to produce nanoporous silicon-based films |
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CN102089861B (zh) | 2013-03-27 |
KR101542636B1 (ko) | 2015-08-06 |
WO2009085098A1 (en) | 2009-07-09 |
CN102089861A (zh) | 2011-06-08 |
US20110020955A1 (en) | 2011-01-27 |
US7998875B2 (en) | 2011-08-16 |
TW200943417A (en) | 2009-10-16 |
JP5449189B2 (ja) | 2014-03-19 |
JP2011508420A (ja) | 2011-03-10 |
KR20100100976A (ko) | 2010-09-15 |
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