TWI496212B - 包含光阻遮罩預處理之電漿製程 - Google Patents

包含光阻遮罩預處理之電漿製程 Download PDF

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TWI496212B
TWI496212B TW098115837A TW98115837A TWI496212B TW I496212 B TWI496212 B TW I496212B TW 098115837 A TW098115837 A TW 098115837A TW 98115837 A TW98115837 A TW 98115837A TW I496212 B TWI496212 B TW I496212B
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mask
feature
dielectric layer
deposition
photoresist
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TW200952071A (en
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Dongho Heo
Ji Soo Kim
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Lam Res Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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Description

包含光阻遮罩預處理之電漿製程
本發明係關於半導體元件之形成。具體而言，本發明係關於透過光阻(PR)遮罩在蝕刻層蝕刻特徵部而形成半導體元件。
在半導體晶圓處理期間，利用熟知的圖案化製程及蝕刻製程將半導體元件之特徵部定義於晶圓上。在這些製程中，將光阻(PR,photoresist)材料沉積於晶圓上，接著將其暴露於由初縮遮罩所過濾之光源下。此初縮遮罩可為以阻擋光透射通過初縮遮罩之例示性特徵部幾何形狀加以圖案化的玻璃平板。
當光通過初縮遮罩後，光將接觸光阻材料之表面。光會改變光阻材料之化學組成，使顯影劑可移除部分的光阻材料。就正光阻材料而言，曝光區域將被移除；而就負光阻材料而言，未曝光區域將被移除。之後，晶圓受到蝕刻，以從不再受光阻材料保護之區域移除下層材料，從而於晶圓上定義期望之特徵部。
波長為193 nm之氟化氬(ArF)準分子雷射已被用來製造最高級別的積體電路，如次0.04 μm元件。結合浸潤式微影技術(ArF微影技術)之上述技術能使製程低於110 nm節點。因為圖案化影像之聚焦深度(景深)限制，如此小的電路特徵部需要更高的解析度及更薄的光阻。例如，某些DRAM製程(如Bitline)之ArF微影製程使用厚度低於100 nm之薄光阻，光阻材料亦較軟且較弱，在電漿製程期間，設置圖案化光阻遮罩後，如此薄弱之光阻遮罩會輕易且非期望地被蝕刻或受損害。
為實現上述且依據本發明之目的，提供一種透過光阻(PR)遮罩在介電層蝕刻特徵部的方法。利用波長不超過193 nm之雷射光，將光阻遮罩加以圖案化。利用惰性氣體電漿，將PR遮罩預處理，接著提供複數循環之電漿製程，每個循環包含：沉積階段， 於PR遮罩上方沉積一沉積層，該沉積層覆蓋PR遮罩之遮罩特徵部之頂部及側壁；及成形階段，將沉積於PR遮罩上方之沉積層加以塑形。
在本發明之實施樣態中，惰性氣體可包含Ar。PR遮罩之預處理可包含：提供惰性氣體、從惰性氣體形成電漿、及停止惰性氣體流。在電漿形成期間，可提供60 MHz或更高之高頻。在本發明之實施樣態中，電漿形成並不提供頻率低於50 MHz之RF能量。
在本發明之另一實施形式中，提供一種透過光阻(PR)遮罩在介電層蝕刻特徵部的設備。利用波長不超過193 nm之雷射光，將光阻遮罩加以圖案化。該設備包含一電漿處理室，該電漿處理室包含：一室壁，形成電漿處理室之外殼；一基板支座，支持在電漿處理室之外殼內之一基板；一壓力調節器，用以調節電漿處理室之外殼內的壓力；至少一電極，用以提供電力至電漿處理室之外殼以維持一電漿；一氣體入口，用以提供氣體至電漿處理室之外殼；一氣體出口，用以從電漿處理室之外殼排出氣體。該設備更包含一氣體源，與該氣體入口流體連通，該氣體源包含一蝕刻氣體源、一沉積階段氣體源、一成形階段氣體源、及一預處理氣體源。一控制器以可控制之方式連結至氣體源以及至少一電極，該控制器包含至少一處理器及電腦可讀媒體，電腦可讀媒體包含：(a)利用惰性氣體電漿將PR遮罩預處理之電腦可讀碼，其包含從預處理氣體源提供惰性氣體之電腦可讀碼、從惰性氣體形成電漿之電腦可讀碼、及停止惰性氣體流之電腦可讀碼；及(b)提供複數循環之電腦可讀碼，每個循環包含一沉積階段及一成形階段。該電腦可讀碼(b)包含：從沉積階段氣體源提供沉積階段氣體之電腦可讀碼；從沉積階段氣體形成電漿之電腦可讀碼，俾能於PR遮罩上方沉積一沉積層，該沉積層覆蓋PR遮罩之遮罩特徵部之頂部及側壁；停止沉積階段氣體流之電腦可讀碼；從成形階段氣體源提供成形階段氣體之電腦可讀碼；從成形階段氣體源形成電漿之電腦可讀碼，俾能將沉積於PR遮罩上方之沉積層加以塑形；及停止成形階段氣體流之電腦可讀碼。
以下將在本發明之詳細說明連同附圖中，對本發明之上述及其他特徵詳加說明。
本發明現在將參照一些較佳的實施例及舉例性附圖詳細地敘述。為了要提供本發明之全面性的了解，許多的具體的細節會在接下來的敘述中提出。然而對熟悉本技藝者，本發明在沒有這些具體細節的情況下仍可實施。在其他情況下，為了避免不必要地混淆本發明，熟知的製程步驟及/或結構並未詳細地描述。
為了幫助了解，圖1為依據本發明之實施例之包含光阻遮罩預處理之電漿製程的高階流程圖。圖案化之光阻遮罩係設置於蝕刻層上方(步驟102)。
圖2A為依據本發明之實施例加工之堆疊200範例的橫剖面圖。堆疊200包含形成於阻障層212上方的蝕刻層220，阻障層係形成於晶圓210之上。在此例子中，層208係配置於阻障層212及晶圓210之間，雖然顯示層208形成於晶圓210上，可有任何數量之層形成於蝕刻層220與晶圓210之間。在此例子中，阻障層212可為碳化矽(SiC)層，或者其亦可為SiN。蝕刻層220可為low-k介電質(如有機矽酸鹽介電質及多孔介電質)，包含：來自加州聖荷西(San Jose)之Novellus的CORALTM ；來自加州聖克拉拉(Santa Clara)之Applied Materials的Black DiamondTM ；可從荷蘭之ASM International N.V.得到的AuroraTM ；可從加州聖克拉拉之Sumitomo Chemical America,Inc.得到的Sumika Film® ；來自新澤西(New Jersey)之Allied Signal of Morristown的HOSPTM ；來自DOW Chemical Company的SiLKTM 或先進多孔SiLK；來自Trikon的Orion® FlowfillTM ；及來自JSR公司的LKDTM 。
遮罩特徵部224之生成可藉由在蝕刻層220上方形成抗反射層(ARL,anti-reflective layer)216來執行，可藉由旋塗式沉積來形成ARL 216，光阻遮罩232係設置於ARL 216上方(步驟102)。藉由將光阻層曝光於圖案化光源，接著將光阻層232顯影以將光阻遮 罩232加以圖案化，而在光阻層得到遮罩特徵部224。最好利用與浸潤式微影技術結合之ArF(193 nm)光阻來形成PR遮罩(ArF微影技術)。ArF PR適合於製造最高級別的積體電路，如次0.04 μm元件。更一般言之，可利用波長不超過193 nm之雷射光將PR遮罩232加以圖案化。
由於ArF PR遮罩為薄弱，隨後的電漿製程一般會使用具有低離子能量的高密度電漿，以避免PR遮罩之損害或擺動。典型地，申請人使用能夠控制PR遮罩之形狀及/或輪廓的多循環兩階段電漿製程。然而，在上述之高密度低能量的電漿中，許多低能量離子轟擊PR遮罩俾能增加PR材料中溶劑之排氣，其導致PR遮罩之『起泡作用(blistering)』(剝落(pealing-off))。一般認為起泡的PR遮罩易於在電漿製程期間釋放PR材料(微粒)於電漿內，污染晶圓及最終的積體電路。在使用193 nm ArF PR之電漿蝕刻製程中的污染微粒問題及非期望微粒之來源已被研究多時，而申請人終於發現PR遮罩之起泡作用為微粒問題之主因。申請人亦發現在某些條件下利用惰性氣體電漿將PR遮罩預先處理，意外地降低隨後之電漿製程中之PR遮罩之起泡作用。
因此，依據本發明之實施例，為了縮減起泡作用及最終的微粒問題，在堆疊200繼續進行多循環電漿製程(步驟106)之前，利用惰性氣體電漿預先處理PR遮罩232(步驟104)，如圖1所示。惰性氣體最好為純氬(Ar)，但亦可使用氦(He)、氙(Xe)或其他惰性氣體。
在預處理之後(步驟104)執行多循環電漿製程(步驟106)，最好在相同的電漿腔室中。多循環電漿製程(步驟106)提供複數之循環，每個循環包含沉積階段108及成形階段110。沉積階段108在PR遮罩上方沉積一沉積層，沉積層至少覆蓋PR遮罩之遮罩特徵部的頂部及側壁。成形階段110將沉積於PR遮罩上方的沉積層加以塑形。在多循環電漿製程106之後，可執行額外的蝕刻製程(步驟112)，且可利用任何剝除或灰化製程來去除PR遮罩(步驟114)。
在顯示於圖2B-2D之本發明之實施例中，藉由多循環電漿製 程106在蝕刻層220選擇性地蝕刻特徵部234。圖3A概要地闡明此例之多循環電漿製程(選擇性蝕刻製程106a)。如圖3A所示，沉積階段108為沉積-蝕刻階段108a，其對於PR遮罩232選擇性地將蝕刻層220加以蝕刻，且將沉積層(聚合物)沉積在PR遮罩232上方以及被蝕刻之特徵部234之側壁上。圖2B概要地闡明沉積-蝕刻階段108a之後之堆疊200的橫剖面圖。可能已執行一個以上的蝕刻循環以得到顯示於圖2B之結構。沉積-蝕刻階段108a蝕刻特徵部234之一部分，同時在被蝕刻之特徵部234之側壁上以及光阻遮罩232上沉積聚合物層236。上述之沉積-蝕刻階段最好提供無限的選擇性，由於上述階段將蝕刻層220加以蝕刻而不蝕刻光阻遮罩232，反而在光阻遮罩232上形成聚合物層236。
在此例子中，如圖3A所示，成形階段110為移除被沉積的聚合物236之聚合物清潔階段110a。圖2C為聚合物清潔階段110a之後的堆疊200之橫剖面圖。可能已執行一個以上的兩階段製程循環以得到顯示於圖2C之結構。聚合物清理階段110a將被蝕刻之特徵部234之側壁上及遮罩特徵部224上的沉積聚合物236移除。在較佳的實施例中，聚合物清潔階段110a期間並不將蝕刻層220加以蝕刻。在其他的實施例中，聚合物清潔階段110a可在特徵部234之底部將蝕刻層220加以蝕刻。
多循環電漿製程106a最好執行10~100次循環；多循環電漿製程106a執行15~50次循環為較佳；多循環電漿製程執行約20次循環為最佳。
圖2D為完成選擇性蝕刻製程(步驟106a)之後之堆疊200的橫剖面圖。在此例子中，特徵部234穿過蝕刻層220而被完全蝕刻。光阻遮罩232未被蝕刻，提供無限的選擇性。
接著剝除光阻遮罩232(圖1，步驟114)。
被蝕刻之特徵部234之側壁最好為垂直。垂直的側壁最好從底部至頂部與特徵部底部形成88o ~90o 之間的角度。應注意沒有聚合物清潔階段(步驟110a)，則連續的沉積-蝕刻階段108a會繼續添加更多聚合物於特徵部234之側壁上。因此，特徵部之寬度會減 少而產生錐形而非垂直的側壁。上述製程會導致停止蝕刻，其會限制蝕刻之深度。
蝕刻層220最好為介電層；蝕刻層為low-k介電層為較佳。介電層可為low-k矽氧化物基介電層。在本發明之較佳實施例中，基板210為矽晶圓且介電蝕刻層220為有機矽酸鹽玻璃(OSG,organosilicate glass)或Coral。在較佳的實施例中，阻障層212含有SiC。利用ArF(193 nm PR)光阻來形成遮罩(步驟104)。在較佳實施例中，ARC層為底部抗反射塗層(BARC,bottom antireflective coating)。
圖4為依據本發明一實施例的電漿處理室400之示意圖，該電漿處理室400可用來進行蝕刻與剝除。電漿處理室400包含：限制環402、上電極404、下電極408、氣體源410、及排氣泵420。氣體源410可包含蝕刻氣體源412、沉積階段氣體源414、成形階段氣體源416、及預處理氣體源418。於電漿處理室400之內，將基板210置於下電極408上。下電極408包含用以夾住基板210之合適基板夾頭機構(如靜電、機械式夾頭等)。反應器蓋428包含設置於下電極408正對面之上電極404。上電極404、下電極408、及限制環402定義受限之電漿容積440。經由氣體源410供給氣體至此受限之電漿容積440，並經由排氣泵420將氣體由此受限之電漿容積440通過限制環402與排氣口而排出。第一RF電源444與上電極404電性相連，第二RF電源448與下電極408電性相連。室壁452包圍限制環402、上電極404及下電極408。第一RF電源444與第二RF電源448兩者皆可包含27 MHz之電源、60 MHz之電源、及2 MHz之電源。例如，LAM Research Corporation之介電質蝕刻系統(如由位於加州佛利蒙(Fremont)之LAM Research CorporationTM 所製造的Exelan®系列可用在本發明之較佳實施例中。連結RF功率與電極之不同組合皆有可能。在本發明之較佳實施例中，僅60 MHz之電源用來預處理作為連結至下電極的第二RF電源448，而上電極係為接地。控制器435以可控制之方式連結至RF電源444及448、排氣泵420、及氣體源410。上述之裝 置能夠調節腔室壓力、氣流、氣體組合、RF電源、及每個階段之持續時間。
圖5A及5B說明一電腦系統500，其適合用來執行於本發明之實施例中所使用的控制器435。圖5A顯示電腦系統可能的實體形式。當然，電腦系統可能有許多種實體形式，範圍從積體電路、印刷電路板、小型手提裝置上至龐大的超級電腦。電腦系統500包含螢幕502、顯示器504、機殼506、磁碟機508、鍵盤510及滑鼠512。磁碟514為電腦可讀媒體，用來傳送資料來回電腦系統500。
圖5B為一個電腦系統500的方塊圖範例。附屬在系統匯流排520上者為各種子系統。處理器522(也稱為中央處理單元或CPU)與包含記憶體524之儲存裝置相連接。記憶體524包含隨機存取記憶體(RAM,read access memory)及唯讀記憶體(ROM,read only memory)。如同技術中所熟知者，ROM單向地傳輸資料與指令至CPU，而RAM一般以雙向方式傳輸資料與指令。這兩種型態的記憶體可以包含任何以下所描述的適當電腦可讀媒體。固定式磁碟526也雙向地連接在CPU 522上；它提供額外的資料儲存能力並包含任何以下所描述的電腦可讀媒體。固定式磁碟526可用來儲存程式、資料等，一般為比主要儲存媒體更慢速之輔助儲存媒體(例如硬碟)。應了解：在適當的情況中，保留在固定式磁碟526內的資訊可用標準方式被併入記憶體524中作為虛擬記憶體。卸除式磁碟514可採取以下所描述的電腦可讀媒體之形式。
亦將CPU 522連接至各種輸入/輸出裝置，如顯示器504、鍵盤510、滑鼠512及揚聲器530。一般而言，輸入/輸出裝置可為下列任一：視訊顯示器、軌跡球、滑鼠，鍵盤，麥克風，觸摸式顯示器、轉換讀卡機、讀磁帶或紙帶機、輸入板、尖筆、聲音或手寫辨識器、生物讀取機或其他電腦。CPU 522也可選擇性地使用網路介面540連接至另一電腦或電信網路。利用此一網路介面，預期CPU在執行上述方法步驟的過程中，可從網路接收資訊或輸出資訊到網路。再者，本發明的方法實施例可單獨在CPU 522上 執行，或透過例如結合分享部分處理之遠端CPU之網際網路來執行。
此外，本發明的實施例進一步與有電腦可讀媒體之電腦儲存產品相關，該電腦可讀媒體上具有用以執行各種電腦執行運算之電腦碼。媒體與電腦碼可為本發明之用途所特別設計及建構，或對精於電腦軟體技術之人士而言，它們乃為熟知且可用。實體的電腦可讀媒體之例子包含但不限於：磁性媒體，如硬碟、磁片及磁帶；光學媒體，如唯讀光碟(CD-ROM,compact disc read only memory)及全像裝置；磁光媒體，如軟磁光碟；及專用於儲存與執行程式碼之硬體裝置，如專用積體電路(ASIC,application-specific integrated circuit)；可程式化邏輯元件(PLD,programmable logic device)；及ROM與RAM裝置。電腦碼的例子包含機械碼(如由編譯器所產生者)及包含利用譯碼器而由電腦所執行之較高階碼的檔案。電腦可讀媒體也可為經由實現在載波上的電腦資料信號加以傳送且表示一連串可由處理器來執行之指令的電腦碼。
圖6概要地闡明PR遮罩之預處理(步驟104)之詳細處理流程。典型地，具有圖案化PR遮罩於其上之層之堆疊的基板210係置於電漿處理室中(步驟132)，如上述之電漿處理室400。提供惰性氣體(步驟134)，自惰性氣體形成電漿(步驟136)以處理PR遮罩，接著停止惰性氣體流(步驟138)。藉由變更處理氣體及其他電漿條件參數，可執行隨後的多循環電漿製程而不撲滅電漿。
最好提供具有低離子能量之高密度電漿，以使PR遮罩在預處理期間不被蝕刻或損害，但PR遮罩被一些低能量離子『輕拍(tapped)』以使軟或片狀之PR遮罩更硬且具有更結實的結構。預處理氣體最好含Ar；預處理氣體僅含Ar為較佳。例如，100~1000 sccm Ar氣體，最好是700 sccm Ar氣體可被提供。或者，預處理氣體可含Ar、He、及/或Xe、或其混合物。
自預處理氣體形成電漿期間(步驟136)，可在功率範圍100~500 W提供60 MHz以上之高頻，功率最好設定在300 W。電漿形成步驟136不提供頻率低於50 MHz的RF能量。當離子能量 無法被直接控制時，300 W之功率範圍及60 MHz以上之高頻確保夠低的離子能量。電漿腔室可被設定在100 mTorr或更大；壓力最好設定在約200 mTorr。
一般認為以低能量惰性氣體離子輕拍PR遮罩之頂部，以按壓並使PR遮罩變堅固。上述引起物理反應，即藉由壓擠而物理地改變PR遮罩材料之性質以使之變堅固，但不引起化學反應。藉由堅固及/或按壓PR遮罩來降低PR遮罩之起泡作用，俾能避免隨後之多循環電漿製程中的微粒污染。
應注意已提出在矽蝕刻製程前於193 nm PR上使用Ar電漿預處理，以在主要的矽蝕刻製程後降低被蝕刻之特徵部的線寬粗糙度(LWR,line width roughness)或線邊緣粗糙度(LER,line edge roughness)。預被蝕刻之堆疊包含Si基板、SiO2 硬質遮罩、底部抗反射塗層(BARC)、及PR。然而，在特定的多循環兩階段蝕刻製程期間，利用高密度低能量電漿之Ar電漿預處理僅控制PR遮罩及/或被蝕刻之矽特徵部的形狀，並非解決關於微粒污染之問題。
如上所述，多循環選擇性蝕刻製程包含複數之循環，每個循環包含沉積階段(步驟108)及成形階段(步驟110)。依據本發明之實施例，沉積階段並不提供頻率低於50 MHz之RF能量；沉積階段最好提供60 MHz以上之高頻。相同地，依據本發明之實施例，成形階段並不提供頻率低於50 MHz之RF能量；成形階段最好提供60 MHz以上之高頻。
如圖3A所示，此例中之多循環電漿製程106藉由多循環電漿製程106a而選擇性地在蝕刻層220蝕刻特徵部。沉積階段108為沉積-蝕刻階段108a，其對於PR遮罩選擇性地將蝕刻層加以蝕刻，且將聚合物(沉積層)沉積在被蝕刻之特徵部之側壁上以及PR遮罩上方。成形階段110為移除被沉積之聚合物的聚合物清潔階段110a。
在上述之選擇性-蝕刻製程106a中，沉積-蝕刻階段(步驟108a)之範例製程配方如下：提供具有40 sccm之CF4 及90 sccm之H2 的沉積-蝕刻階段氣體，腔室壓力設定為90 mTorr，由27 MHz之 RF電源提供1200 W而由2 MHz之RF電源提供400 W。在此例子中，同時進行沉積-蝕刻如一單一步驟。聚合物清潔階段(步驟110a)之範例製程配方如下：提供具有300 sccm之O2 的聚合物清潔階段氣體，腔室壓力設定為250 mTorr，由27 MHz之RF電源提供100 W，而無功率由2 MHz之RF電源提供。
接著剝除PR遮罩(步驟114，圖1)。遮罩剝除之例提供具有10~3000 sccm之O2 的剝除氣體，腔室壓力設定為5~500 mTorr，由2 MHz、27 MHz之RF電源或2 MHz及27 MHz之RF電源之組合提供100~1000 W。
圖3B概要地闡明多循環電漿製程106b之另一例，於其中PR遮罩之臨界尺寸(CD)被縮減。在此例子中，如圖7A所示，沉積階段108b於遮罩特徵部314之底部332上及PR遮罩312上方更沉積一沉積層302。成形階段110為輪廓成形階段110b，自遮罩特徵部之底部332移除沉積層302且留下側壁304而不蝕刻下層介電層，俾能縮減PR遮罩312之CD，如圖7B所示。重複兩階段循環，如圖7C及7D所示，直到得到遮罩特徵部314之期望CD，接著利用被塑形的PR遮罩312將介電層加以蝕刻，被塑形的PR遮罩具有藉由提供複數之循環而被縮減之CD(圖1，步驟112)。在蝕刻製程之後可剝除PR遮罩312(步驟114)。
沉積階段108b之例子可為CF4 沉積作用：其在70 mTorr之壓力下(由設定渦輪泵之Vat閥到1000所建立)利用60 sccm之Ar、75 sccm之CF4 、及100 sccm之H2 的化學物；60 MHz之RF電源提供200-800瓦的功率；此階段維持約12秒。成形階段110b之例子可在25 mTorr之壓力下(由設定渦輪泵之Vat閥到1000所建立)利用87 sccm之CF4 的化學物；60 MHz之RF電源提供200-800瓦的功率；此階段維持約3秒。執行八次循環之利用沉積階段108b接著利用成形階段110b的循環製程。
控制沉積階段108b及輪廓成形階段110b之次數比率的能力乃提供另一個控制變數。合適的比率將提供本質為垂直及保角之側壁。上述之沉積層亦能保護光阻遮罩以增加蝕刻選擇性。其他 能被用來控制沉積輪廓之由本發明提供的控制參數為：循環數目、整體沉積時間、沉積/輪廓成形時間比、氣體化學物比率(如CF4 /H2 )。可使用其他氣體化學物，如C4 F6 /O2 或CH3 F/N2 代替CF4 /H2 、CH3 F/O2 或CH3 F/N2 代替CF4 等等。
圖3C概要地闡明多循環電漿製程106c之另一例子，於其中PR遮罩被削減。在此例子中，沉積階段108c於遮罩特徵部之底部上及PR遮罩上方更沉積一沉積層。成形階段110為削減-蝕刻階段110c，自遮罩特徵部之底部及側壁移除沉積層而不蝕刻介電層，俾能削減遮罩特徵部之側壁。
圖8A-8D概要地闡明每個循環之遮罩特徵部314的橫剖面圖。如圖8A所示，圖案化遮罩312形成於介電層上。典型地，ARL 310設置於介電層之頂部且暴露於遮罩特徵部314之底部332。在這個例子中，如圖8B所示，沉積階段108c於遮罩特徵部314之底部332及PR遮罩312上方更沉積一沉積層330；即沉積層330覆蓋遮罩特徵部314之底部332及遮罩特徵部314之側壁315。沉積層可為一聚合物。在每個沉積階段108c中，一般而言，沉積在遮罩312之頂部之沉積層330的厚度及沉積在遮罩特徵部之底部332之沉積層330的厚度，大於沉積在遮罩特徵部之側壁315之沉積層的厚度。
如圖8C所示，削減-蝕刻階段110c自遮罩特徵部之底部332及側壁315移除沉積層330而不蝕刻介電層，俾能削減遮罩特徵部之側壁。遮罩312之頂部334上的沉積層330大體上在削減-蝕刻階段110c被移除。由於沉積層330在側壁上比在遮罩之頂部上及遮罩特徵部之底部上來的薄，從側壁移除沉積層330之後，側壁沉積物被過度蝕刻至遮罩特徵部之側壁內。對於遮罩之頂部及遮罩特徵部之底部，削減-蝕刻階段最好僅移除前一沉積階段所沉積之沉積層(使之平坦)，而不蝕刻遮罩312或ARL 310。藉由控制兩階段，遮罩特徵部之側壁315被削減以擴大其CD，且在每個循環中大體上維持遮罩312之厚度。
圖8D概要地闡明遮罩削減製程之複數循環後之遮罩特徵部 314的橫剖面圖。藉由重複沉積階段108c及削減-蝕刻階段110c，遮罩特徵部之側壁315逐漸被削減成期望的輪廓。削減-蝕刻階段110c最好在孤立區域選擇性地回蝕遮罩特徵部之側壁315(相對於遮罩特徵部之密集區域)。因此，在孤立區域，遮罩特徵部之側壁被削減，且在密集區域遮罩特徵部大體上可維持原本的形狀。
應注意重複複數之循環(在每個循環中沉積薄沉積層及削減微量側壁)(多循環製程)優於一次沉積厚沉積層及削減大量之側壁。首先，多循環製程提供較佳的輪廓調整。沉積厚聚合物層之單一長沉積步驟易產生稱為『麵包塊(bread-loaf)』之輪廓，在極端情況下，特徵部甚至可能被夾止(be pinched off)。另一方面，單一長蝕刻步驟會產生琢面輪廓。包含交替之沉積步驟及蝕刻步驟的複數循環提供具有最小或沒有麵包塊之較佳輪廓控制及較直的側壁。此外，聚合物層變成緻密、縮減之層化作用(delamination)、條狀、或起泡狀(剝落(peeling-off))。例如，超過1000之厚沉積層易從遮罩剝除，特別在遮罩特徵部之邊緣。此外，應注意由於設計法則之要求，並不期望或實際去變更原始遮罩之CD。
可添加額外的階段至每個循環中。多循環遮罩削減製程最好包含至少三個循環；該遮罩削減製程包含四到五個循環為較佳。
依據本發明之實施例，沉積階段(步驟108c)使用包含碳氫化合物成分之沉積氣體；沉積氣體最好包含C2 H4 ；沉積氣體更包含載氣(如N2 )為較佳。削減-蝕刻階段(步驟110c)使用含氧之蝕刻氣體。
沉積階段中(步驟108c)之範例沉積氣體提供具有100-500 sccm之C2 H4 、100-500 sccm之N2 、及10-200 sccm之Ar的調整氣體流。Ar調整氣體可選擇性地提供至晶圓的邊緣部份，以控制沉積製程之均勻性，因為沉積階段在晶圓邊緣之沉積通常比中央之沉積多。壓力被設定在350-750 mTorr。基板溫度維持在0-60℃，例如，約在20℃。第二RF電源提供200-400瓦(頻率為60 MHz)。在另一例子中，沉積階段提供腔室具有500 sccm之C2 H4 、150 sccm之N2 、及150 sccm之Ar的調整氣體流，740 mTorr之壓力及200 瓦或400瓦之功率(頻率為60 MHz)。
削減-蝕刻階段(步驟110c)之範例提供100-1000 sccm之O2 。在此例子中，O2 為選擇性蝕刻階段提供之唯一氣體(不提供調整氣體)。O2 調整氣體可用於削減-蝕刻階段，且其能依據製程及化學物而被提供於邊緣或中央部份。提供350-750 mTorr之壓力至腔室。第二RF電源提供200-400瓦(頻率為60 MHz)。例如，依據本發明之實施例，削減-蝕刻階段提供腔室750 sccm之氧氣流、740 mTorr之壓力及200瓦之功率(頻率為60 MHz)。依據本發明之另一較佳實施例，削減-蝕刻階段提供腔室750 sccm之氧氣流、740 mTorr之壓力及400瓦之功率(頻率為60 MHz)。依據本發明之又另一較佳實施例，削減-蝕刻階段提供腔室200 sccm之氧氣流、380 mTorr之壓力及200瓦之功率(頻率為60 MHz)。
回到圖1，在遮罩削減後，透過被削減之遮罩在介電層蝕刻特徵部(步驟112)。接著剝除遮罩312及ARL 310(步驟114)。
圖3D為多循環電漿製程106之又另一例，其削減遮罩亦將形成於遮罩特徵部之底部上的抗反射層(ARL)加以開口。在此例子中，如圖9A所示，圖案化遮罩312形成於介電層上方之ARL 310之上方。典型地，ARL 310包含一有機的BARC 311及一無機的DARC 313。BARC 311暴露於遮罩特徵部之底部332。
在此例子中，成形階段110為削減-蝕刻階段110d，首先在遮罩特徵部314之底部332蝕刻ARL 310且在每個循環中削減PR遮罩312，如圖9B所示，即，在此例子中，削減-蝕刻階段110d之執行先於沉積-蝕刻階段108d。在削減-蝕刻階段110d中，於一循環中ARL 310被部分蝕刻且並非被完全移除。遮罩312之頂部334及遮罩特徵部314之側壁315亦被部分移除，如圖9B所示。接著沉積-蝕刻階段108d在每個循環中將沉積層330沉積於PR遮罩312上方，且在遮罩特徵部314之底部332更蝕刻ARL 310，如圖9C所示。沉積層330覆蓋遮罩特徵部314之頂部334及遮罩特徵部314之側壁315，同時在遮罩特徵部314之底部332更蝕刻ARL 310。遮罩削減及ARL開口製程包含兩個以上之循環，最好 至少三個循環；該製程包含四或十二個循環為更佳；該製程重複六到七個循環為較佳。
依據本發明之實施例，在遮罩312之頂部334上，每個沉積-蝕刻階段108d所沉積之沉積層330的厚度大體上與前一削減-蝕刻階段110d所移除之遮罩的厚度相同，如圖9C所示。即，在每個循環的最後，遮罩312之原始厚度大體上透過沉積層330來維持。然而，關於遮罩特徵部314之側壁，遮罩特徵部314之側壁315上的沉積層330(尤其在孤立區域中)並不足以完全彌補在先前的削減-蝕刻階段110d期間所損失的側壁。因此，如圖9C所示，多循環電漿製程106d縮減遮罩之側壁，且大體上維持遮罩之原始厚度，導致遮罩之淨削減。此外，在遮罩特徵部之底部332的ARL 310於削減-蝕刻階段110d及沉積-蝕刻階段108d持續被蝕刻。因此，如圖9D所示，藉由重複削減-蝕刻階段110d及沉積-蝕刻階段108d，遮罩特徵部314之側壁315逐漸被削減成期望的輪廓，而為了隨後的介電層蝕刻製程，將位於遮罩特徵部314之底部332的ARL 310加以開口。
回到圖1，在多循環電漿製程(步驟106)之削減及開口之後，透過被削減的遮罩及被開口之ARL，將特徵部蝕刻至介電層(步驟112)。剝除PR遮罩(步驟114)。
依據本發明之實施例，削減-蝕刻階段(步驟110d)使用含有NF3 的削減-蝕刻氣體。削減-蝕刻氣體最好更包含一載氣，如N2 及/或Ar。在這個實施例中，沉積-蝕刻階段(步驟118d)使用含有CF4 的沉積-蝕刻氣體，且沉積一聚合物材料作為沉積層。沉積-蝕刻氣體可為CF4 、H2 及Ar之組合，或CF4 、H2 、N2 及Ar之組合。含有NF3 的削減-蝕刻氣體在孤立區域之蝕刻率比密集區域高，俾使孤立區域之遮罩特徵部之側壁之縮減多於密集區域之遮罩特徵部之側壁。沉積層可為包含碳氫化合物的聚合物(主成分為碳氫化合物之聚合物)。
削減-蝕刻階段(步驟110d)之例子提供具有100-500 sccm，最好為300 sccm之NF3 氣流，壓力設定為140 mTorr，基板之溫度維 持在20℃，第二RF電源最好提供400瓦(頻率為60 MHz)。在另一實施例中，第二FR電源可提供100-500瓦(頻率為2 MHz)或100-500瓦(頻率為27 MHz)，取決於晶圓及應用。在一較佳實施例中，NF3 為削減-蝕刻氣體之唯一成分而無任何載氣或調整氣體。在每個削減-蝕刻階段中，在含NF3 之削減-蝕刻氣體被通入腔室之後，從而形成削減-蝕刻電漿，以選擇性地削減遮罩並蝕刻ARL，如上所述。停止削減-蝕刻氣流以使遮罩特徵部之側壁縮減一循環之期望數量。對於一組給定參數(如氣體流速、壓力、及RF電源、及ARL之厚度)而言，被縮減之側壁的數量可藉由削減-蝕刻階段之時間週期來加以控制。
沉積-蝕刻階段(步驟108d)之例子提供：含CF4 之氣體(如20-200 sccm之CF4 及20-200 sccm之H2 作為沉積-蝕刻氣體)，及含20-200 sccm之N2 及/或50-500 sccm之Ar之載氣。沉積-蝕刻氣體最好包含60 sccm之CF4 、70 sccm之H2 、30 sccm之N2 、及具有120 sccm之Ar之載氣。提供40-200 mTorr之壓力，最好是80 mTorr至腔室，第二RF電源提供100-500瓦，最好是400瓦(頻率為60 MHz)。在另一實施例中，第二RF電源可提供100-500瓦(頻率為2 MHz)或100-500瓦(頻率為27 MHz)，取決於晶圓及應用。
在另一實施例中，每個循環更包含額外的沉積及/或輪廓成形階段。在每個沉積-蝕刻階段中，在含CF4 之蝕刻氣體被通入腔室之後，從而形成電漿以沉積一沉積層且更蝕刻ARL，如上所述。停止含CF4 之蝕刻氣流以使沉積層彌補前一削減-蝕刻階段所損失之遮罩厚度。對於一組給定參數(如氣體流速、壓力、及RF電源、及ARL之厚度)而言，循環之淨削減數量可藉由削減-蝕刻階段及沉積-蝕刻階段之時間週期來加以控制。一般而言，削減-蝕刻階段越長，沉積-蝕刻階段越長。藉由控制每個循環之兩階段及循環數目，於削減及開口步驟結束時，移除遮罩特徵部之底部之ARL，且孤立區域之特徵部之側壁被削減以補償隨後之介電層蝕刻之微負載效應。
在這些例子中，電漿處理室應可調整腔室壓力、氣體流量、 氣體組成、RF功率、及每個階段之持續時間。
雖然本發明已參照數個較佳之實施例說明，仍具有於本發明之範疇內之修改、變更及各種替代之等效設計。應注意有許多實施本發明之方法及設備的替代方法。因此隨附之申請專利範圍可解釋為包含所有在本發明之精神及範疇內之修改、變更及各種替代之等效設計。
102‧‧‧於蝕刻層上方設置光阻遮罩
104‧‧‧利用惰性氣體電漿預先處理光阻遮罩
106‧‧‧多循環電漿製程
106a‧‧‧多循環選擇性蝕刻製程
106b‧‧‧多循環CD縮減製程
106c‧‧‧多循環遮罩削減製程
106d‧‧‧多循環遮罩削減及ARL開口製程
108‧‧‧沉積階段
108a‧‧‧沉積-蝕刻階段
108b‧‧‧沉積階段
108c‧‧‧沉積階段
108d‧‧‧沉積-蝕刻階段
110‧‧‧成形階段
110a‧‧‧清潔階段
110b‧‧‧輪廓成形階段
110c‧‧‧削減-蝕刻階段
110d‧‧‧削減-蝕刻階段
112‧‧‧額外的蝕刻製程
114‧‧‧剝除遮罩
132‧‧‧將基板置於處理室中
134‧‧‧提供惰性氣體
136‧‧‧由惰性氣體形成電漿
138‧‧‧停止惰性氣體流
200‧‧‧堆疊
208‧‧‧層
210‧‧‧晶圓
212‧‧‧阻障層
216‧‧‧抗反射層
220‧‧‧蝕刻層
224‧‧‧遮罩特徵部
232‧‧‧光阻遮罩
234‧‧‧特徵部
236‧‧‧聚合物層
302‧‧‧沉積層
304‧‧‧側壁
310‧‧‧抗反射層
311‧‧‧BARC
312‧‧‧圖案化遮罩
313‧‧‧DARC
314‧‧‧遮罩特徵部
315‧‧‧側壁
330‧‧‧沉積層
332‧‧‧底部
334‧‧‧頂部
400‧‧‧電漿處理室
402‧‧‧限制環
404‧‧‧上電極
408‧‧‧下電極
410‧‧‧氣體源
412‧‧‧蝕刻氣體源
414‧‧‧沉積階段氣體源
416‧‧‧成形階段氣體源
418‧‧‧預處理氣體源
420‧‧‧排氣泵
428‧‧‧反應器蓋
435‧‧‧控制器
440‧‧‧電漿容積
444‧‧‧第一RF電源
448‧‧‧第二RF電源
452‧‧‧室壁
500‧‧‧電腦系統
502‧‧‧螢幕
504‧‧‧顯示器
506‧‧‧機殼
508‧‧‧磁碟機
510‧‧‧鍵盤
512‧‧‧滑鼠
514‧‧‧磁碟
520‧‧‧系統匯流排
522‧‧‧處理器
524‧‧‧記憶體
526‧‧‧固定式磁碟
530‧‧‧揚聲器
540‧‧‧網路介面
本發明乃經由實施例而非限制例而在附圖之圖式中加以說明，其中相同參考標號表示相同元件，其中：圖1為依據本發明之實施例之包含光阻遮罩預處理之電漿製程的高階流程圖。
圖2A-D概要地闡明利用依據本發明之實施例之多循環電漿製程之介電層中特徵部生成的橫剖面圖。
圖3A-D概要地闡明依據本發明之實施例之多循環、兩階段電漿製程之例子。
圖4為可用來進行PR遮罩預處理、隨後之電漿製程、及剝除之電漿處理室的概要圖。
圖5A-B闡明一電腦系統，其適合用來實施用於本發明之實施例中之控制器。
圖6為依據本發明之實施例之光阻遮罩預處理之詳細流程圖。
圖7A-D為利用依據本發明之實施例之多循環電漿製程加以處理之遮罩特徵部的概要橫剖面圖。
圖8A-D為利用依據本發明之另一實施例之多循環電漿製程加以處理之遮罩特徵部的概要橫剖面圖。
圖9A-D為利用依據本發明之又另一實施例之多循環電漿製程加以處理之遮罩特徵部及ARL的概要橫剖面圖。
102‧‧‧於蝕刻層上方設置光阻遮罩
104‧‧‧利用惰性氣體電漿預先處理光阻遮罩
106‧‧‧多循環電漿製程
108‧‧‧沉積階段
110‧‧‧成形階段
112‧‧‧額外的蝕刻製程
114‧‧‧剝除遮罩

Claims (20)

  1. 一種透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，利用波長不超過193nm之雷射光將該光阻遮罩加以圖案化，該方法包含：PR遮罩預處理步驟，利用惰性氣體電漿將PR遮罩預處理，以在不引起化學反應的情況下藉由壓擠而使該PR遮罩材料變堅固；及複數循環提供步驟，提供複數之循環，其中每個循環包含：一沉積階段，於該PR遮罩上方沉積一沉積層，該沉積層覆蓋該PR遮罩之遮罩特徵部之頂部及側壁；及一成形階段，將沉積於該PR遮罩上方之該沉積層加以塑形。
  2. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該惰性氣體包含Ar。
  3. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該PR遮罩預處理步驟包含：惰性氣體提供步驟，提供該惰性氣體；電漿形成步驟，由該惰性氣體形成電漿；及停止步驟，停止該惰性氣體流。
  4. 如申請專利範圍第3項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該電漿形成步驟包含：提供60MHz或更高之高頻。
  5. 如申請專利範圍第4項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該電漿形成步驟並不提供頻率低於50MHz之RF能量。
  6. 如申請專利範圍第4項之透過光阻(PR)遮罩在介電層蝕刻特徵 部的方法，其中該電漿形成步驟更包含：提供低於500瓦之功率。
  7. 如申請專利範圍第3項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該惰性氣體之氣流具有100sccm或更大。
  8. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段提供60MHz或更高之高頻。
  9. 如申請專利範圍第8項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段並不提供頻率低於50MHz之RF能量。
  10. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該成形階段提供60MHz或更高之高頻。
  11. 如申請專利範圍第10項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該成形階段並不提供頻率低於50MHz之RF能量。
  12. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段亦在該介電層蝕刻特徵部，且更於被蝕刻之特徵部之側壁上沉積該沉積層，及其中該成形階段將該沉積層移除。
  13. 如申請專利範圍第12項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段相對於該PR遮罩選擇性地蝕刻該介電層，及其中該成形階段相對於該介電層選擇性地移除該側壁上之該沉積層。
  14. 如申請專利範圍第13項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段並不移除該光阻遮罩，提供無限之選擇性。
  15. 如申請專利範圍第12項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段更於該遮罩特徵部之底部上沉積該沉積層，其中該成形階段更自該遮罩特徵部之該底部移除該沉積層而不蝕刻其下之該介電層，留下側壁以縮減該PR遮罩之CD，及其中該方法更包含：利用該PR遮罩將該介電層加以蝕刻，該PR遮罩具有藉由提供該複數循環而被縮減之該CD。
  16. 如申請專利範圍第12項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該沉積階段更於該遮罩特徵部之底部上沉積該沉積層，其中該成形階段更自該遮罩特徵部之該底部及該側壁移除該沉積層而不蝕刻其下之該介電層，俾能削減該側壁，及其中該方法更包含：利用藉由提供該複數循環而被削減之該PR遮罩將該介電層加以蝕刻。
  17. 如申請專利範圍第16項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該成形階段相對於該遮罩特徵部之密集區域而在孤立區域選擇性地回蝕該遮罩特徵部之側壁。
  18. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中一抗反射層(ARL)形成於該介電層之上、該圖案化PR遮 罩之下，及其中在每個循環中，該成形階段首先在該遮罩特徵部之底部蝕刻該ARL並削減該PR遮罩，而該沉積階段於該PR遮罩上沉積該沉積層，且更在該遮罩特徵部之該底部蝕刻該ARL。
  19. 如申請專利範圍第1項之透過光阻(PR)遮罩在介電層蝕刻特徵部的方法，其中該PR遮罩預處理步驟降低該PR遮罩之起泡作用以及在隨後之該沉積階段與成形階段之複數循環期間所造成之微粒污染。
  20. 一種透過光阻(PR)遮罩在介電層蝕刻特徵部的設備，利用波長不超過193nm之雷射光將該光阻遮罩加以圖案化，該設備包含：一電漿處理室，包含：一室壁，形成一電漿處理室外殼；一基板支座，支承該電漿處理室外殼內之一基板；一壓力調節器，用以調節該電漿處理室外殼內之壓力；至少一電極，用以提供電力至該電漿處理室外殼，以維持一電漿；一氣體入口，用以提供氣體至該電漿處理室外殼；及一氣體出口，用以從該電漿處理室外殼排出氣體；一氣體源，與該氣體入口流體連通，該氣體源包含：一蝕刻氣體源；一沉積階段氣體源；一成形階段氣體源；及一預處理氣體源；及一控制器，以可控制之方式連結至該氣體源以及該至少一電極，包含：至少一處理器；及非暫時性電腦可讀媒體，包含：利用惰性氣體電漿將該PR遮罩預處理之電腦可讀碼， 包含：從該預處理氣體源提供惰性氣體之電腦可讀碼；從該惰性氣體形成電漿之電腦可讀碼；及停止該惰性氣體流之電腦可讀碼；及提供複數循環之電腦可讀碼，每個循環包含一沉積階段及一成形階段，該電腦可讀碼包含：從該沉積階段氣體源提供沉積階段氣體之電腦可讀碼；從該沉積階段氣體形成電漿之電腦可讀碼，俾能於該PR遮罩上方沉積一沉積層，該沉積層覆蓋PR遮罩之遮罩特徵部之頂部及側壁，其中來自該沉積階段氣體之該電漿亦在該介電層蝕刻特徵部，且更於被蝕刻之該特徵部之側壁上沉積該沉積層；停止該沉積階段氣體流之電腦可讀碼；從該成形階段氣體源提供成形階段氣體之電腦可讀碼；從該成形階段氣體形成電漿之電腦可讀碼，俾能將沉積於該PR遮罩上方之該沉積層加以塑形，其中來自該成形階段氣體之該電漿將該沉積層移除；及停止該成形階段氣體流之電腦可讀碼。
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WO2009140139A2 (en) 2009-11-19
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