CN102117737B - 减小半导体器件中ler的方法及半导体器件 - Google Patents

减小半导体器件中ler的方法及半导体器件 Download PDF

Info

Publication number
CN102117737B
CN102117737B CN200910244517.4A CN200910244517A CN102117737B CN 102117737 B CN102117737 B CN 102117737B CN 200910244517 A CN200910244517 A CN 200910244517A CN 102117737 B CN102117737 B CN 102117737B
Authority
CN
China
Prior art keywords
semiconductor device
ler
finfet
grid
feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200910244517.4A
Other languages
English (en)
Other versions
CN102117737A (zh
Inventor
朱慧珑
骆志炯
尹海洲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Beijing Naura Microelectronics Equipment Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Beijing NMC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS, Beijing NMC Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN200910244517.4A priority Critical patent/CN102117737B/zh
Publication of CN102117737A publication Critical patent/CN102117737A/zh
Application granted granted Critical
Publication of CN102117737B publication Critical patent/CN102117737B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种减小半导体器件中LER的方法及半导体器件。具体地，根据本发明的实施例，该方法包括：对器件中特征的边缘进行离子轰击，以减小其LER。由此，可以有效减小由LER导致的器件性能恶化。

Description

减小半导体器件中LER的方法及半导体器件
技术领域
本申请涉及半导体器件领域，更为具体地，涉及一种减小半导体器件中所形成特征的线边缘粗糙度(LER)的方法以及采用该方法制造得到的半导体器件，其中所述半导体器件特别是鳍状场效应晶体管(FinFET)，所述特征特别是FinFET的栅极。
背景技术
随着技术的发展，集成电路上的集成密度日益提高。为了实现这种高集成度，器件特征的尺寸越来越小。这样的特征例如包括半导体器件中形成的连接线、功能区域等。
为了实现这种小尺寸特征，需要高分辨率的光刻工艺。但是，随着特征尺寸(如线宽)减小，将会遇到所谓“线边缘粗糙度”(LER)的问题。所谓LER，是指半导体器件中形成的特征的边缘或侧壁处的不规则程度。
特征中LER的出现可由相应光刻步骤中使用的光刻胶中存在的LER导致。而光刻胶中存在的LER可由多种因素造成，例如光刻胶本身的材料特性、光刻时使用的掩模本身的LER等等。此外，光刻时使用的刻蚀工艺，如等离子刻蚀，也会导致特征中出现LER。
特征中出现的这种LER最终将会影响器件的性能。例如，在形成栅极时如果存在LER，则将会大大影响器件的截止状态漏电流和短沟道效应的控制。因此，希望能够尽可能减小半导体器件中特征的LER。
发明内容
鉴于上述问题，本发明的目的之一在于提供一种制造半导体器件的方法及相应的半导体器件，其中能够充分减小半导体器件中所形成的特征的线边缘粗糙度(LER)。
根据本发明的一个方面，提供了一种减小半导体器件中特征的LER的方法，包括：对所述特征的侧壁进行离子轰击，以减小其LER。
优选地，离子以相对于所述边缘倾斜的角度，轰击所述特征。
优选地，所述离子为Ar或Xe。
优选地，所述离子为低能离子。
优选地，所述半导体器件为鳍状场效应晶体管(FinFET)，所述特征为该FinFET的栅极。
根据本发明的另一方面，提供了一种半导体器件，包括通过上述方法处理过的特征。
优选地，所述半导体器件为FinFET，所述特征为该FinFET的栅极。
根据本发明，可以有效减小半导体器件中所形成特征的LER，从而避免由LER造成的器件性能恶化。特别是对于FinFET之类的晶体管器件，特征特别是栅极LER的减小，可以避免阈值电压的变化，从而防止截止状态下的漏电流，并因此增大信噪比。
附图说明
图1示出了一种半导体器件(FinFET)的局部结构示意图；
图2示出了根据本发明的实施例对图1所示半导体器件进行处理的示意图；
图3示出了根据本发明实施例对半导体器件进行处理后得到的结构示意图。
具体实施方式
以下，将参照附图，对本发明的实施例进行详细的描述。
需要指出的是，本发明可广泛应用于各种半导体器件的制造工艺中。在此为了说明本发明，以鳍状场效应晶体管(FinFET)为例，来进行描述。但是，这种描述不应被理解为对本发明的限制。
如在背景技术部分所述，目前的半导体器件中集成度越来越高。这就导致在相同面积的晶片上集成的半导体结构如晶体管(例如，FET)越来越多。这可以通过降低FET的沟道长度并同时控制没有过多短沟道效应发生来实现。所谓“短沟道效应”，即在栅极和源极/漏极扩散区域之间共享的静电电荷引起短沟道器件中阈值电压降低的效应。
为了降低FET的沟道长度并同时防止出现短沟道效应，在提高沟道掺杂浓度同时必须减小栅极氧化物的厚度。但是，随着栅极氧化物厚度的减小，其所起到的绝缘所用将大大减弱，漏极电流将穿过该绝缘层而进入栅极，使得晶体管将不能正常工作。
为此，提出了所谓的多栅极晶体管，例如FinFET。在多栅极晶体管中，沟道被若干栅极所围绕，从而可以更为有效地抑制截止状态下的漏电流，并可以提高导通状态下的电流。由于这些特征，可以实现低功耗、高性能的半导体器件。
图1示出了一种双栅极FinFET的局部结构示意图。具体地，该FinFET 100包括在氧化物层105上形成的多个特征，如栅极101、源极102和漏极103，其中沿沟道设置有薄鳍片(Fin)104。在该Fin 104两侧各有一个栅极，这两个栅极电连接，以便对沟道进行调制。由于两个栅极有效地终止漏极场线，抑制在沟道的源极端感应到漏极电势，从而可以极大地抑制短沟道效应。
目前，已经提出了多种方法来形成这样的FinFET。这些形成方法并非是本发明的重点，在此不再赘述。但是，无论利用何种方法来形成FinFET，都离不开使用光刻(例如，包括沉积光刻胶、通过掩模曝光、显影形成图案、刻蚀、去除光刻胶等步骤)来形成栅极101、源极102、漏极103这些特征。因此，这些特征不可避免地存在线边缘粗糙度(LER)。特别是栅极101的LER将导致器件阈值电压发生变化，并因此减小器件的信噪比。
具体地，参见图2，其中示出了图1所示栅极101的一个截面。如图2所示，由于如上所述光刻工艺中存在的限制，所得到的栅极101的边缘(侧壁)是凹凸不平的(在图中为了清楚说明的目的，对这些细节进行了放大)，即LER，这对于器件性能有着不利的影响。
本发明的目的之一在于使得这种LER平滑，从而消除其对器件性能的影响。为此，根据本发明方法的实施例，在制造完成图1所示的FinFET结构之后，还对栅极101的侧壁进行离子轰击。根据本发明的实施例，可以使用惰性气体离子如Ar或Xe来进行轰击。另外，根据本发明的实施例，可以使用低能离子来进行轰击。
为了平滑LER，优选地，使用相对于栅极101的侧壁倾斜入射的离子束来进行轰击。在这种情况下，凸出部分将比凹进部分更大概率地受到离子束的轰击，从而凸出部分与凹进部分相比，以更大的速率被“切削”。结果，能更为有效地平滑栅极的侧壁。
例如，离子的能量在几到几十eV的范围内，可由等离子产生；轰击角度与所采用的离子能量有关，优选地倾斜约15至40度。
图3示出了在通过上述的离子轰击之后得到的结构。可以看出，栅极侧壁的LER得到了大大的改进。
以上针对FinFET中的栅极进行了描述。但是本领域普通技术人员应理解，本发明可应用于其他半导体器件、其他特征的处理。例如，不限于对FinFET的栅极，而是可以对其他晶体管结构的栅极来应用本发明，以减小其LER。
尽管以上参照本发明的实施例对本发明进行了说明，但是应当理解，在不脱离本发明范围的前提下，可以对此做出各种改变和等价替换。本发明不限于所公开的实施例，而是应由所附权利要求来限定。

Claims (5)

1.一种减小半导体器件中特征的线边缘粗糙度LER的方法，包括：
在通过光刻形成所述特征之后，对所述特征的侧壁进行离子轰击，以减小其LER，
其中，离子以相对于侧壁倾斜的角度，轰击所述特征，且所述离子为Ar或Xe。
2.如权利要求1所述的方法，其中，所述离子为低能离子。
3.如权利要求1所述的方法，其中，所述半导体器件为鳍状场效应晶体管FinFET，所述特征为该FinFET的栅极。
4.一种半导体器件，包括通过权利要求1所述的方法处理过的特征。
5.如权利要求4所述的半导体器件，其中，所述半导体器件为鳍状场效应晶体管FinFET，所述特征为该FinFET的栅极。
CN200910244517.4A 2009-12-30 2009-12-30 减小半导体器件中ler的方法及半导体器件 Active CN102117737B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200910244517.4A CN102117737B (zh) 2009-12-30 2009-12-30 减小半导体器件中ler的方法及半导体器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200910244517.4A CN102117737B (zh) 2009-12-30 2009-12-30 减小半导体器件中ler的方法及半导体器件

Publications (2)

Publication Number Publication Date
CN102117737A CN102117737A (zh) 2011-07-06
CN102117737B true CN102117737B (zh) 2015-01-07

Family

ID=44216433

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910244517.4A Active CN102117737B (zh) 2009-12-30 2009-12-30 减小半导体器件中ler的方法及半导体器件

Country Status (1)

Country Link
CN (1) CN102117737B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064808B2 (en) 2011-07-25 2015-06-23 Synopsys, Inc. Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same
US8609550B2 (en) 2011-09-08 2013-12-17 Synopsys, Inc. Methods for manufacturing integrated circuit devices having features with reduced edge curvature
US8629512B2 (en) * 2012-03-28 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Gate stack of fin field effect transistor with slanted sidewalls
CN103367156B (zh) * 2012-03-31 2015-10-14 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法、鳍式场效应管的形成方法
CN103855009B (zh) 2012-11-30 2017-06-13 中国科学院微电子研究所 鳍结构制造方法
JP6271235B2 (ja) 2013-01-24 2018-01-31 キヤノンアネルバ株式会社 フィンｆｅｔの製造方法およびデバイスの製造方法
CN104345568A (zh) * 2013-08-07 2015-02-11 中芯国际集成电路制造(上海)有限公司 减小光刻胶图形线宽粗糙度的方法
KR102148336B1 (ko) * 2013-11-26 2020-08-27 삼성전자주식회사 표면 처리 방법, 반도체 제조 방법 및 이에 의해 제조된 반도체 장치
CN105261559A (zh) * 2014-07-14 2016-01-20 超科技公司 在气态环境中激光加工光致抗蚀剂的方法
US11139402B2 (en) 2018-05-14 2021-10-05 Synopsys, Inc. Crystal orientation engineering to achieve consistent nanowire shapes
US11264458B2 (en) 2019-05-20 2022-03-01 Synopsys, Inc. Crystal orientation engineering to achieve consistent nanowire shapes
CN113885246B (zh) 2020-07-03 2023-02-28 京东方科技集团股份有限公司 黑矩阵结构及其制造方法、显示基板、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1603959A (zh) * 2003-09-29 2005-04-06 东京毅力科创株式会社 蚀刻方法和记录用于控制该方法的程序的计算机记录媒体
JP2006080277A (ja) * 2004-09-09 2006-03-23 Tokyo Electron Ltd 基板の処理方法
CN1806318A (zh) * 2003-06-12 2006-07-19 先进微装置公司 鳍状场效应晶体管中栅极区域的多步骤化学机械研磨
WO2009140139A2 (en) * 2008-05-13 2009-11-19 Lam Research Corporation Plasma process with photoresist mask pretreatment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1806318A (zh) * 2003-06-12 2006-07-19 先进微装置公司 鳍状场效应晶体管中栅极区域的多步骤化学机械研磨
CN1603959A (zh) * 2003-09-29 2005-04-06 东京毅力科创株式会社 蚀刻方法和记录用于控制该方法的程序的计算机记录媒体
JP2006080277A (ja) * 2004-09-09 2006-03-23 Tokyo Electron Ltd 基板の処理方法
WO2009140139A2 (en) * 2008-05-13 2009-11-19 Lam Research Corporation Plasma process with photoresist mask pretreatment

Also Published As

Publication number Publication date
CN102117737A (zh) 2011-07-06

Similar Documents

Publication Publication Date Title
CN102117737B (zh) 减小半导体器件中ler的方法及半导体器件
CN102254808B (zh) 减小ler的方法及实施该方法的装置
CN102364663A (zh) 栅极侧墙刻蚀方法、mos器件制造方法以及mos器件
KR100698079B1 (ko) 반도체소자 및 그의 제조방법
CN101154683A (zh) 晶体管结构及其制造方法
KR100650900B1 (ko) 반도체 소자 제조 방법
KR101272155B1 (ko) 측벽구조의 유전체를 이용한 수직형 터널링 트랜지스터 및 그 양방향 전류특성 억제 방법
KR20070013032A (ko) 플래쉬 메모리 소자의 제조방법
US7560770B2 (en) MOSFET device suppressing electrical coupling between adjoining recess gates and method for manufacturing the same
KR100598172B1 (ko) 리세스 게이트를 갖는 트랜지스터의 제조 방법
CN108807398B (zh) 半导体器件及其制造方法
KR100802272B1 (ko) 반도체 소자의 게이트 형성 방법
KR20070088055A (ko) 모스펫 소자의 제조방법
KR101038308B1 (ko) 반도체 소자의 트랜지스터 제조방법
KR100596829B1 (ko) 반도체 소자의 트랜지스터 형성방법
KR940002781B1 (ko) 곡면 이중 게이트를 갖는 반도체 장치의 제조방법
KR20010011002A (ko) 반도체소자의 트랜지스터 형성방법
KR100743637B1 (ko) 모스펫 소자의 제조방법
KR100741275B1 (ko) 반도체 소자 제조 방법
KR100960469B1 (ko) 반도체 소자의 제조방법
KR100818110B1 (ko) 반도체 소자 및 그의 제조 방법
KR100618705B1 (ko) 반도체 소자의 게이트 형성방법
KR100650772B1 (ko) 반도체 소자의 제조방법
KR20100079192A (ko) 반도체 소자 제조 방법
JPH01185973A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing

Co-patentee after: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd.

Patentee after: Institute of Microelectronics of the Chinese Academy of Sciences

Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing

Co-patentee before: BEIJING NMC Co.,Ltd.

Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20190314

Address after: 100176 No. 8 Wenchang Avenue, Daxing District, Beijing Economic and Technological Development Zone

Patentee after: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd.

Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing

Co-patentee before: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd.

Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences

TR01 Transfer of patent right