TWI481007B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI481007B
TWI481007B TW097123751A TW97123751A TWI481007B TW I481007 B TWI481007 B TW I481007B TW 097123751 A TW097123751 A TW 097123751A TW 97123751 A TW97123751 A TW 97123751A TW I481007 B TWI481007 B TW I481007B
Authority
TW
Taiwan
Prior art keywords
conductive pads
wiring
conductive pad
electrically connected
wiring substrate
Prior art date
Application number
TW097123751A
Other languages
English (en)
Chinese (zh)
Other versions
TW200919700A (en
Inventor
石川智和
岡田三香子
Original Assignee
瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW200919700A publication Critical patent/TW200919700A/zh
Application granted granted Critical
Publication of TWI481007B publication Critical patent/TWI481007B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
TW097123751A 2007-09-12 2008-06-25 Semiconductor device TWI481007B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007236594A JP5222509B2 (ja) 2007-09-12 2007-09-12 半導体装置

Publications (2)

Publication Number Publication Date
TW200919700A TW200919700A (en) 2009-05-01
TWI481007B true TWI481007B (zh) 2015-04-11

Family

ID=40430861

Family Applications (2)

Application Number Title Priority Date Filing Date
TW097123751A TWI481007B (zh) 2007-09-12 2008-06-25 Semiconductor device
TW104106919A TWI529908B (zh) 2007-09-12 2008-06-25 半導體裝置

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW104106919A TWI529908B (zh) 2007-09-12 2008-06-25 半導體裝置

Country Status (5)

Country Link
US (4) US8159058B2 (https=)
JP (1) JP5222509B2 (https=)
KR (1) KR101426568B1 (https=)
CN (2) CN101388389A (https=)
TW (2) TWI481007B (https=)

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JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN102890970B (zh) * 2011-07-21 2017-04-19 广东新岸线计算机系统芯片有限公司 一种pop封装的soc芯片dram输入/输出测试方法和装置
KR101831692B1 (ko) * 2011-08-17 2018-02-26 삼성전자주식회사 기능적으로 비대칭인 전도성 구성 요소들을 갖는 반도체 소자, 패키지 기판, 반도체 패키지, 패키지 적층 구조물 및 전자 시스템
JP5996177B2 (ja) 2011-10-21 2016-09-21 ルネサスエレクトロニクス株式会社 デバッグシステム、電子制御装置、情報処理装置、半導体パッケージおよびトランシーバ回路
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KR102032887B1 (ko) 2012-12-10 2019-10-16 삼성전자 주식회사 반도체 패키지 및 반도체 패키지의 라우팅 방법
US9875808B2 (en) 2013-01-15 2018-01-23 Micron Technology, Inc. Reclaimable semiconductor device package and associated systems and methods
KR102110984B1 (ko) 2013-03-04 2020-05-14 삼성전자주식회사 적층형 반도체 패키지
US20140361800A1 (en) * 2013-06-05 2014-12-11 Qualcomm Incorporated Method and apparatus for high volume system level testing of logic devices with pop memory
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JP2016062212A (ja) * 2014-09-17 2016-04-25 株式会社東芝 半導体記憶装置
KR102296746B1 (ko) 2014-12-31 2021-09-01 삼성전자주식회사 적층형 반도체 패키지
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
JP2017045915A (ja) 2015-08-28 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
CN107995773A (zh) * 2017-11-24 2018-05-04 深圳创维数字技术有限公司 一种电路板及测试系统
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TW202219517A (zh) * 2020-11-03 2022-05-16 點序科技股份有限公司 測試裝置

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Also Published As

Publication number Publication date
TW200919700A (en) 2009-05-01
KR101426568B1 (ko) 2014-08-05
US8698299B2 (en) 2014-04-15
US9330942B2 (en) 2016-05-03
US20090065773A1 (en) 2009-03-12
US8159058B2 (en) 2012-04-17
US20140070214A1 (en) 2014-03-13
US20140252357A1 (en) 2014-09-11
CN102867821A (zh) 2013-01-09
US20120153282A1 (en) 2012-06-21
CN101388389A (zh) 2009-03-18
JP5222509B2 (ja) 2013-06-26
TW201523836A (zh) 2015-06-16
US8766425B2 (en) 2014-07-01
KR20090027573A (ko) 2009-03-17
CN102867821B (zh) 2015-05-13
JP2009070965A (ja) 2009-04-02
TWI529908B (zh) 2016-04-11

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