CN101388389A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101388389A
CN101388389A CNA2008102109164A CN200810210916A CN101388389A CN 101388389 A CN101388389 A CN 101388389A CN A2008102109164 A CNA2008102109164 A CN A2008102109164A CN 200810210916 A CN200810210916 A CN 200810210916A CN 101388389 A CN101388389 A CN 101388389A
Authority
CN
China
Prior art keywords
circuit board
wiring
conductive
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2008102109164A
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English (en)
Chinese (zh)
Inventor
石川智和
冈田三香子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Publication of CN101388389A publication Critical patent/CN101388389A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
CNA2008102109164A 2007-09-12 2008-08-12 半导体器件 Pending CN101388389A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007236594 2007-09-12
JP2007236594A JP5222509B2 (ja) 2007-09-12 2007-09-12 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201210331265.0A Division CN102867821B (zh) 2007-09-12 2008-08-12 半导体器件

Publications (1)

Publication Number Publication Date
CN101388389A true CN101388389A (zh) 2009-03-18

Family

ID=40430861

Family Applications (2)

Application Number Title Priority Date Filing Date
CNA2008102109164A Pending CN101388389A (zh) 2007-09-12 2008-08-12 半导体器件
CN201210331265.0A Active CN102867821B (zh) 2007-09-12 2008-08-12 半导体器件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201210331265.0A Active CN102867821B (zh) 2007-09-12 2008-08-12 半导体器件

Country Status (5)

Country Link
US (4) US8159058B2 (https=)
JP (1) JP5222509B2 (https=)
KR (1) KR101426568B1 (https=)
CN (2) CN101388389A (https=)
TW (2) TWI481007B (https=)

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CN102890970A (zh) * 2011-07-21 2013-01-23 广东新岸线计算机系统芯片有限公司 一种pop封装的soc芯片dram输入/输出测试方法和装置
CN105990369A (zh) * 2014-09-17 2016-10-05 株式会社东芝 半导体存储装置
CN113178439A (zh) * 2020-01-27 2021-07-27 瑞萨电子株式会社 半导体装置

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JPH0525602A (ja) * 1991-07-17 1993-02-02 Nippon Steel Corp メツキ密着性に優れたアルミニウムメツキオーステナイト系ステンレス鋼板の製造法
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
JP5222509B2 (ja) * 2007-09-12 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置
JP5265183B2 (ja) * 2007-12-14 2013-08-14 新光電気工業株式会社 半導体装置
KR20100058359A (ko) * 2008-11-24 2010-06-03 삼성전자주식회사 다층 반도체 패키지, 그것을 포함하는 반도체 모듈 및 전자신호 처리 시스템 및 다층 반도체 패키지의 제조 방법
US8716868B2 (en) 2009-05-20 2014-05-06 Panasonic Corporation Semiconductor module for stacking and stacked semiconductor module
US8451620B2 (en) * 2009-11-30 2013-05-28 Micron Technology, Inc. Package including an underfill material in a portion of an area between the package and a substrate or another package
JP5586267B2 (ja) * 2010-02-24 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置
US8288849B2 (en) * 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
KR101744756B1 (ko) * 2010-06-08 2017-06-09 삼성전자 주식회사 반도체 패키지
JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101831692B1 (ko) * 2011-08-17 2018-02-26 삼성전자주식회사 기능적으로 비대칭인 전도성 구성 요소들을 갖는 반도체 소자, 패키지 기판, 반도체 패키지, 패키지 적층 구조물 및 전자 시스템
JP5996177B2 (ja) 2011-10-21 2016-09-21 ルネサスエレクトロニクス株式会社 デバッグシステム、電子制御装置、情報処理装置、半導体パッケージおよびトランシーバ回路
JP2013125765A (ja) 2011-12-13 2013-06-24 Elpida Memory Inc 半導体装置
KR20140059569A (ko) * 2012-11-08 2014-05-16 삼성전자주식회사 지그재그형 패드 배선 구조를 포함하는 반도체 소자
KR102032887B1 (ko) 2012-12-10 2019-10-16 삼성전자 주식회사 반도체 패키지 및 반도체 패키지의 라우팅 방법
US9875808B2 (en) 2013-01-15 2018-01-23 Micron Technology, Inc. Reclaimable semiconductor device package and associated systems and methods
KR102110984B1 (ko) 2013-03-04 2020-05-14 삼성전자주식회사 적층형 반도체 패키지
US20140361800A1 (en) * 2013-06-05 2014-12-11 Qualcomm Incorporated Method and apparatus for high volume system level testing of logic devices with pop memory
US9443758B2 (en) 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
KR102296746B1 (ko) 2014-12-31 2021-09-01 삼성전자주식회사 적층형 반도체 패키지
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
JP2017045915A (ja) 2015-08-28 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
CN107995773A (zh) * 2017-11-24 2018-05-04 深圳创维数字技术有限公司 一种电路板及测试系统
CN110473839B (zh) 2018-05-11 2025-03-21 三星电子株式会社 半导体封装系统
US10991638B2 (en) 2018-05-14 2021-04-27 Samsung Electronics Co., Ltd. Semiconductor package system
KR102573573B1 (ko) * 2019-10-25 2023-09-01 삼성전자주식회사 반도체 패키지
TWI711131B (zh) * 2019-12-31 2020-11-21 力成科技股份有限公司 晶片封裝結構
TW202219517A (zh) * 2020-11-03 2022-05-16 點序科技股份有限公司 測試裝置

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102890970A (zh) * 2011-07-21 2013-01-23 广东新岸线计算机系统芯片有限公司 一种pop封装的soc芯片dram输入/输出测试方法和装置
CN105990369A (zh) * 2014-09-17 2016-10-05 株式会社东芝 半导体存储装置
CN105990369B (zh) * 2014-09-17 2019-11-08 东芝存储器株式会社 半导体存储装置
CN113178439A (zh) * 2020-01-27 2021-07-27 瑞萨电子株式会社 半导体装置

Also Published As

Publication number Publication date
TW200919700A (en) 2009-05-01
KR101426568B1 (ko) 2014-08-05
US8698299B2 (en) 2014-04-15
US9330942B2 (en) 2016-05-03
US20090065773A1 (en) 2009-03-12
US8159058B2 (en) 2012-04-17
US20140070214A1 (en) 2014-03-13
US20140252357A1 (en) 2014-09-11
CN102867821A (zh) 2013-01-09
US20120153282A1 (en) 2012-06-21
JP5222509B2 (ja) 2013-06-26
TW201523836A (zh) 2015-06-16
TWI481007B (zh) 2015-04-11
US8766425B2 (en) 2014-07-01
KR20090027573A (ko) 2009-03-17
CN102867821B (zh) 2015-05-13
JP2009070965A (ja) 2009-04-02
TWI529908B (zh) 2016-04-11

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Application publication date: 20090318