CN105990369B - 半导体存储装置 - Google Patents
半导体存储装置 Download PDFInfo
- Publication number
- CN105990369B CN105990369B CN201510098097.9A CN201510098097A CN105990369B CN 105990369 B CN105990369 B CN 105990369B CN 201510098097 A CN201510098097 A CN 201510098097A CN 105990369 B CN105990369 B CN 105990369B
- Authority
- CN
- China
- Prior art keywords
- hole
- memory
- wiring board
- face
- semiconductor storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014188533A JP2016062212A (ja) | 2014-09-17 | 2014-09-17 | 半導体記憶装置 |
JP2014-188533 | 2014-09-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105990369A CN105990369A (zh) | 2016-10-05 |
CN105990369B true CN105990369B (zh) | 2019-11-08 |
Family
ID=55797808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510098097.9A Active CN105990369B (zh) | 2014-09-17 | 2015-03-05 | 半导体存储装置 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2016062212A (zh) |
CN (1) | CN105990369B (zh) |
TW (1) | TWI585877B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019153619A (ja) * | 2018-02-28 | 2019-09-12 | 東芝メモリ株式会社 | 半導体装置 |
CN111247636B (zh) * | 2018-03-22 | 2024-04-19 | 闪迪技术有限公司 | 包含具有贯穿衬底通孔结构的键合芯片组件的三维存储器件及其制造方法 |
JP2020047664A (ja) | 2018-09-14 | 2020-03-26 | キオクシア株式会社 | 半導体装置および半導体装置の作製方法 |
JP2022118876A (ja) | 2021-02-03 | 2022-08-16 | キオクシア株式会社 | 半導体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1493059A (zh) * | 2001-02-28 | 2004-04-28 | ������������ʽ���� | 存储卡及其制造方法 |
CN101388389A (zh) * | 2007-09-12 | 2009-03-18 | 株式会社瑞萨科技 | 半导体器件 |
CN203519662U (zh) * | 2013-09-26 | 2014-04-02 | 北大方正集团有限公司 | 用于电路板测试的转接板及测试装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013030712A (ja) * | 2011-07-29 | 2013-02-07 | Toshiba Corp | 半導体モジュールおよび半導体モジュールの製造方法 |
-
2014
- 2014-09-17 JP JP2014188533A patent/JP2016062212A/ja active Pending
-
2015
- 2015-03-04 TW TW104106906A patent/TWI585877B/zh active
- 2015-03-05 CN CN201510098097.9A patent/CN105990369B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1493059A (zh) * | 2001-02-28 | 2004-04-28 | ������������ʽ���� | 存储卡及其制造方法 |
CN101388389A (zh) * | 2007-09-12 | 2009-03-18 | 株式会社瑞萨科技 | 半导体器件 |
CN203519662U (zh) * | 2013-09-26 | 2014-04-02 | 北大方正集团有限公司 | 用于电路板测试的转接板及测试装置 |
Also Published As
Publication number | Publication date |
---|---|
TWI585877B (zh) | 2017-06-01 |
TW201613004A (en) | 2016-04-01 |
CN105990369A (zh) | 2016-10-05 |
JP2016062212A (ja) | 2016-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20170811 Address after: Tokyo, Japan Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Applicant before: Toshiba Corp. |
|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220129 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |