CN104851814A - 集成电路封装件及其形成方法 - Google Patents
集成电路封装件及其形成方法 Download PDFInfo
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- CN104851814A CN104851814A CN201510059724.8A CN201510059724A CN104851814A CN 104851814 A CN104851814 A CN 104851814A CN 201510059724 A CN201510059724 A CN 201510059724A CN 104851814 A CN104851814 A CN 104851814A
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Classifications
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Abstract
本发明提出了一种形成集成电路封装件的方法。第一多个第一层堆叠件被安装在衬底上,其中,衬底具有与第一层堆叠件中的每一个堆叠件均相应的一个或多个接触焊盘并且具有与第一层堆叠件中的每一个堆叠件均相配套的一个或多个探测焊盘。电测试第一层堆叠件中的每一个堆叠件并且识别已知良好的第一层堆叠件和已知不良的第一层堆叠件。第一多个堆叠衬底被安装在已知良好的第一层堆叠件上,由此形成多个第二层堆叠件。电测试第二层堆叠件中的每一个堆叠件以识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。本发明还提供了根据该形成集成电路封装件的方法而形成的半导体器件。
Description
优先权要求和交叉引用
本发明要求于2014年2月13日提交的标题为“Probe Pad Structure andMethods of Using Same”的美国临时申请第61/939,562号的优先权,其全部内容通过引用结合于此。
技术领域
本发明总体涉及集成电路,更具体地,涉及三维集成电路(3DIC)。
背景技术
半导体工业的不断发展部分归因于通过降低电子部件(例如,晶体管、二极管、电阻器、电容器等)的物理尺寸以允许更多的部件被置于给定的芯片区域而持续改进了电子部件的集成密度。因为器件被制造在半导体晶圆的表面上,一些改进实质上是二维(2D)的。
另一种增大器件密度的方法是将各管芯叠置于彼此的顶面上并且通过连接件(诸如,通孔(TV))而互连或布线。这种配置被称为三维集成电路(3DIC)。3DIC的一些益处包括:例如,占用较小的封装,通过减小信号互连件的长度来降低功耗,以及在各个管芯在组装之前被分别检测的情况下提高了产量并且降低了制造费用。
发明内容
根据本发明的一个方面,提供了一种形成集成电路封装件的方法,该方法包括:提供衬底;将多个第一层堆叠件安装在衬底上,其中,衬底具有与第一层堆叠件中的每一个堆叠件均相对应的一个或多个接触焊盘并且具有与第一层堆叠件中的每一个堆叠件均相配套的一个或多个探测焊盘;电测试第一层堆叠件中的每一个堆叠件并且识别已知良好的第一层堆叠件和已知不良的第一层堆叠件;将第一多个堆叠衬底安装在已知良好的第一层堆叠件上,由此形成多个第二层堆叠件;以及电测试第二层堆叠件中的每一个堆叠件,从而识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。
优选地,多个第一层堆叠件是多个集成电路管芯。
优选地,多个第一层堆叠件是多个中介层。
优选地,该方法还包括:将多个伪衬底安装至已知不良的第一层堆叠件。
优选地,电测试第一层堆叠件中的每一个堆叠件包括测试第一层堆叠件中的每一个堆叠件的功能。
优选地,该方法还包括:将第二多个堆叠衬底安装在已知良好的第二层堆叠件上,由此形成多个第三层堆叠件,其中,第二多个堆叠衬底被安装在第一多个堆叠衬底的顶面上;以及电测试第三层堆叠件中的每一个堆叠件,并且识别已知良好的第三层堆叠件和已知不良的第三层堆叠件。
优选地,该方法还包括:将第二多个堆叠衬底安装至已知良好的第一层堆叠件上,由此形成多个第三层堆叠件,其中,将第二多个堆叠衬底与第一多个堆叠衬底相邻接地安装;以及电测试第三层堆叠件中的每一个堆叠件,并且识别已知良好的第三层堆叠件和已知不良的第三层堆叠件。
根据本发明的另一方面,提供了一种形成集成电路封装件的方法,该方法包括:提供衬底,衬底具有第一面和第二面,衬底在第一面上具有多个第一接触焊盘和多个探测焊盘,并且衬底在第二面上具有多个第二接触焊盘;将多个第一层堆叠件安装至衬底上的第一接触焊盘上;使用探测焊盘来电测试第一层堆叠件中的每一个堆叠件以识别已知良好的第一层堆叠件和已知不良的第一层堆叠件;将第一多个堆叠衬底安装在已知良好的第一层堆叠件上,并且将第一多个伪衬底安装在已知不良的第一层堆叠件上,由此形成多个第二层堆叠件;以及使用探测焊盘来电测试第二层堆叠件的子集,第二层堆叠件的子集是不包括伪衬底的那些堆叠件,并且识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。
优选地,多个第一层堆叠件是多个集成电路管芯。
优选地,多个第一层堆叠件是多个中介层。
优选地,该方法还包括:在衬底的第一面上方形成模塑料;以及沿着划线切割衬底以形成集成电路封装件。
优选地,第一多个伪衬底包括已知不良的堆叠衬底。
优选地,该方法还包括:将第二多个堆叠衬底安装在已知良好的第二层堆叠件上,并且将第二多个伪衬底安装在已知不良的第二层堆叠件和第一多个伪衬底上,由此形成多个第三层堆叠件;以及电测试第三层堆叠件的子集,第三层堆叠件的子集是不包括伪衬底的那些堆叠件,并且识别已知良好的第三层堆叠件和已知不良的第三层堆叠件。
优选地,将第二多个堆叠衬底安装在第一多个堆叠衬底的顶面上。
优选地,将第二多个堆叠衬底邻接于第一多个堆叠衬底安装。
根据本发明的又一方面,提供了一种半导体器件,包括:衬底,衬底具有第一面和与第一面相对的第二面;第一堆叠件,位于衬底的第一面上,第一堆叠件具有多个堆叠衬底;探测焊盘,位于衬底的第一面上,探测焊盘与第一堆叠件相配套;以及接触焊盘,位于衬底的第二面上。
优选地,第一多个堆叠衬底包括集成电路管芯。
优选地,第一多个堆叠衬底包括中介层。
优选地,第一堆叠件包括第一堆叠衬底,安装在第一堆叠衬底上的第二堆叠衬底,以及安装在第二堆叠衬底上的第三堆叠衬底。
优选地,第一堆叠件包括第一堆叠衬底以及直接安装至第三堆叠衬底的第二堆叠衬底。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,各种部件没有按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1A是示出了根据一些实施例的形成在面板上衬底(SoP)上的集成电路封装件的三维视图;
图1B是示出了根据一些实施例的形成在晶圆上衬底(SoW)上的集成电路封装件的三维视图;
图2至图6是示出了根据一些实施例的形成集成电路封装件的方法的截面图;
图7A至图11B是示出了根据一些实施例在中间封装工艺过程中对封装件进行E测试工艺的截面图;
图12至图16是示出了根据一些实施例的在晶圆上衬底上中介层(IoSoW)上形成集成电路封装件的方法的截面图;
图17至图21是示出了根据一些实施例的形成集成电路封装件的方法的截面图;
图22是示出了根据一些实施例的形成集成电路封装件的方法的流程图。
具体实施方式
以下公开提供了多种不同实施例或实例,用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚,并且其本身不表示所述多个实施例和/或配置之间的关系。
此外,在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等的空间关系术语,以容易地描述如图中所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外,空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其它方式定位(旋转90度或在其他方位),并且通过在此使用的空间关系描述符进行相应地解释。
本发明提供了一种集成电路封装件的结构及其形成方法。更具体地,在下面更为详细地描述了带有嵌入的探测焊盘的集成电路封装件。另外,下面还提供了使用嵌入的探测焊盘来形成集成电路封装件的方法。
在具体地阐述所示出的实施例之前,一般论述了示例性的实施例的有益特征和某些方面。在此所描述的实施例的一般方面包括设计在衬底的正面(例如,衬底中安装堆叠衬底的一面)上的探测焊盘。如下面详细描述的那样,堆叠衬底可以是集成电路管芯、中介层等。另一个一般方面是可以在封装工艺过程中,应用电子测试,所谓的E测试,诸如,在叠放多个堆叠衬底的每次堆叠步骤后,执行E测试。通过这种方法,在封装工艺过程中可以将已知不良管芯(KBD)和/或已知不良插入器(KBI)识别出来以及将其再加工、替换、去除、丢弃、标记或另外说明。下面的实施例的另一一般方面在于可将附加的堆叠衬底的进一步处理/叠放仅局限于已知良好管芯(KGD)和/或已知良好插入器(KGI),由此降低了制造费用并且改善了整体产量。在下文中将集成电路封装件简单地称为封装件。
现参考所示出的实施例,图1A是根据一些实施例的三维视图,其示出了形成在置于载体101上的衬底103上的封装件105。例如,可以使用粘合层(未示出)等将衬底103附接至载体101上。在一些实施例中,载体101为形成在其上的各层提供了结构支撑,并且可以代表印刷电路板(PCB),定位模具(jig)等。载体101可以由例如聚合物材料、陶瓷材料,硅,石英,玻璃,金属等制成。
在一些实施例中,衬底103为封装件105提供了结构性基底以及电接口。例如,衬底103可以是层压衬底、硅中介层,玻璃中介层等。在一些实施例中,衬底103可以包括多个导电层(未分别示出),这些层中的一些是位于衬底103内的夹层。这些层可以被蚀刻成具有各种宽度和长度的迹线并且通过层间通孔连接。这些迹线和通孔可以共同形成电气网以将电源、接地端和信号从衬底103的顶面布至衬底103的底面。例如,衬底103可以由硅、有机(层压)材料(诸如,双马来酰亚胺三嗪(BT)、聚合物基材料(诸如,液晶聚合物(LCP))、陶瓷材料(诸如,低温共烧陶瓷(LTCC))等制成。衬底103的导电层和通孔可以由任意适合的导电材料(诸如,铜、铝、银、金、其他金属、合金、它们的组合等)形成,并且可以通过任意适合的技术(诸如,电化学镀(ECP)、无电镀、诸如溅射、印刷、化学汽相沉积(CVD)方法的其他沉积方法等)形成。在一些实施例中,衬底103包括电气元件,诸如,电阻器、电容器、信号再分布电路,它们的组合等。这些电气元件可以是有源的、无源的或它们的组合。在其他实施例中,衬底103其中没有有源的和无源的电气元件。
进一步参考图1A,示出了面板上衬底(substrate on panel,SoP)实施例,其中,载体101和衬底103两者具有矩形形状。在其他实施例中,载体101和衬底103可具有不同的形状。例如,图1B示出了晶圆上衬底(SoW)实施例,其中,衬底103和载体101均具有圆形形状。图1A和图1B中所示的载体101的形状仅用于说明目的,并且在一些实施例中,载体101的形状可以不与衬底103的形状相同。
进一步参考图1A和图1B,如以下详细描述的那样,通过在衬底103上叠放多层堆叠衬底而在衬底103上形成封装件105。在将每层堆叠衬底安装在衬底103上之后,均执行E测试来识别良好的堆叠件。在一些实施例中,仅在良好的堆叠件顶面上执行后续的堆叠,并且由此可以改变每个封装件105中的堆叠衬底的数量。在下文中,在所示出的实施例中,将三层堆叠衬底附接在衬底103上。在其他实施例中,可以根据封装件105的规格来改变层数。
封装件105可以根据在下文所详细讨论的封装过程中对每个封装件105所执行的中间和最终E测试的结果来区分。具体而言,已知良好封装件(KGP)107(以白色填充物表示)是封装件105中通过所有E测试的子集,第一多个已知不良封装件(KBP)109(以“/”填充物表示),第二多个KBP 111(以“\”填充物表示),以及第三多个KBP 113(以“X”填充表示)是封装件105中未通过E测试中的一个的子集。
正如下面详细讨论的那样,第二多个KBP 111和第三多个KBP 113是未通过中间E测试中的一个的封装件。而且,第二多个KBP 111和第三多个KBP 113在某种意义上是未完成的封装件,它们包括的堆叠衬底的数量少于KGP107。第一多个KBP 109是未通过最终的E测试的封装件,并且由此包括的堆叠衬底数量与KGP 107相同。如下面详细讨论的那样,每个KGP 107均包括第一数量的堆叠衬底,每个第一多个KBP 109均包括第二数量的堆叠衬底,每个第二多个KBP 111均包括第三数量的堆叠衬底,并且每个第三多个KBP 113均包括第四数量的堆叠衬底。在一些实施例中,第一数量等于第二数量,第二数量大于第三数量,并且第三数量大于第四数量。然后,在一些实施例中,再加工、替换、去除、丢弃、标记或另外说明被识别出来的KBP。例如,通过沿着位于相邻的封装件105之间的划线117将封装件105切割成小块。
在下文中,参考相邻的封装件115描述了形成封装件105的方法,相邻的封装件115包括四个封装件,一个源于KGP107,一个源于第一多个KBP 109,一个源于第二多个KBP 111,并且一个源于第三多个KBP 113。应该注意到,封装件的这种配置被提供用于为各个示出的实施例的后续说明提供帮助并且不以任何方式局限于本公开。
参考图2至图6,示出了相邻的封装件115的截面图(沿着图1A和图1B中的线AA’截取),该图示出了根据一些实施例的形成封装件105的方法。在所示出的实施例中,堆叠的各衬底是集成电路管芯。首先参考图2,将包括第一管芯201、第二管芯203、第三管芯205以及第四管芯207的第一管芯层安装在衬底103上。第一管芯201、第二管芯203、第三管芯205、第四管芯207可以通过例如球焊、焊料贴装、铜球、铜柱等(它们在第一管芯层和衬底103之间提供了电连接)被安装在衬底103上。在一些实施例中,第一管芯层中的每个以及所有以下所描述的其他管芯均包括一个或多个片上系统(SoC)、存储器芯片、存储器块(memory cube)、处理器芯片、逻辑芯片,以及它们的组合。
此外,除了传统地形成在衬底103的正面103f上的用于为第一管芯层提供电连接的第一多个接触焊盘211以外,示出了在衬底103的正面103f上与每个管芯相配套的探测焊盘209。在所示出的实施例中,用于每个管芯的两个探测焊盘均形成在衬底103的正面103f上。在其他实施例中,可能存在一个或多个探测焊盘,它们对一个或多个所安装的管芯而言是共用的,和/或可能存在不同数量的与每个管芯相结合的探测焊盘。在所示出的实施例中,探测焊盘209形成在衬底103的某些位置中,诸如,随后将在此处将衬底103切割成小块的划线117。
进一步参考图2,在如上所述地将第一管芯层安装在衬底103上之后,执行电和/或功能测试以确保第一管芯201、第二管芯203、第三管芯205以及第四管芯207的正常运行,以及第一管芯层和衬底103之间的正常电连接,和/或中间封装件整体的正常运行。在一些实施例中,在将第一管芯层安装在衬底103上之后执行第一E测试213,得到例如,第一管芯201“故障”的指示,以及第二管芯203、第三管芯205和第四管芯207“通过”的指示。基于第一E测试213的结果,第一管芯201被识别为已知不良管芯(KBD),而第二管芯203、第三管芯205以及第四管芯207被识别为已知良好管芯(KGD)。
参考图3,随后将第二管芯层安装在一些第一管芯层的顶面上。由于第一管芯层的第一管芯201被识别为KBD,第二管芯层没有被安装在第一管芯201顶面上。通过在中间阶段将第一管芯201识别为KBD,可以通过不在第一管芯201顶面上安装其他管芯来大大减少制造费用。此外,对第一管芯201不再执行后续的E测试。在所示出的实施例中,第二管芯层包括安装在第二管芯203顶面上的第五管芯301,安装在第三管芯205顶面上的第六管芯303,以及安装在第四管芯207顶面上的第七管芯305。使用例如微凸块、铜柱等将第二管芯层安装到第一管芯层上,从而在第二管芯层和第一管芯层的KGD之间提供电连接。
进一步参考图3,在将第二管芯层安装在第一管芯层的KGD的顶面上之后,执行第二E测试313以测试所得到的中间封装件。执行第二E测试313以确保第二管芯层的正常的运行,第二管芯层和第一管芯层之间的正常的电连接,和/或中间封装件整体的正常的运行。在所示出的实施例中,仅需要测试三个管芯堆叠件,因为第一管芯201已经被标记为KBD。例如,第二E测试313的结果指出包括第二管芯203和第五管芯301的第一管芯堆叠件307“故障”,并且指出包括第三管芯205和第六管芯303的第二堆叠件309以及包括第四管芯207和第七管芯305的第三堆叠件311“通过”。因此,第一管芯堆叠件307被识别为不良堆叠件,第二堆叠件309和第三堆叠件311被识别为良好堆叠件,因为它们通过了两轮E测试,诸如,第一E测试213和第二E测试313。
参考图4,将第三管芯层安装在一些第二管芯层的顶面上。在所示出的实施例中,第三管芯层包括安装在第六管芯303顶面上的第八管芯401和安装在第七管芯305顶面上的第九管芯403,这完成了封装件105的形成。然后,对包括第三管芯205、第六管芯303和第八管芯401的第四管芯堆叠件405以及包括第四管芯207、第七管芯305和第九管芯403的第五管芯堆叠件407执行最终E测试409以确保第四管芯堆叠件405和第五管芯堆叠件407的正常的运行。在所示出的实施例中,最终的E测试409指出第四管芯堆叠件405“故障”,并且指出第五管芯堆叠件407“通过”。因此,第四管芯堆叠件405被识别为不良堆叠件,而第五管芯堆叠件407被识别为良好堆叠件。
总之,再次参考图1A和图1B,第一管芯201代表第三多个KBP 113中的一个,第一管芯堆叠件307代表第二多个KBP 111中的一个,第四管芯堆叠件405代表第一多个KBP 109中的一个,而第五管芯堆叠件407代表KGP 107中的一个。如以上详细描述的那样,在一些实施例中,每个封装件105均最多包括三个安装在彼此顶面上的堆叠的衬底。然而,在其他实施例中,根据封装件105的设计规格,封装件105可以包括任意数量的堆叠衬底。
在一些实施例中,如图5中所示,模塑料501被设置在衬底103上方的封装件105周围。模塑料501填充了封装件105之间的间隔并且封装了封装件105以阻止例如外部的污染和湿气。模塑料501包括模制材料并且可以包括环氧树脂、有机聚合物、或添加或未添加硅基或玻璃基填充物的聚合物等。在一些实施例中,模塑料501包括其被施加时为胶状液体的液态模塑料(LMC)。模塑料501可以任选地包括其他绝缘材料。可以使用例如化学机械抛光(CMP)、蚀刻工艺等将模塑料501的多余材料从封装件105上方去除。
参考图6,将载体101从衬底103上剥离并且将连接件601安装在衬底103的背面103b上的第二多个接触焊盘603上。在一些实施例中,连接件601可以包括焊料凸块、焊料球、铜凸块、铜柱、球栅阵列(BGA)等。然后,例如通过沿着划线117切割衬底103而将封装件105切割成小块。如果经济上可行可以再加工一个或多个KBP,或可以将其切割成小块以及作为非完全堆叠的封装件(non-fully-stacked)进行出售。在一些实施例中,探测焊盘209在切割工艺之后不被销毁并且保留在封装件105上。
图7A至图11B示出了在以上参考图2和图3所描述的中间封装步骤过程中对其中一个封装件105进行的E测试。首先参考图7A和图7B,分别示出了在以上参考图2所描述的中间封装步骤过程中,其中一个封装件105的顶视图和截面图(沿着图7A中的线AA’截取)。更具体地,图7A和图7B示出了安装在载体101上的衬底103上的第一管芯层701。探测焊盘209如图7A中所示具有矩形形状。然而,在其他实施例中,探测焊盘209可以具有其他形状,诸如,正方形、圆形等。另外,在一些实施例中,表面贴装器件(SMD)703可以形成在衬底103上,表面贴装器件(SMD)703可以充当工艺控制监控(PCM)结构。例如,SMD 703可以包括无源器件(诸如,例如,电阻器、电容器等)或有源器件(诸如,二极管等)。通过探测焊盘209对中间封装件执行中间E测试705。在一些实施例中,对中间封装件执行的中间E测试705可以包括例如对第一管芯层(tier die)701的PCM测试,已知良好堆叠件(KGS)测试,以及全功能电路探测(CP)测试。图7B中示出了在中间E测试705过程中经过中间封装件的可能的电流路径707。例如,电流可以从一个探测焊盘开始,经过SMD703、经过衬底103的导线和通孔、经过衬底103和第一管芯层701之间的互连件,并且经过第一管芯层701流至另一个探测焊盘。
图8A和图8B示出了在以上参考图3所描述的中间封装步骤过程中对其中一个封装件105进行的E测试过程。具体地,图8A和图8B分别示出了安装在图7A和图7B的中间封装件上的第二管芯层801的顶视图和截面图(沿着图8A中的线AA’截取)。在所示出的实施例中,例如使用微凸块803将第二管芯层801安装在第一管芯层701上。通过探测焊盘209对所得到的中间封装件执行中间E测试705。在一些实施例中,中间E测试705可以包括例如对第二管芯层801的PCM测试、已知良好堆叠件(KGS)测试、第一管芯层701和第二管芯层801之间的连通性测试、以及全功能电路探测(CP)测试。图8B中示出了在中间E测试705的过程中经过所得到的中间封装件的可能的电流路径707。例如,电流可以从一个探测焊盘经过SMD703、经过衬底103的导线和通孔、经过衬底103和第一管芯层701之间的互连件、经过微凸块803,并且经过第二管芯层801流至另一个探测焊盘。
图9A和图9B是在以上参考图3所描述的中间封装步骤过程中对其中一个封装件105进行的E测试过程。具体地,图9A和图9B是分别示出了与以上参考图8A和图8B描述的实施例相类似的实施例的顶视图和截面图(沿着图9A中的线AA’截取)。在所示出的实施例中,第二管芯层801以管芯堆叠件代表,其中,使用例如微凸块803并且通过硅通孔或通过衬底通孔(TSV)901将各个管芯彼此堆叠和互连。在一些实施例中,在中间E测试705过程中,电流可以从一个探测焊盘经过SMD 703、经过衬底103的导线和通孔,经过衬底103和第一管芯层701之间的互连件,经过微凸块803,并且经过第二管芯层801的通孔TSV 901流至另一个探测焊盘。
图10A至图11B示出了在以上参考图2和图3所描述的中间封装步骤过程中对其中一个封装件105进行的E测试过程。具体地,图10A至图11B是分别示出了与以上参考图8A至图9B描述的实施例相类似的实施例的顶视图和截面图(沿着图10A和图11A中的线AA’截取)。在所示出的实施例中,使用导电柱1001将中间封装件的各个管芯彼此相互安装。在一些实施例中,在中间E测试705过程中,电流可以从一个探测焊盘经过SMD 703,经过衬底103的导线和通孔,经过衬底103和第一管芯层701之间的互连件,经过导电柱1001,以及经过第二管芯层801的TSV 901流至另一个探测焊盘。
参考图12至图16,示出了相邻的多个封装件115的截面图(沿着图1A和图1B中的线AA’截取),该截面图示出了根据一些实施例的形成封装件105的方法。具体地,图12至图16示出了形成晶圆上衬底上中介层(IoSoW,interposer on substrate on wafer)封装件的实施例。如下面详细地描述的那样,所示出的封装方法类似于以上参考图2至图6所描述的封装方法。然而,在所示出的实施例中,第一层堆叠衬底可以是中介层,在其顶面上安装有第二管芯层和第三管芯层。在一些实施例中,第二管芯层和第三管芯层并排地安装在中介层顶面上以形成如图14至图16中所示的一个封装件105。在所示出的实施例中,中介层提供了在第二管芯层和第三管芯层之间电连接。
首先参考图12,在这个实施例中,分别以第一中介层1201、第二中介层1203、第三中介层1205以及第四中介层1207代表第一层堆叠衬底。每个中介层均可以由硅晶圆、玻璃等形成,并且可以具有一个或多个延伸穿过其中的通孔。在一些实施例中,一个或多个中介层可以具有形成在其上的有源的或无源的器件。
进一步参考图12至图16,执行类似于以上参考图2至图6所描述的那些步骤的后续的封装步骤以形成封装件105。如以上详细描述的那样,在一些实施例中,每个封装件105包括至多三层堆叠衬底。然而,在其他实施例中,根据封装件105的设计规格,封装件105可以包括任意层数的堆叠衬底。另外,一旦理解了本发明,以上所论述的实施例的各种变型对本领域的技术人员是显而易见的。
参考图17至图21,示出了相邻的封装件115的截面图(沿着图1A和图1B中的线AA’截取),该截面图示出了根据一些实施例的形成封装件105的另一种方法。具体地,图17至图21示出了与以上参考图2至图6所论述的实施例类似的实施例。与以上参考图2至图6所论述的实施例相比,在所示出的实施例中,伪衬底1801被安装在KBP顶面上以确保每个封装件105中均具有相同数量的管芯。例如,图18示出了安装在第一管芯201顶面上的一个伪衬底1801,而图19示出了安装在第五管芯301顶面上的一个伪衬底1801以及安装在第一管芯201顶面上的两个伪衬底1801。在一些实施例中,伪衬底1801是没有有源和无源器件的管芯和/或中介层并且不为封装件105提供其他功能。在其他实施例中,伪衬底1801可以是已知不良管芯(KBD)。每个封装件中均具有相同数量的管芯是有益的。例如,封装件105的统一的尺寸可以有助于在衬底103上形成均匀的模塑料501层。
图22是示出了根据一些实施例形成集成电路封装件的方法的流程图。该方法于步骤2201起始,其中,将第一多个堆叠衬底放置在衬底上,如以上参考图2所论述的那样,该衬底具有一个或多个的各个堆叠衬底的探测焊盘。在步骤2203中,对第一多个堆叠衬底中的每一个均执行E测试。根据E测试的结果,在步骤2205中,识别多个已知不良的第一层堆叠件,其中包括如以上参考图2所论述的未通过E测试的堆叠件。另外,识别多个已知良好的第一层堆叠件,其中包括如以上参考图2所论述的通过E测试的堆叠件。然后,在步骤2207中,对已知良好的第一层堆叠件中的每一个执行管芯数量测试。如果已知良好的第一层堆叠件中的堆叠衬底的数量等于由封装件设计所规定的期望的数量,那么该方法在此步骤处停止。反之,该方法将继续进入步骤2209,其中,将第二多个堆叠衬底安装在已知良好的第一层堆叠件上并且将多个第二层堆叠件形成为如以上参考图3所论述的那样。在步骤2211中,如以上参考图3所论述的那样,对第二层封装件中的每一个均执行E测试。根据E测试的结果,在步骤2213中,识别多个已知不良的第二层堆叠件,其中包括未通过以上参考图3所论述的E测试的第二层堆叠件。另外,识别多个已知良好的第二层封装件,其中包括如以上参考图3所论述的通过E测试的第二层封装件。然后,在步骤2215中,对已知良好的第二层堆叠件中的每一个均执行管芯数量测试。如果已知良好的第二层堆叠件中的管芯数量等于由封装件设计所规定的期望的数量,那么该方法将在此步骤处停止。反之,重复步骤2209至2215一次或多次直至达到每个封装件中期望的堆叠衬底数量。
在一个实施例中,一种形成集成电路封装件的方法包括提供衬底,以及将多个第一层堆叠件安装在衬底上,其中,该衬底具有与第一层堆叠件中的每一个均相应的一个或多个接触焊盘并且具有与第一层堆叠件中的每一个相配套的一个或多个探测焊盘。该方法进一步包括电测试第一层堆叠件中的每一个并且识别已知良好的第一层堆叠件和已知不良的第一层堆叠件,将第一多个堆叠衬底安装在已知良好的第一层堆叠件上,由此形成多个第二层堆叠件,并且电测试第二层堆叠件中的每一个,从而识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。
在另一个实施例中,一种形成集成电路封装件的方法包括提供衬底,该衬底具有第一面和第二面,衬底在其第一面上具有多个第一接触焊盘和多个探测焊盘,并且在第二面上具有多个第二接触焊盘。该方法还包括将多个第一层堆叠件安装在衬底上的第一接触焊盘上,并且使用探测焊盘电测试第一层堆叠件中的每一个以识别已知良好的第一层堆叠件和已知不良的第一层堆叠件。该方法进一步包括将第一多个堆叠衬底安装在已知良好的第一层堆叠件上,并且将第一多个伪衬底安装在已知不良的第一层堆叠件上,由此形成多个第二层堆叠件,并且使用探测焊盘电测试第二层堆叠件的子集,第二层堆叠件的子集是不包括伪衬底的那些堆叠件,并且识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。
在又一个实施例中,一种半导体器件包括衬底,该衬底具有第一面和与第一面相对的第二面,以及位于衬底的第一面上的第一堆叠件,该第一堆叠件具有多个堆叠衬底。该半导体器件还包括:位于衬底的第一面上的探测焊盘,该探测焊盘与第一堆叠件相配套;以及位于衬底的第二面上的接触焊盘。
上面论述了若干实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种形成集成电路封装件的方法,所述方法包括:
提供衬底;
将多个第一层堆叠件安装在所述衬底上,其中,所述衬底具有与所述第一层堆叠件中的每一个堆叠件均相对应的一个或多个接触焊盘并且具有与所述第一层堆叠件中的每一个堆叠件均相配套的一个或多个探测焊盘;
电测试所述第一层堆叠件中的每一个堆叠件并且识别已知良好的第一层堆叠件和已知不良的第一层堆叠件;
将第一多个堆叠衬底安装在所述已知良好的第一层堆叠件上,由此形成多个第二层堆叠件;以及
电测试所述第二层堆叠件中的每一个堆叠件,从而识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。
2.根据权利要求1所述的方法,其中,所述多个第一层堆叠件是多个集成电路管芯。
3.根据权利要求1所述的方法,其中,所述多个第一层堆叠件是多个中介层。
4.根据权利要求1所述的方法,还包括:将多个伪衬底安装至所述已知不良的第一层堆叠件。
5.根据权利要求1所述的方法,其中,电测试所述第一层堆叠件中的每一个堆叠件包括测试所述第一层堆叠件中的每一个堆叠件的功能。
6.一种形成集成电路封装件的方法,所述方法包括:
提供衬底,所述衬底具有第一面和第二面,所述衬底在所述第一面上具有多个第一接触焊盘和多个探测焊盘,并且所述衬底在所述第二面上具有多个第二接触焊盘;
将多个第一层堆叠件安装至所述衬底上的所述第一接触焊盘上;
使用所述探测焊盘来电测试所述第一层堆叠件中的每一个堆叠件以识别已知良好的第一层堆叠件和已知不良的第一层堆叠件;
将第一多个堆叠衬底安装在所述已知良好的第一层堆叠件上,并且将第一多个伪衬底安装在所述已知不良的第一层堆叠件上,由此形成多个第二层堆叠件;以及
使用所述探测焊盘来电测试第二层堆叠件的子集,所述第二层堆叠件的子集是不包括伪衬底的那些堆叠件,并且识别已知良好的第二层堆叠件和已知不良的第二层堆叠件。
7.根据权利要求6所述的方法,其中,所述多个第一层堆叠件是多个集成电路管芯。
8.根据权利要求6所述的方法,其中,所述多个第一层堆叠件是多个中介层。
9.一种半导体器件,包括:
衬底,所述衬底具有第一面和与所述第一面相对的第二面;
第一堆叠件,位于所述衬底的第一面上,所述第一堆叠件具有多个堆叠衬底;
探测焊盘,位于所述衬底的第一面上,所述探测焊盘与所述第一堆叠件相配套;以及
接触焊盘,位于所述衬底的第二面上。
10.根据权利要求9所述的半导体器件,其中,所述第一多个堆叠衬底包括集成电路管芯。
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Also Published As
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US9653427B2 (en) | 2017-05-16 |
KR101753458B1 (ko) | 2017-07-03 |
US20150228550A1 (en) | 2015-08-13 |
KR20150095553A (ko) | 2015-08-21 |
US20160172333A1 (en) | 2016-06-16 |
US9281254B2 (en) | 2016-03-08 |
CN104851814B (zh) | 2018-06-08 |
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