TWI469330B - 半導體裝置及電子設備 - Google Patents

半導體裝置及電子設備 Download PDF

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Publication number
TWI469330B
TWI469330B TW97135189A TW97135189A TWI469330B TW I469330 B TWI469330 B TW I469330B TW 97135189 A TW97135189 A TW 97135189A TW 97135189 A TW97135189 A TW 97135189A TW I469330 B TWI469330 B TW I469330B
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TW
Taiwan
Prior art keywords
layer
substrate
equal
semiconductor device
single crystal
Prior art date
Application number
TW97135189A
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English (en)
Chinese (zh)
Other versions
TW200935594A (en
Inventor
大沼英人
飯窪陽一
山本孔明
牧野賢一郎
下村明久
比嘉榮二
溝井達也
永野庸治
井坂史人
掛端哲彌
山崎舜平
Original Assignee
半導體能源研究所股份有限公司
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Application filed by 半導體能源研究所股份有限公司 filed Critical 半導體能源研究所股份有限公司
Publication of TW200935594A publication Critical patent/TW200935594A/zh
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Publication of TWI469330B publication Critical patent/TWI469330B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
TW97135189A 2007-09-14 2008-09-12 半導體裝置及電子設備 TWI469330B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007240219 2007-09-14

Publications (2)

Publication Number Publication Date
TW200935594A TW200935594A (en) 2009-08-16
TWI469330B true TWI469330B (zh) 2015-01-11

Family

ID=40452070

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97135189A TWI469330B (zh) 2007-09-14 2008-09-12 半導體裝置及電子設備

Country Status (6)

Country Link
US (1) US20090072343A1 (enExample)
JP (1) JP5577027B2 (enExample)
KR (1) KR20100065145A (enExample)
CN (2) CN102646698B (enExample)
TW (1) TWI469330B (enExample)
WO (1) WO2009035063A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI915517B (zh) 2021-02-19 2026-02-21 日商信越化學工業股份有限公司 複合晶圓及其製造方法

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US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5688203B2 (ja) * 2007-11-01 2015-03-25 株式会社半導体エネルギー研究所 半導体基板の作製方法
US8513090B2 (en) * 2009-07-16 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate, and semiconductor device
JP5549167B2 (ja) * 2009-09-18 2014-07-16 住友電気工業株式会社 Ｓａｗデバイス
WO2011034136A1 (ja) * 2009-09-18 2011-03-24 住友電気工業株式会社 基板、基板の製造方法、ｓａｗデバイスおよびデバイス
FR2952224B1 (fr) 2009-10-30 2012-04-20 Soitec Silicon On Insulator Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.
CN110718557B (zh) 2010-03-08 2023-12-26 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
KR101845480B1 (ko) 2010-06-25 2018-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
WO2012033125A1 (ja) 2010-09-07 2012-03-15 住友電気工業株式会社 基板、基板の製造方法およびｓａｗデバイス
US8987728B2 (en) 2011-03-25 2015-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN105931967B (zh) 2011-04-27 2019-05-03 株式会社半导体能源研究所 半导体装置的制造方法
WO2013057771A1 (ja) * 2011-10-21 2013-04-25 株式会社島津製作所 薄膜トランジスタの製造方法
JPWO2013057771A1 (ja) * 2011-10-21 2015-04-02 株式会社島津製作所 薄膜トランジスタの製造方法
FR2985369B1 (fr) * 2011-12-29 2014-01-10 Commissariat Energie Atomique Procede de fabrication d'une structure multicouche sur un support
CN103295878B (zh) * 2012-02-27 2016-05-25 中芯国际集成电路制造(上海)有限公司 一种多层纳米线结构的制造方法
JP6340205B2 (ja) * 2014-02-20 2018-06-06 株式会社荏原製作所 研磨パッドのコンディショニング方法及び装置
JP2015233130A (ja) 2014-05-16 2015-12-24 株式会社半導体エネルギー研究所 半導体基板および半導体装置の作製方法
CN114655953B (zh) * 2014-08-08 2024-07-23 住友电气工业株式会社 制造金刚石的方法、金刚石、金刚石复合基板、金刚石接合基板和工具
JP6822146B2 (ja) * 2015-01-16 2021-01-27 住友電気工業株式会社 半導体基板の製造方法及び複合半導体基板の製造方法
CN106249947B (zh) * 2016-07-22 2019-04-19 京东方科技集团股份有限公司 一种基板及显示装置
FR3062398B1 (fr) * 2017-02-02 2021-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat pour la croissance d'un film bidimensionnel de structure cristalline hexagonale
CN112272920B (zh) * 2018-06-22 2021-11-16 日本碍子株式会社 接合体及弹性波元件
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
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JP2024016305A (ja) * 2020-12-18 2024-02-07 Ａｇｃ株式会社 接合用ガラス体、及び接合体
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
TWI915517B (zh) 2021-02-19 2026-02-21 日商信越化學工業股份有限公司 複合晶圓及其製造方法

Also Published As

Publication number Publication date
WO2009035063A1 (en) 2009-03-19
TW200935594A (en) 2009-08-16
CN102646698A (zh) 2012-08-22
CN101796613B (zh) 2012-06-27
KR20100065145A (ko) 2010-06-15
JP2009088497A (ja) 2009-04-23
CN101796613A (zh) 2010-08-04
CN102646698B (zh) 2015-09-16
US20090072343A1 (en) 2009-03-19
JP5577027B2 (ja) 2014-08-20

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