KR20100065145A - 반도체 장치 및 전자 기기 - Google Patents

반도체 장치 및 전자 기기 Download PDF

Info

Publication number
KR20100065145A
KR20100065145A KR1020107002910A KR20107002910A KR20100065145A KR 20100065145 A KR20100065145 A KR 20100065145A KR 1020107002910 A KR1020107002910 A KR 1020107002910A KR 20107002910 A KR20107002910 A KR 20107002910A KR 20100065145 A KR20100065145 A KR 20100065145A
Authority
KR
South Korea
Prior art keywords
layer
substrate
semiconductor layer
single crystal
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020107002910A
Other languages
English (en)
Korean (ko)
Inventor
히데토 오누마
요이치 이이쿠보
요시아키 야마모토
켄이치로 마키노
아키히사 시모무라
에이지 히가
타츠야 미조이
요지 나가노
후미토 이사카
테츠야 가케하타
순페이 야마자키
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20100065145A publication Critical patent/KR20100065145A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
KR1020107002910A 2007-09-14 2008-09-05 반도체 장치 및 전자 기기 Ceased KR20100065145A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2007-240219 2007-09-14
JP2007240219 2007-09-14

Publications (1)

Publication Number Publication Date
KR20100065145A true KR20100065145A (ko) 2010-06-15

Family

ID=40452070

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020107002910A Ceased KR20100065145A (ko) 2007-09-14 2008-09-05 반도체 장치 및 전자 기기

Country Status (6)

Country Link
US (1) US20090072343A1 (enExample)
JP (1) JP5577027B2 (enExample)
KR (1) KR20100065145A (enExample)
CN (2) CN101796613B (enExample)
TW (1) TWI469330B (enExample)
WO (1) WO2009035063A1 (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7371605B2 (en) * 2005-03-25 2008-05-13 Lucent Technologies Inc. Active organic semiconductor devices and methods for making the same
US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5688203B2 (ja) * 2007-11-01 2015-03-25 株式会社半導体エネルギー研究所 半導体基板の作製方法
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8513090B2 (en) * 2009-07-16 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate, and semiconductor device
US20120231218A1 (en) * 2009-09-18 2012-09-13 Sumitomo Electric Industries, Ltd. Substrate, manufacturing method of substrate, saw device and device
JP5549167B2 (ja) * 2009-09-18 2014-07-16 住友電気工業株式会社 Ｓａｗデバイス
FR2952224B1 (fr) 2009-10-30 2012-04-20 Soitec Silicon On Insulator Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.
CN106449649B (zh) 2010-03-08 2019-09-27 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
KR101845480B1 (ko) 2010-06-25 2018-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
WO2012033125A1 (ja) 2010-09-07 2012-03-15 住友電気工業株式会社 基板、基板の製造方法およびｓａｗデバイス
US8987728B2 (en) 2011-03-25 2015-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN102760697B (zh) 2011-04-27 2016-08-03 株式会社半导体能源研究所 半导体装置的制造方法
WO2013057771A1 (ja) * 2011-10-21 2013-04-25 株式会社島津製作所 薄膜トランジスタの製造方法
JPWO2013057771A1 (ja) * 2011-10-21 2015-04-02 株式会社島津製作所 薄膜トランジスタの製造方法
FR2985369B1 (fr) * 2011-12-29 2014-01-10 Commissariat Energie Atomique Procede de fabrication d'une structure multicouche sur un support
CN103295878B (zh) * 2012-02-27 2016-05-25 中芯国际集成电路制造(上海)有限公司 一种多层纳米线结构的制造方法
JP6340205B2 (ja) * 2014-02-20 2018-06-06 株式会社荏原製作所 研磨パッドのコンディショニング方法及び装置
JP2015233130A (ja) 2014-05-16 2015-12-24 株式会社半導体エネルギー研究所 半導体基板および半導体装置の作製方法
US10584428B2 (en) * 2014-08-08 2020-03-10 Sumitomo Electric Industries, Ltd. Method of manufacturing diamond, diamond, diamond composite substrate, diamond joined substrate, and tool
US10304739B2 (en) 2015-01-16 2019-05-28 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor substrate, semiconductor substrate, method for manufacturing combined semiconductor substrate, combined semiconductor substrate, and semiconductor-joined substrate
CN106249947B (zh) * 2016-07-22 2019-04-19 京东方科技集团股份有限公司 一种基板及显示装置
FR3062398B1 (fr) * 2017-02-02 2021-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat pour la croissance d'un film bidimensionnel de structure cristalline hexagonale
KR102287003B1 (ko) * 2018-06-22 2021-08-09 엔지케이 인슐레이터 엘티디 접합체 및 탄성파 소자
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
JP2024016305A (ja) * 2020-12-18 2024-02-07 Ａｇｃ株式会社 接合用ガラス体、及び接合体
CN113381286B (zh) * 2021-06-02 2023-03-03 山东大学 离子束增强腐蚀制备晶体薄膜的方法
WO2023014616A1 (en) 2021-08-02 2023-02-09 Invensas Bonding Technologies, Inc. Protective semiconductor elements for bonded structures

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
JPH0590117A (ja) * 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JPH07109573A (ja) * 1993-10-12 1995-04-25 Semiconductor Energy Lab Co Ltd ガラス基板および加熱処理方法
JPH07335511A (ja) * 1994-06-13 1995-12-22 Nippon Telegr & Teleph Corp <Ntt> 張り合わせウエハ
EP1037272A4 (en) * 1997-06-19 2004-07-28 Asahi Chemical Ind SILICON ON ISOLATOR (SOI) SUBSTRATE AND SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6103599A (en) * 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000081848A (ja) * 1998-09-03 2000-03-21 Semiconductor Energy Lab Co Ltd 液晶表示装置を搭載した電子機器
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4379943B2 (ja) * 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
JP2001144275A (ja) * 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウエーハの製造方法および貼り合わせｓｏｉウエーハ
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
WO2001028000A1 (en) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Method for manufacturing soi wafer, and soi wafer
JP2002094078A (ja) * 2000-06-28 2002-03-29 Semiconductor Energy Lab Co Ltd 半導体装置
TW504846B (en) * 2000-06-28 2002-10-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
JP2002134375A (ja) * 2000-10-25 2002-05-10 Canon Inc 半導体基体とその作製方法、および貼り合わせ基体の表面形状測定方法
JP4507395B2 (ja) * 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6855584B2 (en) * 2001-03-29 2005-02-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7253032B2 (en) * 2001-04-20 2007-08-07 Semiconductor Energy Laboratory Co., Ltd. Method of flattening a crystallized semiconductor film surface by using a plate
JP4439789B2 (ja) * 2001-04-20 2010-03-24 株式会社半導体エネルギー研究所 レーザ照射装置、並びに半導体装置の作製方法
JP4024508B2 (ja) * 2001-10-09 2007-12-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7084046B2 (en) * 2001-11-29 2006-08-01 Shin-Etsu Handotai Co., Ltd. Method of fabricating SOI wafer
WO2003049189A1 (en) * 2001-12-04 2003-06-12 Shin-Etsu Handotai Co.,Ltd. Pasted wafer and method for producing pasted wafer
JP2003209259A (ja) * 2002-01-17 2003-07-25 Fujitsu Ltd 半導体装置の製造方法及び半導体チップ
JP2004014856A (ja) * 2002-06-07 2004-01-15 Sharp Corp 半導体基板の製造方法及び半導体装置の製造方法
JP2004087535A (ja) * 2002-08-22 2004-03-18 Sony Corp 結晶質半導体材料の製造方法および半導体装置の製造方法
CN100499035C (zh) * 2003-10-03 2009-06-10 株式会社半导体能源研究所 半导体器件的制造方法
US7170176B2 (en) * 2003-11-04 2007-01-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4748967B2 (ja) * 2003-11-04 2011-08-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4759919B2 (ja) * 2004-01-16 2011-08-31 セイコーエプソン株式会社 電気光学装置の製造方法
JP2005217209A (ja) * 2004-01-30 2005-08-11 Hitachi Ltd レーザアニール方法およびレーザアニール装置
KR20120096586A (ko) * 2004-10-20 2012-08-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 제조방법
JP2006148086A (ja) * 2004-10-20 2006-06-08 Semiconductor Energy Lab Co Ltd レーザ照射方法、レーザ照射装置、および半導体装置の作製方法
JP2006303201A (ja) * 2005-04-21 2006-11-02 Sumco Corp Ｓｏｉ基板の製造方法
JP2007173354A (ja) * 2005-12-20 2007-07-05 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
JP2007220782A (ja) * 2006-02-15 2007-08-30 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
US7741687B2 (en) * 2006-03-10 2010-06-22 Semiconductor Energy Laboratory Co., Ltd. Microstructure, semiconductor device, and manufacturing method of the microstructure
JP2007201502A (ja) * 2007-04-20 2007-08-09 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate

Also Published As

Publication number Publication date
CN102646698B (zh) 2015-09-16
TW200935594A (en) 2009-08-16
JP2009088497A (ja) 2009-04-23
WO2009035063A1 (en) 2009-03-19
TWI469330B (zh) 2015-01-11
CN101796613B (zh) 2012-06-27
JP5577027B2 (ja) 2014-08-20
CN101796613A (zh) 2010-08-04
US20090072343A1 (en) 2009-03-19
CN102646698A (zh) 2012-08-22

Similar Documents

Publication Publication Date Title
JP5577027B2 (ja) 半導体装置の作製方法並びに半導体装置及び電子機器
KR101434934B1 (ko) Ｓｏｉ 기판의 제작 방법, 및 반도체 장치의 제작 방법
JP5383143B2 (ja) 半導体基板の作製方法および半導体装置の作製方法
TWI437696B (zh) 半導體裝置及其製造方法
US8247307B2 (en) Manufacturing method of substrate provided with semiconductor films
CN101393859B (zh) 设置有半导体膜的衬底及其制造方法
JP5523693B2 (ja) 半導体基板の作製方法
TWI476870B (zh) Ｓｏｉ基板的製造方法
KR101478813B1 (ko) 반도체 장치의 제조 방법
US7790572B2 (en) Method for manufacturing semiconductor substrate
TWI437662B (zh) Ｓｏｉ基板的製作方法
US20090004821A1 (en) Manufacturing method of soi substrate and manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20100209

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
AMND Amendment
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20130905

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20141124

Patent event code: PE09021S01D

AMND Amendment
PE0601 Decision on rejection of patent

Patent event date: 20150415

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20141124

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

Patent event date: 20150515

Comment text: Request for Trial against Decision on Refusal

Patent event code: PJ02012R01D

Patent event date: 20150415

Comment text: Decision to Refuse Application

Patent event code: PJ02011S01I

Appeal kind category: Appeal against decision to decline refusal

Decision date: 20161222

Appeal identifier: 2015101002686

Request date: 20150515

AMND Amendment
PB0901 Examination by re-examination before a trial

Comment text: Amendment to Specification, etc.

Patent event date: 20150612

Patent event code: PB09011R02I

Comment text: Request for Trial against Decision on Refusal

Patent event date: 20150515

Patent event code: PB09011R01I

Comment text: Amendment to Specification, etc.

Patent event date: 20150126

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20130905

Patent event code: PB09011R02I

B601 Maintenance of original decision after re-examination before a trial
PB0601 Maintenance of original decision after re-examination before a trial

Comment text: Report of Result of Re-examination before a Trial

Patent event code: PB06011S01D

Patent event date: 20150713

J301 Trial decision

Free format text: TRIAL NUMBER: 2015101002686; TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20150515

Effective date: 20161222

PJ1301 Trial decision

Patent event code: PJ13011S01D

Patent event date: 20161222

Comment text: Trial Decision on Objection to Decision on Refusal

Appeal kind category: Appeal against decision to decline refusal

Request date: 20150515

Decision date: 20161222

Appeal identifier: 2015101002686