TWI421987B - 晶圓級積體封裝 - Google Patents

晶圓級積體封裝 Download PDF

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Publication number
TWI421987B
TWI421987B TW097115852A TW97115852A TWI421987B TW I421987 B TWI421987 B TW I421987B TW 097115852 A TW097115852 A TW 097115852A TW 97115852 A TW97115852 A TW 97115852A TW I421987 B TWI421987 B TW I421987B
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TW
Taiwan
Prior art keywords
wafer
semiconductor
package
contact pad
electrical contact
Prior art date
Application number
TW097115852A
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English (en)
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TW200901411A (en
Inventor
Heap Hoe Kuan
Seng Guan Chow
Linda Pei Ee Chua
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Stats Chippac Ltd
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Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200901411A publication Critical patent/TW200901411A/zh
Application granted granted Critical
Publication of TWI421987B publication Critical patent/TWI421987B/zh

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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Description

晶圓級積體封裝
本發明一般係關於半導體元件，且更特別地係關於半導體封裝元件。
半導體，或是電腦晶片實際上係於現今所製造每個電器產品中發現。(多個)晶片係被不僅被用在複雜的工業與商業電子設備中，而且被用在諸如電視、洗衣機與烘衣機、無線電、以及電話的許多家庭用與消費項目上。當(多個)產品變為越小型且更多功能時，係有一將更多晶片包含入該等更小型產品的需要，以實行該功能性。在手機大小上的降低係為更多性能如何地被納入(多個)小型電子產品的一個實例。
當對於具有低成本、高效能、提高微型化、以及高封裝密度的需求已增加時，具有諸如多晶片模組(Multi-Chip Module MCM)結構之多個晶片或是類似經堆疊晶片結構的(多個)元件係已被發展出以符合該需求。MCM結構係具有一些晶片以及被黏著於一單一半導體封裝內的其他半導體構件。該些晶片與其他構件係能以一垂直方式、以一橫向方式、或是其之組合來被黏著。
一個此方法係為：將一個晶片堆疊在另一個晶片的上面，且接著將該晶片堆疊封入一個封裝中。對於具有經堆疊晶片之一半導體的最後封裝係遠小於各個該等晶片被分 別地封裝的結果。除了提供小型尺寸之外，經堆疊晶片封裝係給予一些關於製造該封裝的好處，其諸如容易處理以及組裝。
在一經堆疊晶片佈置中，該等晶片係循序地被銲線接合(wire-bonded)，其典型地具有運用已知熱壓縮或是超音速銲線接合的自動銲線接合設備。在該銲線接合過程中，一銲線銲接裝置之頭係一導引線上施加一向下壓力至在該晶片上之接合銲墊，其中該導引線係與一在該晶片上的銲線接合銲墊保持相接觸以銲接(weld)或是接合(bond)該引線。
在許多情況中，經堆疊晶片半導體係能比數個半導體更快速地且更便宜地被製造，其中該等數個半導體中每一個係具有一實行相同(多個)功能的單一晶片。一經堆疊晶片方法係有利的，其係由於達成在電路密度上的提高以及於相同封裝內實行不同功能性(例如，記憶體、邏輯運算、特定應用積體電路(ASIC))的能力。所以，如包含球狀閘陣列封裝(Ball Grid Array，BGA)、覆晶(flip chip)(經凸塊(bumped))元件)、以及晶圓級封裝(WLCSP)之晶片尺度封裝(Chip Scale Packaging，CSP)的此多個晶片封裝係已被實施。再者，使用諸如系統級封裝(System-in-Package，Sip)以及晶片尺度模組封裝(chip scale module packaging，CSMP)之多個技術來與數個被動元件一起整合係已經常被使用的。
然而，對於使用先前所討論各種技術來達成較高整合 的希望通常係引起一最後封裝結構在足跡上不是更大就是更厚。高整合通常係已造成犧牲封裝微型化的權衡。
因此，係存在對於允許具有不同功能性之較高件整合且還維持或是減少該封裝外形之一封裝的需要。
於是，在一個實施例中，本發明係一種形成一半導體封裝的方法，該半導體封裝係包含下列步驟：係提供一具有一被整合至該晶圓之一頂表面的第一電氣接觸銲墊之晶圓、係形成一自該第一電氣接觸銲墊(pad)之一第一表面延伸向下的穿孔互連(through-hole interconnection)、係將一晶片電氣連接至該第一電氣接觸銲墊之一第二表面、係切割該晶圓以形成一通道部分以及一連接部分、係置放一封裝材料(encapsulant)於該晶片以及該通道部分上、係研磨(backgrinding)該晶圓以移除該連接部分並且以曝光該穿孔互連的一表面、係將一第二電氣接觸銲墊置放於該穿孔互連的表面上、以及係將一介電層沿著該第二電氣接觸銲墊之一側表面來置放。
在另一個實施例中，本發明係一具有一晶圓的半導體封裝，其中該晶圓係具有一被整合至該晶圓之一頂表面的第一電氣接觸銲墊。一穿孔互連係自該第一電氣接觸銲墊之一第一表面延伸向下。一晶片係被電氣連接至該第一電氣接觸銲墊之一第二表面。一第二電氣接觸銲墊係被置放於該穿孔互連的一表面上。一介電層係沿著該第二電氣接 觸銲墊之一側表面被置放。該晶圓係被切割以形成一通道部分以及一連接部分。一封裝材料係被置放於該晶片以及該通道部分上。該晶圓係被研磨以移除該連接部分並且以曝光該穿孔互連的表面。
在另一個實施例中，本發明係一具有一晶圓的半導體封裝，其中該晶圓係具有一被整合至該晶圓之一頂表面的第一電氣接觸銲墊。一穿孔互連係自該第一電氣接觸銲墊之一第一表面延伸向下。一第一晶片係被電氣連接至該第一電氣接觸銲墊之一第二表面。一第二電氣接觸銲墊係被置放於該穿孔互連的一表面上。一介電層係沿著該第二電氣接觸銲墊之一第一表面被置放。一第二晶片係被電氣連接至該第二電氣接觸銲墊之一第二表面。該晶圓係被切割以形成一通道部分以及一連接部分。一第一封裝材料係被置放於該晶片以及該通道部分上。該晶圓係被研磨以移除該連接部分並且以曝光該穿孔互連的表面。
在另一個實施例中，本發明係一種製造一半導體元件的方法，該半導體元件係包含下列步驟:係提供一具有一被整合至該晶圓之一頂表面的第一電氣接觸銲墊之晶圓、係提供一自該第一電氣接觸銲墊之一第一表面延伸向下的穿孔互連、係提供一被電氣連接至該第一電氣接觸銲墊之一第二表面的晶片、係提供一被置放於該穿孔互連之一表面上的第二電氣接觸銲墊、係提供一沿著該第二電氣接觸銲墊之一側表面被置放的介電層。該晶圓係被切割以形成一通道部分以及一連接部分。一封裝材料係被置放於該晶片 以及該通道部分上。該晶圓係被研磨以移除該連接部分並且以曝光該穿孔互連的一表面。
本發明係被敘述在下文關於該等圖式之描述的一個或更多實施例中，其中相同的元件符號係代表相同或是類似的元件。儘管本發明係以用於達成本發明目的之最佳模式的角度來敘述，熟習本項技術人士仍將理解到係打算包括如可被包含於本發明之精神與範疇內的替代例、修改例、以及對等例，其中本發明之精神與範疇係如由該等下述揭示內容與圖式所支持的該等後附申請專利範圍以及其對等歷來定義。
一半導體封裝係能以考慮一經堆疊晶片佈置以及滿足減輕許多先前所述問題的方式而被製造，而提供越來越小尺寸。該封裝係能更容易地被製造且具有比先前封裝更高的效率，造成一整體上具有較低製造成本的封裝。最後，具有經堆疊晶片的半導體封裝之可靠度係藉由使用下述設計以及製造方法來增加。
翻至圖1A，一示範性先前技術之半導體元件10係被說明。元件10係包含一晶圓或是一基板12，該基板係具有一頂表面16以及一底表面14。一罩(cap)係被置放在該頂表面上以封閉電器構件24。一介電襯料(liner)20係透過在晶圓12中之自一頂表面延伸至一底表面的一通路(via)來置放。該通路係以如所示導電材料22來填充。
圖1B以及1C係進一步說明該通路結構之各種先前技術的實施例。在圖1B中，基板26係包含一底表面28以及一頂表面34。一導電材料30係被置放在表面32之間，該等表面係被置放在晶圓26中的溝渠(trenches)裡。相同地，圖1C係另一個具有一底表面38以及一頂表面44的晶圓，其中一導電材料42係被置放在表面內，該等表面係作為在該晶圓中之該等通道的襯裡。
本發明係在此等如在先前技術所見之方法以及技術上作出改善，以給予一半導體元件在高度與足跡上係更小、更有效率的來製造、以及造成較高效能。
圖2A係根據本發明說明一在一形成一半導體元件之示範性方法中的第一步驟。一晶圓50係具有一矽基板。晶圓以及相似的基板係能被提供，其對於一特別應用係在尺寸與深度上作出變化。
一開始於圖2A之在形成一半導體元件的示範性方法中之第二步驟係被顯示於圖2B中。一連續電氣接觸銲墊52係被形成作為重分布層(redistribution layers，RDLs)或是晶圓凸塊(flex-on-cap，FOC)過程。FOC係牽涉到實際上將銲錫球(solder ball)直接地置放在一凸塊底層金屬(under-bump metallization，UBM)上，其係將一接合銲墊躺至一晶圓。儘管該銲錫球係藉由該RDL軌跡而保持電氣連接至該接合銲墊，RDL係仍牽涉側面地將該銲錫球之位置分離自該晶圓接合銲墊。在任一個情況中，銲墊52係被整合至晶圓50之一頂表面。
一在該示範性方法之第三步驟係於圖2C中所見，其中一連續銲線接合係被形成在基板50上。該等互連54係能在該基板上被蝕刻並且以一導電材料來填充，或是相似的技術能被利用。在各種實施例中，該等通孔互連係能延伸至在30至150微米(um)之間變化的深度。
如在該示範性方法中的下一個第四步驟，一覆晶或是晶片58(諸如，一經銲線接合晶片)係被附接至銲線接合54。一連續凸塊係能提供從晶片58至穿孔互連54的電氣連接性。一選擇性充填(underfill)材料56係能被置放在晶片58與該基板50的頂表面之間。
於第四步驟的結論，一連續晶圓58係被電氣連接至複數個穿孔互連54其係部分地被置放通過晶圓50。再次，如圖2D係代表一部分橫斷面，晶圓58之任何數目係能以適合特殊應用之各種組態來提供
圖2係代表一在形成一半導體元件之示範性方法的第五步驟。如所示，一連續通道、溝渠或是空隙(voids)62係被形成在互連54、銲墊51、以及晶圓58的各別組件中各一者之間。在晶片58以及互連54與銲墊52之間的該等各種電氣連接及支援機制係能包含凸塊60及/或充填材料56。
一封裝材料64係被置放於如圖2F中所見之該等各別組件，其中該圖2F係描述一在形成一半導體元件之示範性方法的第六步驟。封裝材料64係塗層在晶片58的各別表面、選擇性充填材料56、以及晶圓50的表面。該等通 道62中每一者係以封裝材料64來填充。封裝材料64係能包含聚合物材料、有機材料、或是其他封裝材料。封裝材料64係將結構支援提供至該半導體元件中的該等各種構件(例如，晶片58)。
在形成一圖2G所描述之半導體元件的示範性方法之一第七步驟中的晶圓50係經歷一研磨作業，以移除來自晶圓50之一底部分或是背部分的材料。其中一旦晶圓結構50之連接部分被移除時(如由箭頭68所表示)，表面70係產生於該研磨作業。該等各別組件中每一者係保持被連接於封裝材料64的一層。
穿孔互連54之一底表面係藉由該研磨過程的使用被曝光出。如圖2F與2G中所見，通道62係被形成以粗略地對應於該等複數個互連54之深度，以便當晶圓50之該等連接部分被移除時，互連54之表面66係被曝光出。
圖2H係說明接下來一在形成一半導體元件之示範性方法中的第八步驟。複數個背側銲墊72係被電氣接至互連54之表面66。銲墊72係能以絕大部分相同的方式來形成，其中該方式係如先前所見使用RDL或是FOC而被整合至晶圓50之一頂側的銲墊52。一介電層74係沿著該晶圓之背側或是底表面70而被置放。介電層74係沿著銲墊72之一側表面而被置放。層74係圍繞且係隔絕銲墊72並且係提供跨越於晶圓50之底表面70的結構性支持。
一連續銲錫球78係接著能被附接或是用其他方法被耦合及/或被連接至在接下來一第九步驟中之銲墊72中每一 者，其中該步驟係在形成一半導體元件之經描述示範性方法裡。該等組件中每一者係能選擇性地被功能測試，以決定是否各別電氣連結係令人滿意地被製造。
如一最後步驟，該等各別組件80中每一者接著係能被分離(singulate)成如圖2I中所見之半導體元件80。在一個實施例中，該最後半導體元件80係包含一球78，其係將半導體元件80電氣連接至另一個結構。背側銲墊72係被耦合至穿孔互連54，並且係被耦合至上側銲墊52。一晶片58係使用凸塊60而被連接至上側銲墊52且係藉由充填材料56來固定。
在形成半導體元件80之一個示範性方法中，一晶圓首先係能被提供為具有一連續被整合至該晶圓之一頂表面的第一電氣接觸銲墊。一穿孔互連接著係能被形成為自該第一電氣接觸銲墊之一第一表面延伸向下。一晶片接著係能被附接至該等第一電氣接觸銲墊之一第二表面。該晶圓係能被切割以形成一通道部分以及一連接部分。一封裝材料接著係能被置放於該晶片以及該通道部分上。該晶圓接著係能經過一研磨過程以移除該連接部分並且以曝光該穿孔互連的一表面。一第二連續第電氣接觸銲墊係能被置放於該穿孔互連的表面上。一介電層係沿著該等第二銲墊之一側表面。一球接著係能被耦合至該等第二銲墊以提供電氣連接性。
翻至圖3，一納入一覆晶IC晶片58之一半導體元件80的第一示範性實例係被看到。元件80係能被稱為一晶圓 級積體封裝元件80。元件80係包含諸如先前所提及結構的銲墊52、選擇性充填層56、凸塊60、封裝材料64、銲墊72、介電層74、以及球78。
除了該等前文提及結構之外，元件80係包含一被動構件(諸如，一濾波器、匹配器、電感器、電容器、電阻器、或是一相似電氣元件82)，該被動構件係如所示的被整合至元件80內且係透過銲墊52之一部分而被電氣連接至該元件。該嵌入式被動構件係能實行諸如電容、電感、電阻、或是一功能組合的功能性。
在該實施例中之晶圓結構50係納入一雙面積體電路84。該雙面積體電路84係一主動積體電路元件84。元件84係能實行諸如邏輯運算、記憶、特定應用程式(ASIC)、或是嵌入式積體被動元件(IPD)的功能性。該雙面積體電路係能作用為一半導體中介層(interposer)、其在於該晶圓係能提供結構性支持而沒有提供額外的電子功能性，且還作用以提供電氣訊號從一來源散佈至一終端。
元件84係能將數個訊號安排在該元件之頂表面與底表面兩者上的路線中。該等訊號路線係能藉由具有沿著該X一Y方向之單一或多重銲墊52以及72而被提供。一連續穿孔互連54係將該等訊號安排在沿著該Z方向的路線中。
元件84係包含各種互聯銲墊以容納諸如引線、凸塊、以及將要進一步被敘述之其它被動構件互連的訊號轉換媒介。元件84係能包含矽(Si)、砷化鎵(gallium aresnide GaAs)、或是任何其他合適半導體材料、或是其之一組合。 該雙面積體電路84之側牆係由封裝材料64(如由箭頭86所表示)所保護。所以，該晶圓級積體元件80係更可靠的且特別對處理步驟更有彈性的被製造。
諸如封裝/元件80的晶圓級積體封裝係能包含單一或多個積體電路(IC)元件，其係能被附接至該雙面積體電路元件84之一頂側或是一底側。該等IC元件係能為可銲線接合的、覆晶、被動構件、或是其之一組合。該等IC元件係能以一並排方式(side-by-side)的組態方式或是藉由堆疊而來佈置。該等各種組態係可應用在該雙面積體電路元件84之各別頂側或是底側兩者。
封裝/元件80係能被用作為一用於如將在之後所述封裝內封裝組態的內部堆疊模組(inner stacking module，ISM)。封裝/元件80亦能被用作為一傳統球狀柵極陣列(BGA)封裝80藉此封裝80係能被附接至一用於將來封裝及/或測試的基板。
翻至圖4，一晶圓級積體封裝88之一第二示範性實例係被顯示。封裝88係包含一如前所見的被動元件82。如所組態且所形成之介電層74係給予一連續曝光銲墊72的地(land)90。該等地90係能被打算以提供特殊應用之電氣連接性。該等地90係能以各種組態方式形成，以將各別銲墊72之一部分曝光的如同所需一樣多或是一樣少。
圖5係說明一晶圓級積體封裝92之一額外第三實施例，其中該經納入覆晶IC 58係具有一經曝光頂表面94。在本實施例中，封裝材料64係被形成使得覆晶IC 58之頂 表面係被曝光以用於一特殊應用中，其諸如來提供一較小較薄的封裝92。封裝材料64係被置放使得該表面94係被曝光，或是該表面94係能之後透過一研磨程序或是一相似的機械操作而被曝光，以降低封裝材料64的覆蓋範圍。
作為一熱增強晶圓級積體封裝96之該經曝光表面封裝92的一變化係在圖6中所見，其中一膠黏材料98係被置放在晶片58的頂表面上。該膠黏劑係將一散熱器耦合至晶片58之頂表面，以將熱散逸跨過該封裝的頂表面。該散熱器100亦能納入其它熱特徵以增強封裝96在某些情況下的整體效能。
圖7係說明一晶圓級積體封裝102，其係納入一電氣屏蔽結構106。該電氣屏蔽結構106係使用一膠黏結構104而被耦合至晶圓50的一部分，以及係圍繞與屏蔽著電氣構件，亦即，棲身於屏蔽結構106內部的晶片58及/或其它被動構件82。結構106以及膠黏底座104係被封裝材料64所圍繞，以對封裝102提供額外的結構性支持。該屏蔽係由具有孔洞(hole)以允許封裝之金屬罩所製成。該屏蔽係避免在該封裝內以及封裝外的元件之間的訊號干擾。任何干擾係將使訊號傳送失真，其在RF應用上係能為有問題的。
圖8係說明一納入一可銲線接合晶片110之晶圓級積體封裝108的一額外實施例，其係由引線112連接至銲線接合銲墊114。銲線接合銲墊114係以一相似於銲墊52之方式而被整合至晶圓50之上側。銲墊52係能被修改以接 受如所指示的銲線接合。銲線接合IC 110以及引線112係以封裝材料64來覆蓋以提供結構性支持。
在一額外實施例中，圖9係說明一晶圓級積體封裝80，其接著係被置放在一經凸塊基板上以給予一封裝內封裝(Package-in-Package，PiP)118組態。封裝80係作為一用於PiP實施之如先前所述的ISM。
一晶圓膠黏劑120係被利用以將該晶圓級積體封裝80黏著於一經凸塊基板112的一表面。一連續通路或是類似結構係將電氣訊號運載通過基板112至一連續球78其係被置放在基板112之一底表面。
一額外晶片或是封裝124係被置放在元件80上。晶片或是封裝124係使用凸塊130而被電氣連接元件80。一凸塊銲墊72係將電氣訊號運載越過一引線112至經凸塊基板122的一電氣終端126。
一第二封裝材料132係被置放在封裝80以及封裝124或是如所見之晶片124上，以形成一完整封裝內封裝組態118。各種晶片或是封裝124係能與元件80合併以適用一特殊應用。
儘管本發明之一個或更多實施例係已被詳細說明，熟習本項技術人士仍將理解到，對於該些實施例的更改與修改係可被作出而沒有悖離如在下述該等申請專利範圍中所提及之本發明的精神。
10,80‧‧‧半導體元件
12,26,50‧‧‧晶圓或是基板
14,28,38,66‧‧‧底表面
16,34,44,94‧‧‧頂表面
18‧‧‧罩
20‧‧‧介電襯料
22,30,42‧‧‧導電材料
24‧‧‧電氣構件
32,40,70‧‧‧表面
52‧‧‧電氣接觸銲墊
54‧‧‧穿孔互連
56‧‧‧充填材料
58‧‧‧晶片
60‧‧‧凸塊
62‧‧‧空隙、通道
64‧‧‧封裝材料
68,86‧‧‧箭頭
72‧‧‧背側銲墊
74‧‧‧介電層
78‧‧‧銲錫球
80‧‧‧半導體封裝/元件
82‧‧‧被動構件
84‧‧‧雙面積體電路
80,88,92,102,108‧‧‧晶圓級積體封裝
90‧‧‧地
96‧‧‧熱增強晶圓級積體封裝
98‧‧‧膠黏材料
100‧‧‧散熱器
104‧‧‧膠黏底座
106‧‧‧電氣屏蔽結構
110‧‧‧可銲線接合晶片
112‧‧‧引線
114‧‧‧可銲線接合銲墊
118‧‧‧封裝內封裝組態
120‧‧‧晶片膠黏劑
122‧‧‧經凸塊基板
124‧‧‧晶片或是封裝
126‧‧‧電氣終端
128‧‧‧通路
130‧‧‧凸塊
132‧‧‧第二封裝材料
圖1A係說明一示範性先前技術半導體元件。
圖1B係說明一第一示範性先前技術半導體基板。
圖1C係說明一第二示範性先前技術半導體基板。
圖2A係說明一在一形成一半導體元件之示範性方法中的第一步驟。
圖2B係說明一在開始於圖2A中之示範性方法裡的第二步驟。
圖2C係說明一在開始於圖2A中之示範性方法裡的第三步驟。
圖2D係說明一在開始於圖2A中之示範性方法裡的第四步驟。
圖2E係說明一在開始於圖2A中之示範性方法裡的第五步驟。
圖2F係說明一在開始於圖2A中之示範性方法裡的第六步驟。
圖2G係說明一在開始於圖2A中之示範性方法裡的第七步驟。
圖2H係說明一在開始於圖2A中之示範性方法裡的第八步驟。
圖2I係說明一在開始於圖2A中之示範性方法裡的第九步驟。
圖3係說明一納入覆晶(flip chip)積體電路之一半導體元件的第一示範性實施例。
圖4係說明一包含複數個lands之一半導體元件的第 二示範性實施例。
圖5係說明一其中一積體晶片之一頂表面被曝光出之一半導體元件的第三示範性實施例。
圖6係說明一納入散熱器(heat spreader)結構以提供熱增強之一半導體元件的第四示範性實施例。
圖7係說明一納入一電氣屏蔽結構之一半導體元件的第五示範性實施例。
圖8係說明一納入一銲線接合(wire-bonded)積體電路之一半導體元件的第六示範性實施例。
圖9係說明一運用封裝內封裝(package-in-package)技術之一半導體元件的第七示範性實施例。
50‧‧‧晶圓或是基板
52‧‧‧電氣接觸銲墊
54‧‧‧穿孔互連
56‧‧‧充填材料
58‧‧‧晶片
60‧‧‧凸塊
64‧‧‧封裝材料
70‧‧‧表面
72‧‧‧背側銲墊
74‧‧‧介電層
78‧‧‧銲錫球

Claims (37)

  1. 一種形成一半導體封裝的方法，該方法係包含：提供一具有一第一電氣接觸銲墊的晶圓，其中該第一電氣接觸銲墊係被整合至該晶圓之一頂表面；形成一自該第一電氣接觸銲墊之一第一表面延伸向下的穿孔互連；將一晶片電氣連接至該第一電氣接觸銲墊之一第二表面；切割該晶圓以形成一通道部分以及一連接部分；置放一封裝材料於該晶片以及該通道部分上；研磨該晶圓以移除該連接部分，並且曝光該穿孔互連的一表面；將一第二電氣接觸銲墊置放於該穿孔互連的表面上；以及將一介電層沿著該第二電氣接觸銲墊之一側表面來置放。
  2. 如申請專利範圍第1項之方法，其係進一步包含將一銲錫凸塊置放在該晶片與該第一電氣接觸銲墊之間，以將該晶片電氣連接至該第一電氣接觸銲墊。
  3. 如申請專利範圍第1項之方法，其係進一步包含將一充填材料置放在該晶片與該第一電氣接觸銲墊之間，以提供結構性支持。
  4. 如申請專利範圍第1項之方法，其係進一步包含將一銲錫凸塊連接至該第二電氣接觸銲墊，以提供電氣連接性。
  5. 如申請專利範圍第4項之方法，其係進一步包含測試該晶片之功能性。
  6. 如申請專利範圍第4項之方法，其係進一步包含將該晶圓分離成含有該晶片的一個別區段。
  7. 如申請專利範圍第1項之方法，其中該晶片係包含一覆晶半導體元件、一銲線接合半導體元件、一被動構件、或是其之一組合。
  8. 如申請專利範圍第1項之方法，其中該介電層係被置放以形成延伸跨越該半導體元件之一底表面的複數個地。
  9. 如申請專利範圍第1項之方法，其係進一步包含將一被動構件電氣連接至該第一電氣接觸銲墊的第一表面。
  10. 一種製造一半導體元件的方法，該製造方法係包含：提供一晶圓，其係具有一被整合至該晶圓之一頂表面的第一電氣接觸銲墊；提供一穿孔互連，其係自該第一電氣接觸銲墊之一第一表面延伸向下；提供一晶片，其係被電氣連接至該第一電氣接觸銲墊之一第二表面的；提供一第二電氣接觸銲墊，其係被置放於該穿孔互連之一表面上；以及提供一介電層，其係沿著該第二電氣接觸銲墊之一側表面被置放，其中：該晶圓係被切割以形成一通道部分以及一連接部分； 一封裝材料，其係被置放於該晶片以及該通道部分上；以及該晶圓係被研磨以移除該連接部分，並且曝光該穿孔互連的一表面。
  11. 如申請專利範圍第10項之製造方法，其係進一步包含提供一銲錫凸塊，該銲錫凸塊係被置放在該晶片與該第一電氣接觸銲墊之間，以將該晶片電氣連接至該第一電氣接觸銲墊。
  12. 如申請專利範圍第10項之製造方法，其係進一步包含提供一充填材料，該充填材料係被置放在該晶片與該第一電氣接觸銲墊之間，以提供結構性支持。
  13. 如申請專利範圍第10項之製造方法，其中該晶片係包含一覆晶半導體元件、一銲線接合半導體元件、一被動構件、或是其之一組合。
  14. 如申請專利範圍第10項之製造方法，其中該介電層係被置放在一圖樣中，以提供延伸跨越該半導體元件之一底表面的複數個地。
  15. 如申請專利範圍第10項之製造方法，其係進一步包含一被動構件，該被動構件係被電氣連接至該第一電氣接觸銲墊的第一表面。
  16. 如申請專利範圍第10項之製造方法，其中該封裝材料係被置放使得該晶片之一頂表面係被曝光。
  17. 如申請專利範圍第16項之製造方法，其係進一步包含提供一膠黏層，該膠黏層係被置放於該晶片的頂表面， 並且提供一散熱器結構，該散熱器結構係被置放於該膠黏劑上以提供一熱增強半導體封裝。
  18. 一種半導體封裝，其係包含：一雙面基板，其係具有一主動表面及對置於該主動表面之第二表面；一穿孔互連結構，其係從該主動表面延伸穿過該雙面基板至該第二表面；一第一導電層，其係形成於該主動表面上，且係電性連接至該穿孔互連結構；一半導體晶片，其係安裝於該雙面基板的該主動表面上，且係電性連接至該第一導電層；一封裝材料，其係沉積於該半導體晶片和該雙面基板上，且進一步沿著該雙面基板之一側壁從該主動表面延伸至該第二表面；一第二導電層，其係形成於該第二表面上，且係電性連接至該穿孔互連結構；以及一介電層，其係形成於建立一地之該第二表面上，以圍繞並隔絕該第二導電層。
  19. 如申請專利範圍第18項之半導體封裝，其中該半導體晶片係包含一覆晶半導體元件、一銲線接合半導體元件、或一被動構件。
  20. 如申請專利範圍第18項之半導體封裝，其係進一步包含一散熱器結構，該散熱器結構係置放於該半導體晶片上。
  21. 如申請專利範圍第18項之半導體封裝，其係進一步包含一電磁干擾屏蔽，該電磁干擾屏蔽係置放於該晶片上。
  22. 如申請專利範圍第18項之半導體封裝，其係進一步包含一被動構件，該被動構件係安裝於該雙面基板上，且係電性連接至該第一導電層。
  23. 如申請專利範圍第18項之半導體封裝，其係進一步包含複數個晶片，該複數個晶片係以一封裝內封裝配置方式來堆疊。
  24. 如申請專利範圍第18項之半導體封裝，其中該半導體晶片的一表面係從該封裝材料處曝光。
  25. 如申請專利範圍第18項之半導體封裝，其係進一步包含一充填材料，該充填材料係置放在該半導體晶片和該雙面基板之間，以提供結構性支持。
  26. 一種半導體封裝，其係包含：一雙面基板，其係具有一主動表面及對置於該主動表面之第二表面；一導電通路(via)，其係從該主動表面處形成，且係延伸穿過該雙面基板至該第二表面；一第一導電層，其係形成於該主動表面上，且係電性連接至該導電通路；一半導體構件，其係安裝於該雙面基板的該主動表面上，且係電性連接至該第一導電層和該導電通路；一封裝材料，其係沉積於該半導體構件，沉積於該雙面基板上，和沉積於沿著該雙面基板之一側面而形成之一 通道內；一第二導電層，其係形成於該第二表面上，且係電性連接至該導電通路；以及一介電層，其係形成於該第二表面上，以圍繞並隔絕該第二導電層。
  27. 如申請專利範圍第26項之半導體封裝，其中該半導體構件係包含一覆晶半導體元件、一銲線接合半導體元件、或一被動構件。
  28. 如申請專利範圍第26項之半導體封裝，其係進一步包含一散熱器結構，該散熱器結構係置放於該半導體構件上。
  29. 如申請專利範圍第26項之半導體封裝，其係進一步包含一電磁干擾屏蔽，該電磁干擾屏蔽係置放於該半導體構件上。
  30. 如申請專利範圍第26項之半導體封裝，其係進一步包含一被動構件，該被動構件係安裝於該雙面基板上，且係電性連接至該第一導電層。
  31. 如申請專利範圍第26項之半導體封裝，其係進一步包含複數個半導體構件，該複數個半導體構件係以一封裝內封裝配置方式來堆疊。
  32. 如申請專利範圍第26項之半導體封裝，其中該半導體構件的一表面係從該封裝材料處曝光。
  33. 一種半導體封裝，其係包含：一具有一晶圓形式因子之基板，其係具有一主動表面 及對置於該主動表面之第二表面；一導電通路，其係形成於該主動表面和該第二表面之間；一第一導電層，其係形成於該主動表面上，且係電性連接至該導電通路；一半導體構件，其係安裝於該基板上，且係電性連接至該第一導電層和該導電通路；一通道，其係從該主動表面上延伸而部分地穿過該基板；一封裝材料，其係沉積於該基板、該半導體構件上，並沉積進入於該通道內，其中該基板係被研磨以將該封裝材料曝光於該通道和該導電通路中；以及一互連結構，其係形成於該第二表面上。
  34. 如申請專利範圍第33項之半導體封裝，其中該互連結構係包含：一接觸銲墊，其係形成於該第二表面上，且係電性連接至該導電通路；一介電層，其係形成於該第二表面上和該接觸銲墊附近。
  35. 如申請專利範圍第33項之半導體封裝，其係進一步包含一散熱器結構，該散熱器結構係置放於該半導體構件上。
  36. 如申請專利範圍第33項之半導體封裝，其係進一步包含一電磁干擾屏蔽，該電磁干擾屏蔽係置放於該半導體 構件上。
  37. 如申請專利範圍第33項之半導體封裝，其係進一步包含一充填材料，該充填材料係置放在該半導體構件和該基板之間，以提供結構性支持。
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US20080315372A1 (en) 2008-12-25
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