TWI322490B - Die package with asymmetric leadframe connection - Google Patents

Die package with asymmetric leadframe connection Download PDF

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Publication number
TWI322490B
TWI322490B TW095123545A TW95123545A TWI322490B TW I322490 B TWI322490 B TW I322490B TW 095123545 A TW095123545 A TW 095123545A TW 95123545 A TW95123545 A TW 95123545A TW I322490 B TWI322490 B TW I322490B
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TW
Taiwan
Prior art keywords
lead frame
semiconductor
die
semiconductor die
package
Prior art date
Application number
TW095123545A
Other languages
English (en)
Other versions
TW200707678A (en
Inventor
Ming Hsun Lee
Chih Chin Liao
Cheemen Yu
Hem Takiar
Original Assignee
Sandisk Corp
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Publication date
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200707678A publication Critical patent/TW200707678A/zh
Application granted granted Critical
Publication of TWI322490B publication Critical patent/TWI322490B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

1322490 九、發明說明： 【發明所屬之技術領域】 本發明之實施例係關於一種半導體封裝之方法及一種由 此形成之半導體封裝。 【先前技術】
隨著電子器件之尺寸不斷減小，運作電子器件的相關聯 之半導體封裝被設計成具有更小的形式因素、更低的功率 要求及更高的功能性。目前，半導體製造中的亞微米特徵 對封裝技術提出了更高要求，其包括更多的引線計數、減 小的引線間距、最小的覆蓋面積及明顯的整體體積減小。 半導體封裝之一個分支涉及引線架之使用，引線架係一 其上安裝有-個或多個半導體晶粒之薄金屬層。該引線架 包括用於將電信號自一個或多個半導體傳遞至一印刷電路 板或其他外部電器件之電引線。基於普通引線架之封裝包 括塑膠小外形封裝（PS〇P)，薄小外形封裝（Ts〇p)，及收缩 小外形封裝（SS〇P)。圖1及圖2顯示一習用引線架封裝中之 組件。所圖解闡釋之組件可在（例如）Ts〇p封裝中使用，立 可達成之標準為32引線、則線、則線心·引線封裝 (為清晰起見，圖式中僅顯示少數弓丨線）。 顯不一附接丰導體, 町按千导髖日日粒22刖之引線架2〇。一典型引 線架20可包括多個引線24， $祕 巧寺引線24具有用於附接至半 2 = 之第—端H用於附著至—印刷電路板或 其他電組件之第二端（未顯示線架2〇可進—步包括一 晶粒附接墊⑽便以結構方式將㈣體晶㈣支撐於引線 1l2493.doc 架2〇上。雖然晶粒附接墊26可提供—接地路徑但傳統 上，其並不攜載來往於半導體晶粒22之信號。在某些引線 架”且態中’眾所周知，於一所謂引線上晶片(c〇L)組態 中，可略去晶粒附接墊26而代之以將半導體晶粒直接附接 至引線架引線。 如圖2中所示，可使用晶粒附接化合物將半導體引線24 安裝至粒附接墊26。傳統上，半導體晶粒Μ形成有複數 個位於該半導體晶粒頂側上的第一及第二對置邊緣上之晶 粒銲墊28。一旦該半導體晶粒被安裝至該引線架上，即實 施一絲銲過程，藉此使用精細導線3〇將銲墊28電耦接至相 應電引線24。一銲墊28至一特定電引線24之分派係由工業 標準規格所界定。為清晰起見’圖2未顯示所有欲導線連 接至引線24之銲墊28，但在習用設計型式中，每一銲墊皆 可導線連接至其相應帶電體。亦周知，如圖2中所示，並 未將所有銲墊導線連接至一帶電體。 圖3顯不一在絲銲過程後的引線架2〇及半導體晶粒u之 側剖視圖。-旦完成絲銲，即實施成型過程以在成型化合 物34内裝入組件並形成成品封裝。眾所周知，如圖3中所 不，須將半導體晶粒凹陷或r置底」於該引線架内，以使 該半導體晶粒與成型化合物環繞該晶粒及引線架流動時之 成型化合物力相平衡。重要的是在成型過程期間平衡半導 體晶粒，此乃因不平衡會使半導體晶粒在成型化合物之力 (备其流動時）下產生過度移動。此種移動可使一個或多個 銲墊28斷裂或短接，從而導致該半導體封裝損壞或完全失 112493.doc 1322490 類似地，引線架100之側104包括複數個電引線，稱為引 線112。然而，引線112係大致平行於側1 〇6及丨〇8自側i〇4 延伸跨越引線架之内部且具有終止於接近於側1〇2附近之 端110a處之端112a。儘管側102附近之引線112及11()的各 端極接近’但引線110及112係彼此分離並電隔絕。引線 112可包括與端112a對置之第二端112b供用於連接至一諸 如印刷電路板之外部器件（端112b未顯示於圖5中，但可在 圖8中看到）。在實施例中’引線架ι〇〇可由銅、銅合金或 藉以製造引線架的各種導電材料中之任意一種導電材料所 形成。 一個或多個引線112可在引線架100的兩個側1〇2及1〇4之 間延伸並附接至該兩個側，例如，以丨12，指示之引線。連 接至兩個側102及1〇4之引線U2'並不攜載來自半導體晶粒 之電信號，但可用於半導體晶粒之電接地，以及為安裝在 其上之半導體晶粒提供結構性支撐（如下文中所解釋）。除 附接至兩個側之引線112，外，通常，可將引線112共同認作 為一自引線架100之側104延伸出之懸臂。在本發明之替代 只施例中’可能不存在連接至兩個側1 02及1 〇4之引線 112'。 應瞭解’圖式中所示之各種引線112及11〇組態僅係諸多 .•且態中之一種可能組態。熟習此項技術者應瞭解，存在各 種各樣的包括延伸於半導體晶粒下面之短引線丨1〇及長引 線112在内之組態。儘管已將長懸臂式電引線112闡述為來 自側104且朝側1〇2延伸’但應瞭解可反轉引線HQ及η〗 II2493.doc 1322490 之晶粒銲墊。 半導體晶粒22可使用介電晶粒附接化合物接合至引線架 100之指狀物112。因此，電引線Π2用於如下雙重目的： 攜載來往於半導體晶粒22之電信號。以及以物理方式將半 導體22支撐於引線架1〇〇上。由於引線η2攜載電信號之事 貫，故應使用一電絕緣性晶粒接合化合物將半導體晶粒22 附接至引線112。在實施例中，本發明涵蓋除晶粒附接化 合物外還於半導體晶粒22與引線112之間施加一介電薄膜 或一層 ° 在本發明之實施例中，儘管引線112係在晶粒22下面延 伸，但在替代實施例中，本發明應涵蓋引線112可延伸於 晶粒22上以便連接沿晶粒22之單個邊緣之晶粒銲墊。在此 等實施例中，該晶粒可藉由晶粒附接墊、間隔層（如下文 所述）或其它支撐部件支撐於引線架中。 圖7顯示附著至引線架1〇〇中之引線〖12之晶粒22。一旦 附接晶粒22，則可以—周知之絲銲過程將晶粒銲塾28絲録 至相應電引線11G及112。如卫業標準或定製說明書所指 示，可將某些絲銲墊28電耦接至電引線11〇,（例如，如絲 鮮m所示）且可將其他晶粒銲墊28電㈣至電引線ιΐ2(如 絲銲⑵所示）。在實施财，某些晶粒料28可能仍保持 不連接至任一引線110或112。在替代實施例令可將每一 晶粒銲塾28絲銲至電引線110、112中之去备 ,„ U2中之一者❶在實施例
’引線架_之引線112允許在_工業標 使用半導體晶粒22。 固.〜T 112493.doc •13· 1322490 圖8係如上文所述安裝於電引線112上並絲薛至電引線 110及112的一半導體晶粒22之側剖視圖。在實施例令，電 弓。I線112可傾斜以提供—置底組態。在如上所述之絲銲過 程後，可以一周知之過程將半導體22、絲銲120、122及引 Λ 10及112之。卩分囊封於成型化合物中以形成半導體 晶粒封裝134。雖然未必需要，但根據上述實施例之引線 架100可維持與用於一具有沿兩個邊緣之晶粒銲墊之半導 體晶粒相同之⑽圖分派。在完成半導體晶粒封裝134之 製造且測試該封裝後，則可以—周知之表面安裝過程將封 裝134安裝至一諸如印刷電路板之電組件。 如在背景技術部分中所論述，在成型過程期間，該成型 化合物流會在半導體晶粒上施加力，若該半導體晶粒未經 適當平衡或支撑於-引線架上，則該力可導致該半導體晶 粒過度移動。若未經適當平衡或支樓’則可使-個或多Ζ 絲銲斷裂或短接。此外’該引線架之下表面會受迫向下且 穿過已完成封裝之底部露出。在根據本發明之一封裝中， 引線m之曝露係問題’此乃因引線U2攜載來自半導體晶 粒之信號。 因此，根據圖9中所示之本發明之一進—步實施例，可 將-間隔層14 G附著至電引線丨丨2與半導體日日日粒2 2對置之一 側上的電引線112之大致水平表面。在實施例+，間隔層 140可係-藉由周知之黏合化合物附著至電引線ιΐ2之介電 材料，例如，—聚酿亞胺薄膜或帶、或環氧樹脂(FR_4、 F^)或雙馬來酿亞胺三嗪（BT)。間隔層14()之#^㈣ H2493.doc -14- u々49〇 封裝1 34内之空間需要而變化。 在封裝134所需之成形過程 一 可完全量封於44姑， 丄加工後，該間隔層 囊封於封裒134中…戈間隔層之一底表面可曝露至 、4以外之環境而不會影響封裝134之運作。間隔声 "Ο提供至少兩個益處。第_，在成型過 140加固並增加對引線架之結構性支撐及平衡…間隔層 又讶夂十衡以防止半導 體曰曰粒之過度移動及危及晶粒與？丨線架之間的絲鲜。第
-，間隔層14〇絕緣並防止電引線122曝露於該封。 儘管根據本發明之一實施例，間隔層14〇係由心電材料 所形成Μ旦另一選擇係，該間隔層可由一諸如石夕之半導電 性材料或-導電性材料所形成，並藉由—介電晶粒附接化 合物附著至電引線112。 在上述實施例中，該間隔層有助於在成形過程期間穩固 懸臂式電引線112以防止損壞絲銲及暴露引線ιΐ2。然而， 應瞭解，有利地，間隔層14〇亦可用於一其他習用引線架 晶粒封裝中之相同目的。亦即，該間隔層可用於一其中該 半導體晶粒具有沿該晶粒兩個邊緣之銲墊之引線架組萍 中，且該引線架包括習用電引線。在該等實施例中，該半 導體晶粒可以一引線上晶片（COL)組態直接附接至引線 架’或除一晶粒附接墊外亦可使用該間隔層。 至此，所述之本發明實施例皆包括一單個半導體晶粒 22。但應瞭解’在本發明之替代實施例中，封裝134中可 包括多於一個半導體晶粒。圖10中所示之實施例包括三個 半導體晶粒22a、22b及22c。應瞭解，在本發明之替代實 112493.doc 施例中，可使用兩個或多於三個半導體晶粒。每一晶粒可 包括沿該單個邊緣之晶粒銲墊，且可係如圖所示之偏置狀 以便如上所述及如圖10中絲銲120、122所示，所有三個半 導體晶粒可離開一單個邊緣而接合至電引線110及112(如 上所述）兩者。圖8及圖9之單個半導體晶粒及圖1〇之多半 導體晶粒實施例可較佳使用間隔層14〇來運作。然而，應 瞭解，圖8及圖1〇之實施例可在沒有間隔層14〇之情形下運 作0 在圖10之實施例中，半導體晶粒22a、22b及22c之每一 個皆具有沿-單個共用邊緣之晶粒銲墊。在另一實施例 中至夕個SB粒可包括沿一單個邊緣之晶粒銲墊且至少 另一晶粒具有沿兩個對置邊緣之絲銲墊。在此一實施例 中，半導體封1134可包括田比鄰半導體晶粒之第一邊緣的 電引線110及112’如囷10中所示。封裝134可進一步包括 自引線架刚上她鄰半導體晶粒之第二對置邊緣之側1〇4延 伸出之附加電引線(未顯示）。該等附加電引線可電耦接至 沿彼邊緣之晶粒銲墊。 在一仍進一步實施例中 本發明涵蓋一第一半導體晶粒 包括僅沿第一邊緣之晶粒銲墊 僅沿一與該第一邊緣對置之第 ’及一第二半導體晶粒包括 二邊緣之晶粒銲塾。對於此 一實施例 本發明涵蓋該引線架之第一㈣包括短電引線 (如引線110)及在半導體晶粒下 112)兩者。類似地，該引線架之第 半導體晶粒下面延伸之長電引線。 面延伸之長電引線（如引線 二側包括短電引線及在 在該等實施例中，該半 112493.doc -16 - 1322490 導體晶粒可以物理方式附接至兩組長電引線，且該等長電 引線可相互交織在一起而彼此不接觸。因此，此一實施例 中之引線架100能夠將沿一晶粒之第一邊緣之晶粒銲墊連 接至該引線架兩側上之引線’且引線架100能夠將沿一晶 粒之第二對置邊緣之晶粒銲墊連接至該引線架兩側上之引 線。 可使用上述半導體晶粒及引線架以形成一 TS0p 48_引腳 組態。然而’應瞭解，在本發明之替代實施例中，引腳之 數量及引線架封裝之類型可明顯變化。儘管所用晶粒類型 對本發明並非至關重要’但封裝13 4中所用半導體晶粒可 係快閃s己憶體晶片（NOR/NAND)，SRAM或DDT，及/或一 諸如A SIC荨之控制器晶片。本發明亦涵蓋其他積體電路晶 粒用於實施其他功能。 出於例示及說明之目的，上文已對本發明進行了詳細說 明。而非意欲將本發明包羅無遺或限定於所揭示之具體形 式。依據上述教示，可做出眾多修改及變化。所述實施例 之選擇旨在最佳地解釋本發明之原職其實際應用，藉以 使其他熟習此項技術者能夠以適合於所構想具體應用之各 種實施例形式及使用各種修改來最佳地利用本發明。本發 明之範疇意欲由隨附申請專利範圍來界定。 【圖式簡單說明】 圖1係θ用引線架及半導體晶粒之分解透視圖。 圖2係一絲銲至一習用引線架之習用半導體晶粒之透視 圖。 112493.doc -17- 竿:包括—裝人成型化合物中之半導體晶粒及引線 ^在内的習用半導體封裝之側剖視圖。 内包括沿半導體晶粒之單個邊緣之半導體銲墊在 内的+導體晶粒之習用視圖。 =係-根據本發明之—實施例之引線架之透視圖。 邊缘ΓΓ:據本發明之實施例之?丨線架及-具有沿單個 邊緣之知塾的半導體晶粒之分解透視圖。
=係-根據本發明-實施例之—絲銲至引線架之半導 體日日粒之透視圓。 =8係—包括裝人成型化合物内之半導體晶粒及引線架 的根據本發明之一半導體封裝之側剖視圖。 ϋ係-包括裝人成型化合物内之半導體晶粒'引線架 ^層在内的根據本發明—替代實施例之—半導 之側剖視圖。
一 係-包括複數個半導體晶粒在内的根據本發明—進 一步實施例之一半導體封裝之側剖視圖。 【主要元件符號說明】 20 22 22a 22b 22c 24 24a 引線架 半導體晶粒 半導體晶粒 半導體晶粒 半導體晶粒 引線 第一端 H2493.doc -18-

Claims (1)

  1. I322490 第095123545號專利申請案 中文申請專利範圍替換本(98年8月） 十、申請專利範圍： ^ ；j 1. 一種用於一半導體封裝中之引線架，該引線架包括相」互 對置之第一及第二側、—能裝配於該等第一與第二側之 間的該引線架上之半導體晶粒，該半導體晶粒具有沿該 半導體晶粒之一第一邊緣之鲜塾，該引線架包括： 一個或多個電引線，當該半導體晶粒連接至該引線架 時，其用於將-個或多個該等晶粒錄塾連接至該引線架 之該第二側上的一個或多個外部連接，當該半導體晶粒 鲁 連接至該引線架時，該-個或多個晶粒銲塾田比鄰該引線 架之該第一側定位。 2.如請求項丨之引線架，該—個或多個電引線自該引線架 之該第二側延伸出且終止於毗鄰該引線架之該第一側 處。 3. 如明求項2之引線架，該一個或多個電引線自該引線架 之該第二側延伸出，該引線架係額外提供用於支撐該半 導體晶粒。 4. 如請求項3之引線架，當該半導體晶粒支撐於該引線架 上時，該半導體晶粒具有一位於毗鄰該引線架之該第一 側處之該第一邊緣，且當該半導體晶粒支撐於該引線架 上時，該半導體晶粒具有一位於毗鄰該引線架之該第二 側處之第二邊緣，該一個或多個電引線自該引線架之該 第二側延伸出一距離以便當該—個或多個半導體晶粒支 撐於其上時自該半導體晶粒之該第一邊緣下面伸出。 5· -種用於—半導體封裝中之引線架’該引線架包括相互 Il2493-980820.doc 對置的第一及第二側、一個或多個能裝配於該等第一與 第二側之間的該引線架上之半導體晶粒，當該一個或多 個半導體晶粒支撐於該引線架上時，該一個或多個半導 體晶粒具有一位於毗鄰該引線架之該第一側處之第一邊 緣’且當該一個或多個半導體晶粒支撐於該引線架上 時’該一個或多個半導體晶粒具有一位於毗鄰該引線架 之該第二侧處之第二邊緣，該引線架包括： 一自該引線架之該第二側延伸出之第一群組電引線， 該第一群組電引線終止於該引線架之該第一側附近處， 該第一群組電引線能支撐該一個或多個半導體晶粒且 該第一群組電引線被提供用於電連接至沿該一個或多個 半導體晶粒之該第一邊緣之晶粒銲墊。 6·如凊求項5之引線架，其進一步包括一自該引線架之該 第一側延伸出之第二群組電引線，該第二群組電引線被 提供用於連接至沿該一個或多個半導體晶粒之該第一邊 緣之該等晶粒銲塾。 7. 如請求項6之引線架，該第二群組電引線自該引線架之 該第一側延伸出且終止於該引線架之該第一側附近接 近自該弓丨線架之該第二側延伸出之該第一群組電引線之 各端處。 8. —種半導體封裝’其包括： 一具有第一及第二對置邊緣之半導體晶粒；及 種用於支樓該半導體晶粒之引線架，該引線架包 括： 112493-980820.doc 相互對置的第 晶粒之該第一邊緣 第二邊緣， —及第二侧’該第-側毗鄰該半導體 ，且該第二側毗鄰該半導體晶粒之該 —帛一群組電弓丨線’其具有複數個第一端，該 :端係自該引線架之該第一側連接至該封裝外 ^且其具有複數個第二端，該等第二端係與該等第ί ^對置並在該半導體晶粒之該第—邊緣處連接至該 體晶粒；及 一第二群組電弓丨線，其具有複數個第一端，該等第 —端係自該引線架之該第二側連接至該封裝外部之電連 =，且其具有複數個第二端，該等第二端係與該等第一 子置並在°玄半導體晶粒之該第一邊緣處連接至該半導 體晶粒。 9. 10. 11. 12. 13. =咕求項8之半導體封裝，該第二群組電引線自該引線 架之該第二側延伸出且終止於該半導體晶粒之該第一邊 緣附近處。 如切求項8之半導體封裝，其中該半導體晶粒安裝至該 第二群組電弓丨線上。 如清求項10之半導體封裝，其中該第二群組電引線之該 等第二端延伸超過該半導體晶粒之該第一邊緣。 如印求項8之半導體封裝，其進一步包括一在該第二群 組電弓丨線下面安裝於該封裝中之間隔層，該間隔層提供 對該引線架之支撐。 如β求項8之半導體封裝，其進一步包括一第一群組之 H2493-980820.doc 7個或多個絲鏵’其位於該半導體晶粒之該第—邊缘 處，以及該半導體晶粒與該第二群組電引線之間。 14.如:Γΐ!13之半導體封裝，其進-步包括-第二群址之 $多個絲銲’其位於該半導體晶粒之該第—邊緣 處’以及料導體晶粒與該第—群組電引線之間。 之半導體封裝’該半導體封裝係一快閃記憶 16二：為—半導體封裝提供-標準弓丨腳圖組態之方法，該 半導體封裝具有用於一曰 、+導體日日粒之第一及第二側，該 曰曰；立具有沿鄰於該封裝之該第-側的該半導 體晶粒之單個邊緣之晶粒輝墊，該方法包括以下步驟： ρ I線引腳自@封裝之該第二側延伸跨越該半導體 晶粒以與㈣該封I之該第—側之該等晶粒銲墊連接。 17·如清未項16之為—半導體封裝提供—標準引腳圖組態之 方法，其進-步包括將該半導體晶粒支撐於該等電引線 上之步驟。 18.如凊求項16之為—半導體封裝提供-標準引腳圖组態之 方法’其進-步包括藉由包括—附著至該等電引線之間 隔層來加固該半導體封裝之步驟。 112493-980820.doc -4- 1322490 '第095123545號專利申請案 中文說明書替換頁(97年9月） 七、指定代表圖： ' (一)本案指定代表圖為：第（5 )圖。 (二)本代表圖之元件符號簡單說明： 100 引線架 102 ♦ 第一側 104 第二側 106 第三側 108 第四側 110 電引線 110a 第一端 112 引線 112a 第二端 112· 引線 116- 加固物
    八、本案若有化學式時，請揭示最能顯示發明特徵的化學式： • (無） 112493-970919.doc
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