CN101213662A - 具有不对称引线框连接的电路小片封装 - Google Patents

具有不对称引线框连接的电路小片封装 Download PDF

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CN101213662A
CN101213662A CNA2006800236164A CN200680023616A CN101213662A CN 101213662 A CN101213662 A CN 101213662A CN A2006800236164 A CNA2006800236164 A CN A2006800236164A CN 200680023616 A CN200680023616 A CN 200680023616A CN 101213662 A CN101213662 A CN 101213662A
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lead frame
semiconductor die
lead
electrical
semiconductor
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CN100547777C (zh
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李明顺
廖智清
奇门·余
赫姆·塔基阿尔
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Delphi International Operations Luxembourg SARL
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SanDisk Corp
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Abstract

本发明揭示一种用于半导体封装的引线框，其包括从所述引线框的一个侧边延伸到所述引线框的相对侧边的电引线，其中可在所述引线框的第二侧边处与所述半导体电路小片形成电连接。可将所述半导体电路小片支撑在延伸越过所述引线框的引线上。所述封装可进一步包括附着到所述电引线的间隔层，以在模制所述封装期间加强所述半导体封装且防止暴露所述电引线。

Description

具有不对称引线框连接的电路小片封装
对相关申请案的交叉参考
本申请案与题为“NTEGRATED CIRCUIT PACKAGE HAVING STACKEDINTEGRATED CIRCUITS AND METHOD THEREFOR”的第11/140,608号美国专利申请案有关，所述美国专利申请案当前正处于待决中且以全文引用的方式并入本文中。
技术领域
本发明实施例涉及一种半导体封装的方法和一种借此形成的半导体封装。
背景技术
随着电子装置的尺寸持续减小，对电子装置进行操作的相关联半导体封装正被设计为具有较小形状因数、较低电力要求和较高功能性。当前，半导体制作中的亚微米型特征正对封装技术提出更高要求，包括较高引线数目、较低引线节距、最小占据面积和显著的总体体积减少。
半导体封装的一个分支涉及使用引线框，引线框是上面安装一个或一个以上半导体电路小片的金属薄层。引线框包括用于将来自所述一个或一个以上半导体的电信号传送到印刷电路板或其它外部电装置的电引线。常见的基于引线框的封装包括塑料小轮廓封装(PSOP)、薄小轮廓封装(TSOP)和收缩小轮廓封装(SSOP)。图1和图2中展示常规引线框封装中的组件。所说明的组件可例如用于TSOP封装中，TSOP封装以32引线、40引线、48引线和56引线封装为标准(出于清楚起见在图式中展示较少引线)。
图1展示在附接半导体电路小片22之前的引线框20。典型的引线框20可包括多个引线24，所述引线具有第一末端24a以用于附接到半导体电路小片22，且具有第二末端(未图示)以用于附着到印刷电路板或其它电组件。引线框20可进一步包括电路小片附接垫26以用于在结构上将半导体电路小片22支撑在引线框20上。尽管电路小片附接垫26可提供接地路径，但其在常规上不会将信号携载到半导体电路小片22或从半导体电路小片22携载信号。在某些引线框配置中，已知省略电路小片附接垫26且改为以所谓的引线上芯片(COL)配置将半导体电路小片直接附接到引线框引线。
半导体引线24可使用电路小片附接化合物安装到电路小片附接垫26，如图2所示。半导体电路小片22在常规上形成为在半导体电路小片的顶面上在第一和第二相对边缘上具有多个电路小片接合垫28。一旦将半导体电路小片安装到引线框，便执行电线接合过程，借此使用精细电线30将接合垫28电耦合到相应电引线24。将接合垫28分配到特定电引线24由工业标准规范界定。图2出于清楚起见展示不到全部的接合垫28连线到引线24，但每个接合垫可在常规设计中连线到其各自电引线。还已知将不到全部的接合垫连线到电引线，如图2所示。
图3展示在电线接合过程之后的引线框20和半导体电路小片22的横截面侧视图。一旦完成电线接合，便执行模制过程以将组件包裹在模制化合物34中且形成最终封装。已知将半导体电路小片凹陷或“向下设置”在引线框内，如图3所示，以便抵靠着当模制化合物在电路小片和引线框周围流动时所产生的力来平衡半导体电路小片。重要的是，在模制过程期间平衡半导体电路小片，因为不平衡可能会造成半导体电路小片在模制化合物流动时所产生的力下过度移动。此类移动可使所述电线接合28中的一者或一者以上断裂或短路，从而导致破坏或完全损坏半导体封装。由于在一个封装中可能存在五十个或五十个以上电线接合，因而如果在模制过程期间不对半导体电路小片进行恰当平衡的话，这将成为重大问题。
还已知在向下设置封装配置中在模制过程期间，较高浓度的模制化合物在模制过程中在半导体电路小片顶部上方流动。这在半导体电路小片顶部产生向下的力。在没有电路小片附接垫26或其它恰当结构支撑的情况下，电路小片和引线框可能向下受力，直到附接到电路小片的电引线中的一者或一者以上在封装底部暴露于外部环境为止。这再次可能导致破坏或损坏封装。
如图2和3所示，通常在半导体电路小片的第一和第二相对侧边上具有接合垫28以用于与其相应引线电耦合。根据工业规范且为便于设计，沿着半导体电路小片的第一边缘的接合垫连接到邻近于第一边缘的相应引脚，且沿着半导体电路小片的第二边缘的接合垫连接到邻近于第二边缘的相应引脚。在致力于减小半导体电路小片形状因数的过程中，现已知在半导体电路小片上仅沿着电路小片的一个边缘提供接合垫，如图4所示。如果根据工业标准进行电连接来维持恰当引出线连接，那么需要一种用于将沿着半导体电路小片的单个边缘的接合垫与引线框的第一和第二侧边两者上的电引线进行电连接的系统。
发明内容
本发明概略地说涉及一种制作用于半导体封装的引线框的方法和一种借此形成的引线框。根据本发明实施例的引线框可用于将沿着半导体电路小片的单个边缘的电路小片接合垫与引线框的第一和第二相对侧边进行电耦合。引线框的邻近于电路小片的接合垫边缘的第一侧边包括多个电引线，其终止在与第一侧边相距较短距离处，以用于连接到邻近接合垫。引线框的与第一侧边相对的第二侧边包括多个细长电引线。这些电引线从第二侧边延伸穿过引线框内部，且在接近从引线框的第一侧边延伸的电引线的末端处终止。
一个或一个以上半导体电路小片可通过安装到细长的电引线而支撑在引线框上。因此，细长的电引线用于将电信号携载到半导体电路小片和从半导体电路小片携载电信号以及在物理上将半导体电路小片支撑在引线框上的双重用途。一旦将所述一个或一个以上半导体电路小片附接到引线框，便可将沿着电路小片的单个边缘的电路小片接合垫电线接合到来自引线框的第一侧边的电引线和从引线框的第二侧边延伸的细长电引线两者。在实施例中，细长的电引线允许以工业标准引出线配置使用半导体电路小片。
在电线接合过程之后，可将半导体电路小片、电线接合以及电引线的部分封装在模制化合物中，以形成半导体电路小片封装。在本发明的另一实施例中，在封装之前，可将间隔层附着到细长电引线的与支撑半导体电路小片的引线表面相对的表面。间隔层可以是例如聚酰亚胺膜或带或各种环氧树脂的介电材料。间隔层提供至少两个益处。第一，间隔层在模制过程期间加强和改进引线框的平衡，以防止半导体电路小片过度移动且防止对电路小片与引线框之间的电线接合造成危险。第二，间隔层将细长电引线绝缘且防止细长电引线暴露于封装外部。
附图说明
图1是常规引线框和半导体电路小片的分解透视图。
图2是电线接合到常规引线框的常规半导体电路小片的透视图。
图3是包括包裹在模制化合物中的半导体电路小片和引线框的常规半导体封装的横截面侧视图。
图4是沿着半导体电路小片的单个边缘包括半导体接合垫的半导体电路小片的常规视图。
图5是根据本发明实施例的引线框的透视图。
图6是根据本发明实施例的引线框和沿着单个边缘具有接合垫的半导体电路小片的分解透视图。
图7是根据本发明实施例的电线接合到引线框的半导体电路小片的透视图。
图8是根据本发明的包括包裹在模制化合物内的半导体电路小片和引线框的半导体封装的横截面侧视图。
图9是根据本发明替代性实施例的包括包裹在模制化合物内的半导体电路小片、引线框和间隔层的半导体电路小片的横截面侧视图。
图10是根据本发明另一实施例的包括多个半导体电路小片的半导体封装的横截面侧视图。
具体实施方式
现将参看图5到10来描述本发明实施例，图5到10大体上涉及一种制作半导体封装的方法和一种借此形成的半导体封装。应了解，本发明可以许多不同形式实施，且不应将其理解为限于本文所陈述的实施例。而是，提供这些实施例以使得本发明将为全面且完整的，且将把本发明完全传达给所属领域的技术人员。实际上，希望本发明涵盖这些实施例的替代形式、修改和等效物，所述替代形式、修改和等效物包括在由所附权利要求书界定的本发明范围和精神内。此外，在以下对本发明的详细描述中，陈述多个具体细节，以便提供对本发明的全面理解。然而，所属领域的技术人员将明白，可在没有此类具体细节的情况下实践本发明。
更明确地说，本发明实施例涉及制作用于具有标准引出线配置的半导体封装的引线框和借此形成的引线框，其中所述半导体电路小片包括沿着单个边缘的电路小片接合垫，例如由现有技术图4的半导体电路小片展示。现参看图5，提供引线框100以用于在例如图4所示的半导体电路小片与引线框两个侧边上的电引线之间建立电连接。引线框100包括第一和第二相对侧边102和104以及大体上在侧边102与104之间延伸的第三和第四相对侧边106和108。侧边102包括多个电引线110，所述电引线110具有第一末端110a以用于连接到半导体上的接合垫，且具有第二末端110b以用于连接到例如印刷电路板的外部装置(末端110b未在图5中展示，但在图8中可见)。
引线框100的侧边104类似地包括多个电引线，称为引线112。然而，引线112从侧边104穿过引线框内部大体平行于侧边106和108而延伸，且具有在侧边102附近接近于末端110a终止的末端112a。不管在侧边102附近引线112和110的末端的接近度如何，引线110和112彼此分离且电隔离。引线112可包括与末端112a相对的第二末端112b，以用于连接到例如印刷电路板的外部装置(末端112b未在图5中展示，但在图8中可见)。在实施例中，引线框100可由铜、铜合金或制成引线框的多种导电材料中的任一者形成。
所述引线112中的一者或一者以上可在引线框100的侧边102与104之间延伸，且附接到所述侧边102与104两者，例如以112′指示的引线。连接到侧边102与104两者的引线112′不从半导体电路小片携载电信号，但可用于半导体电路小片的电接地，以及为安装在其上的半导体电路小片提供结构支撑，如下文解释。除了附接到两个侧边的引线112′之外，通常可将引线112共同认为是从引线框100的侧边104延伸的悬臂。在本发明的替代性实施例中，可能没有连接到侧边102和104两者的引线112′。
应了解，附图所示的各种引线112和110的配置是许多可能配置中的一种。所属领域的技术人员将理解各种各样的配置，包括短引线110和在半导体电路小片下方延伸的长引线112。尽管已经将长悬臂电引线112描述为来自侧边104且朝向侧边102延伸，但应了解，可颠倒引线110和112的各自位置以进行操作，其中半导体电路小片沿着与附图所示的边缘相对的边缘具有电线接合垫。
在本发明实施例中，可通过大体上横断且越过每个电引线112延伸的加强件116将每个电引线112附着在一起。加强件116可以是具有一定程度刚性的各种介电材料中的任一者，以进而将电引线112保持在一起，以便总体上改进电引线112的结构支撑。在一个实施例中，加强件可以是附着在电引线112的整个顶部和/或底部表面上的聚酰亚胺胶带。在实施例中，电引线可形成有用于接纳聚酰亚胺带的一对凹槽。在替代性实施例中，加强件116可由其它隔离材料形成，包括环氧树脂(FR-4、FR-5)或双马来酰亚胺三嗪(BT)，其提供在凹口中且附接到电引线112。在本发明的替代性实施例中，可在指状物112上提供多于或少于两个加强件116。在其它实施例中，可完全省略加强件116。
图6展示待安装在引线框100上的常规半导体电路小片22的分解透视图。如上文指示，半导体电路小片22可在半导体电路小片的当附接电路小片时位于引线框侧边102邻近处的侧边下方包括多个电路小片接合垫28。应了解，半导体22可在半导体电路小片的其它位置处包括电路小片接合垫。然而，可在需要将沿着半导体电路小片的单个边缘的电路小片接合垫与引线框的第一和第二相对侧边进行电耦合的任何时候使用根据本发明的引线框100。预期引线框100可在侧边104上包括额外引线，以用于在半导体电路小片22在第一和第二相对侧边上具有电路小片接合垫的情况下连接半导体电路小片22上的电路小片接合垫。
可使用介电电路小片附接化合物将半导体电路小片22接合到引线框100的指状物112。因此，电引线112用于将电信号携载到半导体电路小片22和从半导体电路小片22携载电信号以及在物理上将半导体22支撑在引线框100上的双重用途。由于引线112携载电信号的事实，应当使用电绝缘电路小片接合化合物将半导体电路小片22附接到引线112。在实施例中，预期除了电路小片附接化合物以外，还在半导体电路小片22与引线112之间施加介电膜或层。
尽管在本发明实施例中引线112在电路小片22下方延伸，但预期在替代性实施例中引线112可在电路小片22上方延伸，以与沿着电路小片22的单个边缘的电路小片接合垫形成连接。在此类实施例中，可通过电路小片附接垫、间隔层(下文描述)或其它支撑部件将电路小片支撑在引线框中。
图7展示附着到引线框100中的引线112的电路小片22。一旦附接电路小片22，便可用已知电线接合工艺将电路小片接合垫28电线接合到相应电引线110和112。如由工业标准或自定义规范规定的，可将一些电线接合垫28电耦合到电引线110，例如由电线接合120所示，且可将其它电路小片接合垫28电耦合到电引线112，如由电线接合122所示。在实施例中，一些电路小片接合垫28可保持不连接到引线110和112中的任一者。或者，在实施例中，可将每个电路小片接合垫28电线接合到电引线110、112中的一者。在实施例中，引线框100的引线112允许以工业标准引出线配置使用半导体电路小片22。
图8是安装在电引线112上且如上所述那样电线接合到电引线110和112的半导体电路小片22的横截面侧视图。在实施例中，电引线112可成角度设置，以便提供向下设置配置。在如上所述的电线接合过程之后，可用已知工艺将半导体22、电线接合120、122以及引线110和112的若干部分封装在模制化合物130中，以形成半导体电路小片封装134。虽然不要求，但根据上述实施例的引线框100可针对沿着两个边缘具有电路小片垫的半导体电路小片维持相同的引出线分配。一旦完成半导体电路小片封装134的制作且测试了所述封装，便接着可用已知的表面安装工艺将封装134表面安装到例如印刷电路板的电组件。
如背景技术中所论述的，在模式过程期间模制化合物流动向半导体电路小片施加力，如果没有将半导体电路小片恰当地进行平衡或支撑在引线框上，那么所述力可能造成半导体电路小片过度移动。如果没有恰当平衡或支撑，那么所述电线接合中的一者或一者以上可发生断裂或短路。此外，引线框的下表面可能向下受力，且通过成品封装的底部暴露。引线112的暴露在根据本发明的封装中可能是存在问题的，因为引线112从半导体电路小片携载信号。
因此，根据图9所示的本发明另一实施例，间隔层140可在电引线112的与半导体电路小片22相对的侧面上附着到电引线112的大体水平表面。在实施例中，间隔层140可以是例如聚酰亚胺膜或带、环氧树脂(FR-4、FR-5)或双马来酰亚胺三嗪(BT)的介电材料，其通过已知粘合化合物附着到电引线112。间隔层140的厚度可依据封装134内的空间要求而有所不同。
在模制过程和封装134所需的任何修整之后，可将间隔层完全封装在封装134内，或可将间隔层的底部表面暴露到封装134外部的环境，而不会对封装134的操作造成任何后果。间隔层140提供至少两个益处。第一，间隔层140在模制过程期间加强和增加引线框的结构支撑和平衡，以防止半导体电路小片过度移动且防止对电路小片与引线框之间的电线接合造成危险。第二，间隔层140将电引线112绝缘且防止电引线112暴露于封装外部。尽管在本发明实施例中间隔层140由介电材料形成，但其可替代地由例如硅的半导电材料形成或由导电材料形成，且经由介电电路小片附接化合物而附着到电引线112。
在上述实施例中，间隔层有助于在模制过程期间稳定悬臂电引线112，以防止破坏电线接合和暴露引线112。然而，应了解，间隔层140还可有利地出于相同目的用于另外的常规引线框电路小片封装中。也就是说，间隔层可用于这样的引线框配置中，其中半导体电路小片沿着电路小片的两个边缘具有接合垫，且引线框包括常规的电引线。在此类实施例中，半导体电路小片可用引线上芯片(COL)配置直接附接到引线框，或除了电路小片附接垫以外，还可使用间隔层。
至此所描述的本发明实施例已经包括单个半导体电路小片22。应了解，在本发明的替代性实施例中可在封装134中包括一个以上半导体电路小片。图10所示的实施例包括三个半导体电路小片22a、22b和22c。应了解，在本发明的替代性实施例中可使用两个或三个以上半导体电路小片。每个电路小片均可沿着单个边缘包括电路小片接合垫，且可如图所示那样偏移，使得所有三个半导体电路小片可从单个边缘接合到电引线110和112两者，如上文描述且如图10中的电线接合120、122展示。图8和9的单个半导体电路小片和图10的多个半导体电路小片实施例可优选地使用间隔层140来操作。然而，应了解，图8和10的实施例可在没有间隔层140的情况下进行操作。
在图10的实施例中，半导体电路小片22a、22b和22c中的每一者沿着单个共同边缘具有电路小片接合垫。在另一实施例中，所述电路小片中的至少一者可沿着单个边缘包括电路小片接合垫，且所述电路小片中的至少另一者沿着两个相对边缘具有电线接合垫。在此类实施例中，半导体封装134可在邻近于半导体电路小片的第一边缘处包括电引线110和112，如图10所示。封装134可进一步包括从引线框100上邻近于半导体电路小片的第二相对边缘的侧边104延伸的额外电引线(未图示)。这些额外电引线可电耦合到沿着所述边缘的电路小片接合垫。
在又一实施例中，预期第一半导体电路小片仅沿着第一边缘包括电路小片接合垫，且第二半导体电路小片仅沿着与第一边缘相对的第二边缘包括电路小片接合垫。对于此实施例，预期引线框的第一侧边包括短电引线(如引线110)和在半导体电路小片下方延伸的长电引线(如引线112)。引线框的第二侧边类似地包括短电引线和在半导体电路小片下方延伸的长电引线。在此类实施例中，半导体电路小片可在物理上附接到两组长电引线，且所述长电引线可在不接触彼此的情况下彼此交织。因此，此实施例中的引线框100将能够把沿着电路小片的第一边缘的电路小片接合垫连接到引线框的两个侧边上的引线，且引线框100将能够把沿着电路小片的第二相对边缘的电路小片接合垫连接到引线框的两个侧边上的引线。
上述半导体电路小片和引线框可用于形成TSOP 48引脚配置。然而，应了解，引脚的数目和引线框封装的类型可在本发明替代性实施例中显著变化。虽然所使用的电路小片类型对于本发明并不重要，但封装134中所使用的半导体电路小片可以是快闪存储器芯片(或非/与非)、SRAM或DDT和/或例如ASIC的控制器芯片。用于执行其它功能的其它集成电路小片也是预期的。
已经出于说明和描述目的呈现了先前对本发明的详细描述。不希望所述描述是详尽的或将本发明限于所揭示的精确形式。鉴于以上教示，能够作出许多修改和变化。选择所述实施例是为了最佳解释本发明的原理和其实际应用，以进而使得所属领域的技术人员能够用各种实施例和用适于所预期的特定用途的各种修改来最佳利用本发明。希望本发明的范围由所附权利要求书界定。

Claims (21)

1.一种用于半导体封装中的引线框，所述引线框包括第一和第二相对侧边，半导体电路小片能够在所述第一与第二侧边之间装配在所述引线框上，所述半导体电路小片沿着所述半导体电路小片的第一边缘具有接合垫，所述引线框包含：
一个或一个以上电引线，其用于当所述半导体电路小片连接到所述引线框时，在所述引线框的所述第一侧边上将所述电路小片接合垫中的一者或一者以上连接到一个或一个以上外部连接，当所述半导体电路小片连接到所述引线框时，所述一个或一个以上电路小片接合垫定位在邻近于所述引线框的所述第二侧边处。
2.根据权利要求1所述的引线框，所述一个或一个以上电引线从所述引线框的所述第一侧边延伸且在邻近于所述引线框的所述第二侧边处终止。
3.根据权利要求2所述的引线框，从所述引线框的所述第一侧边延伸的所述一个或一个以上电引线经额外提供以用于支撑所述半导体电路小片。
4.根据权利要求3所述的引线框，所述半导体电路小片具有当将所述半导体电路小片支撑在所述引线框上时位于邻近于所述引线框的所述第一侧边处的第一边缘，且所述半导体电路小片具有当将所述半导体电路小片支撑在所述引线框上时位于邻近于所述引线框的所述第二侧边处的第二边缘，所述一个或一个以上电引线从所述引线框的所述第一侧边延伸一段距离，以便当将所述一个或一个以上半导体电路小片支撑在所述引线框上时从所述半导体电路小片的所述第二边缘下方突出。
5.一种用于半导体封装中的引线框，所述引线框包括第一和第二相对侧边，一个或一个以上半导体电路小片能够在所述第一与第二侧边之间装配在所述引线框上，所述一个或一个以上半导体电路小片具有当将所述一个或一个以上半导体电路小片支撑在所述引线框上时位于邻近于所述引线框的所述第一侧边处的第一边缘，且所述一个或一个以上半导体电路小片具有当将所述一个或一个以上半导体电路小片支撑在所述引线框上时位于邻近于所述引线框的所述第二侧边处的第二边缘，所述引线框包含：
从所述引线框的所述第一侧边延伸的第一群组电引线，所述第一群组电引线在所述引线框的所述第二侧边附近终止，所述第一群组电引线能够支撑所述一个或一个以上半导体电路小片，且所述第一群组电引线经提供以用于电连接到沿着所述一个或一个以上半导体电路小片的所述第二边缘的电路小片接合垫。
6.根据权利要求5所述的引线框，其进一步包括从所述引线框的所述第二侧边延伸的第二群组电引线，所述第二群组电引线经提供以用于连接到沿着所述一个或一个以上半导体电路小片的所述第二边缘的所述电路小片接合垫。
7.根据权利要求6所述的引线框，所述第二群组电引线从所述引线框的所述第二侧边延伸，且在所述引线框的所述第二侧边附近且接近从所述第一侧边延伸的所述第一群组电引线的末端处终止。
8.一种用于包括一个或一个以上半导体电路小片的半导体封装中的引线框，所述引线框包含：
多个电引线，所述一个或一个以上半导体电路小片在所述多个电引线的第一大致水平侧面上安装到所述多个电引线的至少一部分；以及
间隔层，其安装在所述电引线的与所述第一大致水平侧面相对的第二大致水平侧面上，所述间隔层在所述半导体封装的模制过程期间加强所述引线框。
9.根据权利要求8所述的引线框，所述引线框进一步包含：
第一和第二相对边缘，所述一个或一个以上半导体电路小片能够在所述第一与第二侧边之间装配在所述引线框上；以及
从所述引线框的所述第一侧边延伸的所述多个电引线中的一个或一个以上电引线，所述一个或一个以上电引线在所述引线框的所述第二侧边附近终止。
10.根据权利要求8所述的引线框，所述间隔层是由介电材料形成的。
11.一种半导体封装，其包含：
半导体电路小片，其具有第一和第二相对边缘；以及
引线框，其用于支撑所述半导体电路小片，所述引线框包括：
第一和第二相对侧边，所述第一侧边邻近于所述半导体电路小片的所述第一边缘，且所述第二侧边邻近于所述半导体电路小片的所述第二边缘，
第一群组电引线，其具有从所述引线框的所述第一侧边连接到所述封装外部的电连接的第一末端，且具有与所述第一末端相对的在所述半导体电路小片的所述第一边缘处连接到所述半导体电路小片的第二末端，以及
第二群组电引线，其具有从所述引线框的所述第二侧边连接到所述封装外部的电连接的第一末端，且具有与所述第一末端相对的在所述半导体电路小片的所述第一边缘处连接到所述半导体电路小片的第二末端。
12.根据权利要求11所述的半导体封装，所述第二群组电引线从所述引线框的所述第二侧边延伸且在所述半导体电路小片的所述第一边缘附近终止。
13.根据权利要求11所述的半导体封装，其中所述半导体电路小片安装到所述第二群组电引线。
14.根据权利要求13所述的半导体封装，其中所述第二群组电引线的所述第二末端延伸越过所述半导体电路小片的所述第一边缘。
15.根据权利要求11所述的半导体封装，其进一步包含在所述第二群组电引线下方安装在所述封装内的间隔层，所述间隔层提供对所述引线框的支撑。
16.根据权利要求11所述的半导体封装，其进一步包含第一群组一个或一个以上电线接合，其处于所述半导体电路小片的所述第一边缘处且在所述半导体电路小片与所述第二群组电引线之间。
17.根据权利要求16所述的半导体封装，其进一步包含第二群组一个或一个以上电线接合，其处于所述半导体电路小片的所述第一边缘处且在所述半导体电路小片与所述第一群组电引线之间。
18.根据权利要求11所述的半导体封装，所述半导体封装是快闪存储器封装。
19.一种提供用于具有用于半导体电路小片的第一和第二侧边的半导体封装的标准引出线配置的方法，所述半导体电路小片沿着所述半导体电路小片的邻近于所述封装的所述第二侧边的单个边缘具有电路小片接合垫，所述方法包含以下步骤：
使电引线引脚从所述封装的第一侧边延伸越过所述半导体电路小片以与邻近于所述封装的所述第二侧边的所述电路小片接合垫形成连接。
20.根据权利要求19所述的提供用于半导体封装的标准引出线配置的方法，其进一步包含将所述半导体电路小片支撑在所述电引线上的步骤。
21.根据权利要求19所述的提供用于半导体封装的标准引出线配置的方法，其进一步包含通过包括附着到所述电引线的间隔层来加强所述半导体封装的步骤。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024799A (zh) * 2009-09-09 2011-04-20 株式会社日立制作所 半导体装置
CN107305877A (zh) * 2016-04-19 2017-10-31 英飞凌科技美国公司 适应性模制引线框封装件及相关方法
CN108666291A (zh) * 2017-03-28 2018-10-16 爱信精机株式会社 电子元件模块和用于制造电子元件模块的方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080185694A1 (en) * 1999-08-04 2008-08-07 Super Talent Electronics, Inc. Processes of Manufacturing Portable Electronic Storage Devices Utilizing Lead Frame Connectors
JP2007129182A (ja) * 2005-05-11 2007-05-24 Toshiba Corp 半導体装置
US7375415B2 (en) * 2005-06-30 2008-05-20 Sandisk Corporation Die package with asymmetric leadframe connection
US7728411B2 (en) * 2006-02-15 2010-06-01 Sandisk Corporation COL-TSOP with nonconductive material for reducing package capacitance
US7727816B2 (en) * 2006-07-21 2010-06-01 Stats Chippac Ltd. Integrated circuit package system with offset stacked die
JP5048685B2 (ja) * 2006-12-29 2012-10-17 オンセミコンダクター・トレーディング・リミテッド 半導体装置およびその製造方法
DE102007050608A1 (de) * 2007-10-23 2009-04-30 Infineon Technologies Ag Gehäuse für einen Halbleiter-Chip
US7821112B2 (en) * 2008-03-09 2010-10-26 Powertech Technology Inc Semiconductor device with wire-bonding on multi-zigzag fingers
US7615407B1 (en) * 2008-07-02 2009-11-10 National Semiconductor Corporation Methods and systems for packaging integrated circuits with integrated passive components
US7612436B1 (en) * 2008-07-31 2009-11-03 Micron Technology, Inc. Packaged microelectronic devices with a lead frame
JP5361426B2 (ja) * 2009-02-05 2013-12-04 株式会社東芝 半導体デバイス
US8216885B2 (en) * 2009-10-19 2012-07-10 Texas Instruments Incorporated Methods and devices for manufacturing cantilever leads in a semiconductor package
ITTO20150231A1 (it) 2015-04-24 2016-10-24 St Microelectronics Srl Procedimento per produrre lead frame per componenti elettronici, componente e prodotto informatico corrispondenti
EP3331007A1 (en) * 2016-12-05 2018-06-06 Melexis Technologies SA Integrated circuit package comprising lead frame
CN108987369B (zh) * 2018-06-26 2024-03-26 柳州梓博科技有限公司 一种芯片封装结构、芯片功能模组及电子设备

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3469017A (en) * 1967-12-12 1969-09-23 Rca Corp Encapsulated semiconductor device having internal shielding
US3930114A (en) * 1975-03-17 1975-12-30 Nat Semiconductor Corp Integrated circuit package utilizing novel heat sink structure
JPS52116074A (en) * 1976-03-26 1977-09-29 Hitachi Ltd Electronic part
JPS59207645A (ja) * 1983-05-11 1984-11-24 Toshiba Corp 半導体装置およびリ−ドフレ−ム
JPS607159A (ja) * 1983-06-24 1985-01-14 Toshiba Corp 樹脂封止型半導体装置とその製造方法
JP2763004B2 (ja) 1987-10-20 1998-06-11 株式会社 日立製作所 半導体装置
JPH0720925Y2 (ja) * 1989-05-12 1995-05-15 株式会社三井ハイテック リードフレーム
US5140404A (en) * 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
JPH04302164A (ja) * 1991-03-29 1992-10-26 Fujitsu Ltd 半導体装置
JPH04367285A (ja) * 1991-06-14 1992-12-18 Nec Corp 光電変換半導体装置
JPH0513652A (ja) * 1991-06-28 1993-01-22 Shinko Electric Ind Co Ltd リードフレーム
JPH06334106A (ja) * 1992-03-16 1994-12-02 Hitachi Ltd 樹脂封止型半導体装置
US5352633A (en) * 1992-06-02 1994-10-04 Texas Instruments Incorporated Semiconductor lead frame lead stabilization
JPH0653404A (ja) * 1992-07-29 1994-02-25 Nec Corp リードフレーム
FR2694840B1 (fr) * 1992-08-13 1994-09-09 Commissariat Energie Atomique Module multi-puces à trois dimensions.
JPH06132458A (ja) * 1992-10-19 1994-05-13 Mitsubishi Electric Corp 樹脂封止型半導体装置およびそのリードフレーム
EP0595021A1 (en) * 1992-10-28 1994-05-04 International Business Machines Corporation Improved lead frame package for electronic devices
US5389739A (en) * 1992-12-15 1995-02-14 Hewlett-Packard Company Electronic device packaging assembly
JPH0823042A (ja) * 1994-07-07 1996-01-23 Fujitsu Ltd 半導体装置及びその製造方法及びこれに使用される金型
US6184575B1 (en) * 1994-08-26 2001-02-06 National Semiconductor Corporation Ultra-thin composite package for integrated circuits
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US5729049A (en) * 1996-03-19 1998-03-17 Micron Technology, Inc. Tape under frame for conventional-type IC package assembly
US5798570A (en) * 1996-06-28 1998-08-25 Kabushiki Kaisha Gotoh Seisakusho Plastic molded semiconductor package with thermal dissipation means
US6114750A (en) 1996-10-01 2000-09-05 International Rectifier Corp. Surface mount TO-220 package and process for the manufacture thereof
JPH10116934A (ja) * 1996-10-09 1998-05-06 Fuji Electric Co Ltd 樹脂封止半導体装置およびその製造方法
US5907769A (en) * 1996-12-30 1999-05-25 Micron Technology, Inc. Leads under chip in conventional IC package
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US6159764A (en) * 1997-07-02 2000-12-12 Micron Technology, Inc. Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
US5955777A (en) * 1997-07-02 1999-09-21 Micron Technology, Inc. Lead frame assemblies with voltage reference plane and IC packages including same
TW497376B (en) * 1999-05-14 2002-08-01 Siliconware Precision Industries Co Ltd Dual-die semiconductor package using lead as die pad
US6605875B2 (en) * 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
US6576494B1 (en) * 2000-06-28 2003-06-10 Micron Technology, Inc. Recessed encapsulated microelectronic devices and methods for formation
US6603196B2 (en) 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US6843421B2 (en) * 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
SG111919A1 (en) * 2001-08-29 2005-06-29 Micron Technology Inc Packaged microelectronic devices and methods of forming same
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US6841852B2 (en) 2002-07-02 2005-01-11 Leeshawn Luo Integrated circuit package for semiconductor devices with improved electric resistance and inductance
US7367503B2 (en) 2002-11-13 2008-05-06 Sandisk Corporation Universal non-volatile memory card used with various different standard cards containing a memory controller
US7034385B2 (en) 2003-08-05 2006-04-25 International Rectifier Corporation Topless semiconductor package
US6858470B1 (en) 2003-10-08 2005-02-22 St Assembly Test Services Ltd. Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof
US7381593B2 (en) * 2004-08-05 2008-06-03 St Assembly Test Services Ltd. Method and apparatus for stacked die packaging
EP1662343B1 (en) * 2004-11-29 2009-02-25 Seiko Epson Corporation Electronic apparatus, method for detecting positions of pointer members in electronic apparatus, and a program for detecting positions of pointer members in electronic apparatus
US7375415B2 (en) * 2005-06-30 2008-05-20 Sandisk Corporation Die package with asymmetric leadframe connection
US7638861B2 (en) * 2005-12-08 2009-12-29 Fairchild Semiconductor Corporation Flip chip MLP with conductive ink
US7728411B2 (en) * 2006-02-15 2010-06-01 Sandisk Corporation COL-TSOP with nonconductive material for reducing package capacitance
US7629676B2 (en) * 2006-09-07 2009-12-08 Infineon Technologies Ag Semiconductor component having a semiconductor die and a leadframe
US7622793B2 (en) * 2006-12-21 2009-11-24 Anderson Richard A Flip chip shielded RF I/O land grid array package
US7687893B2 (en) * 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7619307B1 (en) * 2008-06-05 2009-11-17 Powertech Technology Inc. Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024799A (zh) * 2009-09-09 2011-04-20 株式会社日立制作所 半导体装置
CN107305877A (zh) * 2016-04-19 2017-10-31 英飞凌科技美国公司 适应性模制引线框封装件及相关方法
CN107305877B (zh) * 2016-04-19 2019-10-18 英飞凌科技美国公司 适应性模制引线框封装件及相关方法
CN108666291A (zh) * 2017-03-28 2018-10-16 爱信精机株式会社 电子元件模块和用于制造电子元件模块的方法

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US20070001272A1 (en) 2007-01-04
US8097495B2 (en) 2012-01-17
KR20080023702A (ko) 2008-03-14
KR100963664B1 (ko) 2010-06-15
WO2007011511A3 (en) 2007-03-15
TWI322490B (en) 2010-03-21
US20080182365A1 (en) 2008-07-31
EP1911091A2 (en) 2008-04-16
US7375415B2 (en) 2008-05-20
CN100547777C (zh) 2009-10-07
WO2007011511A2 (en) 2007-01-25

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