TWI300971B - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
TWI300971B
TWI300971B TW095144838A TW95144838A TWI300971B TW I300971 B TWI300971 B TW I300971B TW 095144838 A TW095144838 A TW 095144838A TW 95144838 A TW95144838 A TW 95144838A TW I300971 B TWI300971 B TW I300971B
Authority
TW
Taiwan
Prior art keywords
film
wiring
layer
dielectric constant
insulating film
Prior art date
Application number
TW095144838A
Other languages
English (en)
Chinese (zh)
Other versions
TW200711041A (en
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of TW200711041A publication Critical patent/TW200711041A/zh
Application granted granted Critical
Publication of TWI300971B publication Critical patent/TWI300971B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H10P14/6905—Inorganic materials containing silicon being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6924—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW095144838A 2002-04-12 2003-03-07 Semiconductor device TWI300971B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002109901 2002-04-12

Publications (2)

Publication Number Publication Date
TW200711041A TW200711041A (en) 2007-03-16
TWI300971B true TWI300971B (en) 2008-09-11

Family

ID=29243211

Family Applications (2)

Application Number Title Priority Date Filing Date
TW095144838A TWI300971B (en) 2002-04-12 2003-03-07 Semiconductor device
TW092104965A TWI278962B (en) 2002-04-12 2003-03-07 Semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW092104965A TWI278962B (en) 2002-04-12 2003-03-07 Semiconductor device

Country Status (5)

Country Link
US (5) US6838771B2 (enExample)
JP (1) JP2010045406A (enExample)
KR (2) KR100556641B1 (enExample)
CN (2) CN101197372B (enExample)
TW (2) TWI300971B (enExample)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7172960B2 (en) * 2000-12-27 2007-02-06 Intel Corporation Multi-layer film stack for extinction of substrate reflections during patterning
TWI300971B (en) * 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
JP2004071705A (ja) * 2002-08-02 2004-03-04 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
US7169698B2 (en) * 2004-01-14 2007-01-30 International Business Machines Corporation Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
US20050200026A1 (en) * 2004-03-10 2005-09-15 Taiwan Semiconductor Manufacturing Co. Ltd. Contact structure for nanometer characteristic dimensions
JP4695345B2 (ja) * 2004-05-18 2011-06-08 株式会社 日立ディスプレイズ 有機エレクトロルミネッセンス表示装置
US7217651B2 (en) * 2004-07-28 2007-05-15 Intel Corporation Interconnects with interlocks
JP4776195B2 (ja) * 2004-09-10 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置
US20060103023A1 (en) * 2004-11-12 2006-05-18 International Business Machines Corporation Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby
US20060125102A1 (en) * 2004-12-15 2006-06-15 Zhen-Cheng Wu Back end of line integration scheme
KR100641553B1 (ko) * 2004-12-23 2006-11-01 동부일렉트로닉스 주식회사 반도체 소자에서 패턴 형성 방법
KR100669851B1 (ko) * 2005-07-12 2007-01-16 삼성전자주식회사 상변화 메모리 장치의 제조 방법
MX2009004291A (es) * 2006-10-22 2009-09-07 Idev Technologies Inc Metodos para asegurar extremos de hebra y los dispositivos resultantes.
JP2008140886A (ja) * 2006-11-30 2008-06-19 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP4506767B2 (ja) * 2007-02-28 2010-07-21 カシオ計算機株式会社 半導体装置の製造方法
US8222061B2 (en) * 2007-03-30 2012-07-17 The Penn State Research Foundation Mist fabrication of quantum dot devices
JP2009088269A (ja) 2007-09-28 2009-04-23 Toshiba Corp 半導体装置、およびその製造方法
US8084356B2 (en) * 2007-09-29 2011-12-27 Lam Research Corporation Methods of low-K dielectric and metal process integration
US8106487B2 (en) * 2008-12-23 2012-01-31 Pratt & Whitney Rocketdyne, Inc. Semiconductor device having an inorganic coating layer applied over a junction termination extension
CN101958310B (zh) * 2009-07-16 2012-05-23 中芯国际集成电路制造(上海)有限公司 半导体器件及半导体器件的形成方法
JP5383446B2 (ja) * 2009-11-18 2014-01-08 パナソニック株式会社 半導体装置
US8314472B2 (en) 2010-07-29 2012-11-20 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structure comprising pillar
US8344504B2 (en) 2010-07-29 2013-01-01 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structure comprising pillar and moisture barrier
US8536707B2 (en) 2011-11-29 2013-09-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor structure comprising moisture barrier and conductive redistribution layer
CN103839922B (zh) * 2012-11-27 2017-06-13 中芯国际集成电路制造(上海)有限公司 半导体测试结构及其测试方法、检测方法
KR101872532B1 (ko) * 2012-12-28 2018-06-28 삼성전기주식회사 회로 기판 및 그 제조 방법
US9041207B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Method to increase I/O density and reduce layer counts in BBUL packages
TWI552290B (zh) * 2014-04-22 2016-10-01 矽品精密工業股份有限公司 封裝基板及其製法
US9704804B1 (en) * 2015-12-18 2017-07-11 Texas Instruments Incorporated Oxidation resistant barrier metal process for semiconductor devices
KR102579880B1 (ko) 2016-05-12 2023-09-18 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
US11289647B2 (en) 2017-10-19 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Resistive random access memory device
IT201700122764A1 (it) * 2017-10-27 2019-04-27 Consiglio Nazionale Ricerche Sensore di gas basato su ossido di metallo e relativo metodo di fabbricazione
WO2019193896A1 (ja) * 2018-04-02 2019-10-10 株式会社ソシオネクスト 半導体装置
CN112368821B (zh) * 2018-06-29 2025-01-21 索尼半导体解决方案公司 半导体装置和半导体装置的制造方法
JP7110879B2 (ja) * 2018-09-28 2022-08-02 住友電気工業株式会社 半導体装置およびその製造方法
JP7282500B2 (ja) * 2018-10-19 2023-05-29 キヤノン株式会社 半導体装置、機器、半導体装置の製造方法
CN111584433B (zh) * 2020-06-08 2021-12-10 上海领矽半导体有限公司 一种保护环及其形成方法
CN114743952A (zh) * 2022-06-14 2022-07-12 合肥晶合集成电路股份有限公司 半导体结构及其制作方法
CN121463856A (zh) * 2025-12-31 2026-02-03 江苏芯德半导体科技股份有限公司 一种晶圆级芯片尺寸封装结构及方法

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02217198A (ja) 1989-02-20 1990-08-29 Kawasaki Steel Corp 溶接用フラックス入りワイヤの製造方法
US5494859A (en) * 1994-02-04 1996-02-27 Lsi Logic Corporation Low dielectric constant insulation layer for integrated circuit structure and method of making same
TW378345B (en) 1997-01-22 2000-01-01 Hitachi Ltd Resin package type semiconductor device and manufacturing method thereof
KR100295380B1 (ko) * 1997-04-02 2001-08-07 가네꼬 히사시 층간절연물질로서저유전율의비정질탄소불화물막을가질수있는반도체장치및그제조방법
JPH10335458A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置及びその製造方法
JPH11163127A (ja) 1997-11-25 1999-06-18 Sony Corp 多層配線およびその製造方法
JP3121311B2 (ja) * 1998-05-26 2000-12-25 日本電気株式会社 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法
US6218302B1 (en) * 1998-07-21 2001-04-17 Motorola Inc. Method for forming a semiconductor device
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6187663B1 (en) * 1999-01-19 2001-02-13 Taiwan Semiconductor Manufacturing Company Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials
JP2000216264A (ja) * 1999-01-22 2000-08-04 Mitsubishi Electric Corp Ｃｍｏｓ論理回路素子、半導体装置とその製造方法およびその製造方法において用いる半導体回路設計方法
KR100308213B1 (ko) * 1999-02-12 2001-09-26 윤종용 반도체 장치를 위한 저유전 층간 절연막의 제조 방법
JP3502288B2 (ja) 1999-03-19 2004-03-02 富士通株式会社 半導体装置およびその製造方法
TW444252B (en) * 1999-03-19 2001-07-01 Toshiba Corp Semiconductor apparatus and its fabricating method
JP3727818B2 (ja) 1999-03-19 2005-12-21 株式会社東芝 半導体装置の配線構造及びその形成方法
JP2001026121A (ja) 1999-07-14 2001-01-30 Canon Inc インクジェット記録装置および該記録装置のインク残量検出方法
JP2001044191A (ja) * 1999-07-27 2001-02-16 Sony Corp 積層絶縁膜とその製造方法および半導体装置とその製造方法
JP2001044202A (ja) 1999-07-30 2001-02-16 Nec Corp 半導体装置及びその製造方法
JP2001057366A (ja) 1999-08-18 2001-02-27 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6815329B2 (en) * 2000-02-08 2004-11-09 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
JP2001274238A (ja) 2000-03-28 2001-10-05 Hitachi Ltd 半導体集積回路装置の製造方法
JP2001274239A (ja) 2000-03-28 2001-10-05 Toshiba Corp 半導体装置およびその製造方法
JP3604007B2 (ja) * 2000-03-29 2004-12-22 富士通株式会社 低誘電率被膜形成材料、及びそれを用いた被膜と半導体装置の製造方法
JP2001319928A (ja) 2000-05-08 2001-11-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6482733B2 (en) * 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
US6316351B1 (en) * 2000-05-31 2001-11-13 Taiwan Semiconductor Manufacturing Company Inter-metal dielectric film composition for dual damascene process
WO2002001627A1 (en) 2000-06-26 2002-01-03 Hitachi, Ltd. Semiconductor device and method manufacturing the same
JP2002026121A (ja) 2000-06-30 2002-01-25 Tokyo Electron Ltd 半導体装置およびその製造方法、絶縁膜の形成方法
US6500752B2 (en) * 2000-07-21 2002-12-31 Canon Sales Co., Inc. Semiconductor device and semiconductor device manufacturing method
US20020033486A1 (en) * 2000-08-04 2002-03-21 Samsung Electronics Co., Ltd. Method for forming an interconnection line using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer
US6358842B1 (en) * 2000-08-07 2002-03-19 Chartered Semiconductor Manufacturing Ltd. Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
US6451683B1 (en) * 2000-08-28 2002-09-17 Micron Technology, Inc. Damascene structure and method of making
JP4095763B2 (ja) * 2000-09-06 2008-06-04 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US7119008B2 (en) 2000-09-18 2006-10-10 Acm Research, Inc. Integrating metal layers with ultra low-K dielectrics
JP2002110676A (ja) * 2000-09-26 2002-04-12 Toshiba Corp 多層配線を有する半導体装置
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
US6576345B1 (en) * 2000-11-30 2003-06-10 Novellus Systems Inc Dielectric films with low dielectric constants
US6475929B1 (en) * 2001-02-01 2002-11-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant
US6677680B2 (en) * 2001-02-28 2004-01-13 International Business Machines Corporation Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
US6727593B2 (en) 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
JP4118029B2 (ja) * 2001-03-09 2008-07-16 富士通株式会社 半導体集積回路装置とその製造方法
US20020140064A1 (en) 2001-03-29 2002-10-03 Advanced Semiconductor Engineering Inc. Semiconductor chip package and lead frame structure thereof
US6383913B1 (en) * 2001-04-06 2002-05-07 United Microelectronics Corp. Method for improving surface wettability of low k material
JP4523194B2 (ja) 2001-04-13 2010-08-11 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP2002353307A (ja) * 2001-05-25 2002-12-06 Toshiba Corp 半導体装置
US7224063B2 (en) * 2001-06-01 2007-05-29 International Business Machines Corporation Dual-damascene metallization interconnection
US6541303B2 (en) 2001-06-20 2003-04-01 Micron Technology, Inc. Method for conducting heat in a flip-chip assembly
JP4801296B2 (ja) * 2001-09-07 2011-10-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US6992391B2 (en) * 2001-09-28 2006-01-31 Intel Corporation Dual-damascene interconnects without an etch stop layer by alternating ILDs
JP2003163265A (ja) 2001-11-27 2003-06-06 Nec Corp 配線構造およびその製造方法
JP2003264260A (ja) * 2002-03-08 2003-09-19 Toshiba Corp 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板
TWI300971B (en) * 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
JP4040363B2 (ja) * 2002-05-20 2008-01-30 富士通株式会社 半導体装置
WO2004097916A1 (ja) * 2003-04-30 2004-11-11 Fujitsu Limited 半導体装置の製造方法、半導体ウエハおよび半導体装置
US20040251549A1 (en) * 2003-06-11 2004-12-16 Tai-Chun Huang Hybrid copper/low k dielectric interconnect integration method and device
JP4230334B2 (ja) * 2003-10-31 2009-02-25 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US20100252933A1 (en) 2010-10-07
JP2010045406A (ja) 2010-02-25
US7772700B2 (en) 2010-08-10
US7986041B2 (en) 2011-07-26
TW200711041A (en) 2007-03-16
US20060001169A1 (en) 2006-01-05
US20030213980A1 (en) 2003-11-20
KR20030081161A (ko) 2003-10-17
CN1452244A (zh) 2003-10-29
US7372154B2 (en) 2008-05-13
KR100571896B1 (ko) 2006-04-18
TWI278962B (en) 2007-04-11
CN101197372A (zh) 2008-06-11
CN101197372B (zh) 2010-09-29
US20050093161A1 (en) 2005-05-05
US7247525B2 (en) 2007-07-24
KR20050055677A (ko) 2005-06-13
KR100556641B1 (ko) 2006-03-03
US6838771B2 (en) 2005-01-04
TW200305255A (en) 2003-10-16
US20060001167A1 (en) 2006-01-05

Similar Documents

Publication Publication Date Title
TWI278962B (en) Semiconductor device
TW550743B (en) Semiconductor device and method of manufacturing the semiconductor device
US8455985B2 (en) Integrated circuit devices having selectively strengthened composite interlayer insulation layers and methods of fabricating the same
JP3974023B2 (ja) 半導体装置の製造方法
US20040251549A1 (en) Hybrid copper/low k dielectric interconnect integration method and device
JP2004080017A (ja) 相互接続構造体およびその形成方法
KR19990029622A (ko) 반도체집적회로장치 및 그 제조방법
JP2004095865A (ja) 半導体装置およびその製造方法
US7319271B2 (en) Semiconductor device
WO2004023542A1 (ja) 半導体装置及びその製造方法
US20050242440A1 (en) Insulating film forming method capable of enhancing adhesion of silicon carbide film, etc. and semiconductor device
JP3657576B2 (ja) 半導体装置の製造方法
US7015589B2 (en) Semiconductor device having low-k dielectric film in pad region
JP2004031918A (ja) 半導体装置
US7351653B2 (en) Method for damascene process
JP4443517B2 (ja) 半導体装置の製造方法
KR100546940B1 (ko) 반도체 소자의 구리 배선 형성 방법
JP2006128722A (ja) 半導体装置
JP2007088017A (ja) 有機絶縁膜とその作製方法，及び有機絶縁膜を用いた半導体装置
TWI247358B (en) Etch stop layer of compound material in semiconductor manufacturing process
JP2007317818A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees