TWI264099B - Lead frame and manufacturing method therefor - Google Patents

Lead frame and manufacturing method therefor Download PDF

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Publication number
TWI264099B
TWI264099B TW091115221A TW91115221A TWI264099B TW I264099 B TWI264099 B TW I264099B TW 091115221 A TW091115221 A TW 091115221A TW 91115221 A TW91115221 A TW 91115221A TW I264099 B TWI264099 B TW I264099B
Authority
TW
Taiwan
Prior art keywords
lead frame
metal plate
plating
mask
palladium
Prior art date
Application number
TW091115221A
Other languages
English (en)
Inventor
Ichinori Iidani
Yoichiro Hamada
Original Assignee
Sumitomo Metal Mining Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001207316A external-priority patent/JP4852802B2/ja
Application filed by Sumitomo Metal Mining Co filed Critical Sumitomo Metal Mining Co
Application granted granted Critical
Publication of TWI264099B publication Critical patent/TWI264099B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/481—Disposition
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

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1264099 經濟部智慧財產局員工消費合作社印製 A； ~_____B7____五、發明説明（1 ) 【技術領域】 本發明是有關使用於半導體裝置的導線架及其製造方 法。 【技術背景】 以往’導線架是從金屬板以蝕刻加工或沖壓加工成形 爲預定的形狀，全面實施鍍鈀處理後，在預定位置搭載半 導體元件’將其封上樹脂後用金屬模具等切成各個片’作 爲I C晶片等之電子零件提供實際使用。 近年’導線架的規格，考量對環境的影響而停止了含 鉛的外裝焊接電鍍，改採用導線架全面實施鍍鈀處理。然 而’因鈀爲高價的金屬材料，所以全面實施鍍鈀處理會使 製品成本上升而成問題。 因此，本發明的主要目的在於提供抑低鈀使用量於最 少而廉價的導線架。 本發明的另一目的在於提供消除不良品質的導線架製 造方法。 【發明的揭露】 爲達成上述目的’依照本發明的導線架，是於金屬板 成形的導線架中，僅於半導體元件搭載部分和金屬線接合 部分以及基板安裝面側的焊接部分等必要的最少限度的位 置，局部實施鍍鈀處理爲其特徵。 又’依照本發明的導線架，是於金屬板成形的導線架 本纸張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐)~"" "" -4 - (請先閲讀背面之注意事項存填寫本頁) 裝--- I訂i 如 1264099 Λ7 _ B7 五、發明説明（2 ) 中5僅於半導體元件搭載側表面及基板安裝側表面實施鍍 纪處理’成形的導線部、焊墊部之其他不需安裝的部分及 側面則不予電鍍爲其特徵。 (請先閔讀背vB之注意事項再填寫本頁) 又’依照本發明的導線架’是於金屬板成形的導線架 中’僅於半導體元件搭載側表面及基板安裝側表面的必要 的最少限度部分實施鍍鈀處理，成形的導線部、焊墊部之 其他不需安裝的部分及側面則不予電鍍爲其特徵。 依此，實施鍍鈀處理的面積會成爲最少限度，因此與 以往全面實施鍍鈀處理的導線架比較，能夠提供廉價的導 線架。 又’依照本發明的導線架製造方法，是將金屬板成形 以準備導線架材料，於該導線架材料的半導體元件搭載部 分的必要的最少限度的位置’局部實施鍍鈀處理，然後於 前述導線架材料的金屬線接合部分以及基板安裝面側的焊 接部分等必要的最少限度的位置，局部實施鍍鈀處理。 經濟部智慧財產局員工消費合作社印製 又’依照本發明的導線架製造方法，是將金屬板成形 以準備導線架材料，僅於該導線架材料的半導體元件搭載 側表面實施鍍鈀處理’然後僅於前述導線架材料的基板安 衣側表面貝施鍍處理，前述導線架材料的導線部、焊墊 部之其他不需安裝的部分及側面則不予電鍍。 又，依照本發明的導線架製造方法，是將金屬板成形 且準備導線架材半斗，在該金屬板㈤表背兩面上設置抗餓層 ，在該抗蝕層表面密接具有所要的導線架形狀的遮罩，曝 光、顯影作成施行電鍍的遮罩後，在露出的金屬板表面施 本纸張尺度適用中國國家標準（CNS ) A4規格（2I0X 297公釐） -5- 1264099 A / B7 五、發明説明（3 ) (請先閱讀背面之注意事項再填寫本頁) 予電鍍，以設置至少包含鈀層的電鍍層，然後將前述遮罩 剝離，再度於兩面全面設置抗蝕層，使用具有預定式樣的 遮罩曝光、顯影以獲得蝕刻遮罩，然後蝕刻處理，將導線 部、焊墊部之其他形狀成形。 又，依照本發明的導線架製造方法，是將金屬板成形 以準備導線架材料，在該金屬板的表裡兩面上設置抗纟虫層 ，在該抗蝕層表面密接具有所要的導線架形狀的遮罩，曝 光、顯影作成施行電鍍的遮罩後，在露出的金屬板表面施 予電鍍，以設置至少包含鈀層的電鍍層，然後將前述遮罩 層去除，用前述電鍍層當作抗蝕層將金屬板蝕刻，該蝕刻 處理於前述金屬板需蝕刻部分即將貫通之前停止處理，將 前述金屬板背面以膠帶遮罩，再施予蝕刻處理使前述金屬 板需蝕刻部分貫通，由於前述膠帶，多數的導線部等會被 保持於各個獨立的關係位置。 經濟部智慧財產局員工消費合作社印製 又，依照本·發明的導線架製造方法，是將金屬板成形 以準備導線架材料，在該金屬板的表裡兩面上設置抗蝕層 ，在該抗蝕層表面密接具有所要的導線架形狀的遮罩，曝 光、顯影作成蝕刻遮罩後，將露出的金屬板部蝕刻去除， 以形成導線架形狀，然後在其表裡兩面電鍍，以設置至少 包含钯層的電鍍層。 又，依照本發明的導線架製造方法，是將金屬板成形 以準備導線架材料，在該金屬板的表裡兩面上設置抗蝕層 ，在該抗蝕層表面密接具有所要的導線架形狀的遮罩，曝 光、顯影作成施行電鍍的遮罩後，在露出的金屬板表面施 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） _ 6 _ 1264099 A 7 B7 五、發明説明（4 ) (請先閱讀背面之注意事項再填寫本頁) 予電鍍，以設置至少包含鈀層的電鍍層，然後將抗蝕層去 除，用前述電鍍層當作抗蝕層將金屬板蝕刻，以形成多數 •的導線部、焊墊部之其他形狀。 依照上述方法，不僅能夠提供比以往全面實施鍍鈀處 理的導線架價廉的導線架，在導線架預定位置搭載半導體 元件封上樹脂後，於切割成各個單片之際，應被切斷的金 屬部分因已由蝕刻處理所溶解，因此只要切斷樹脂即可， 所以能夠提供不會產生如以往的導線脫落或樹脂破損等不 良品質的導線架。 本發明除上述以外的目的、特徵及優點，由以下參照 附圖的詳細說明將更爲淸楚。 【圖面的簡單說明】 # 圖1 .:本發明導線架製造方法實施例之一的製程圖。 圖2 :本發0月導線架製造方法另一實施例的製程圖。 圖3 :本發明導線架製造方法再一實施例的製程圖。 圖4 ··本發明導線架製造方法再另一實施例的製程圖 〇 經濟部智慧財產局員工消貧合作社印製 【圖號說明】 1 金屬板 2 乾膜（dryfilm) 3 玻璃罩（glassmask) 3 a 導線架式樣 本紙痕尺度適用中國國家標準（CNS ) Α4規格（2!0Χ 297公慶） 1264099 B7五、發明説明（5 )
4 玻 璃 罩 4 a 導 線 架 式 樣 5、6 玻璃 罩 7 蝕 刻 液 噴 嘴 8 膠 W 經濟部智慧財產局員工消費合作社印製 【發明的最佳實施形態】 實施例1 圖1爲本發明導線架製造方法實施例之一的製程圖。 圖中，1爲要形成導線架的銅板等金屬板，2爲設置於金 屬板1的表裡兩面上的乾膜（d r y f i 1 m ) ，3爲被覆於設 置在金屬板1表面上的乾膜2上使用遮光劑形成導線架式 樣3 a的玻璃遮罩，4爲爲被覆於設置在金屬板1背面上 的乾膜2上，挾著金屬板1與導線架式樣3 a對稱而使用 遮光劑形成有導線架式樣4 a的玻璃遮罩，5、6爲形成 有所需的遮光式樣的玻璃遮罩，7爲挾著金屬板1予以相 向設置的複數的蝕刻液噴嘴。 其次循序說明導線架的製程。首先，如圖1 ( a )所 示，在金屬板1的表裡兩面全面設置作爲遮光罩的乾膜2 後，將具有導線架式樣3 a 、4 a的玻璃遮罩3、4以對 準位置的狀態被覆於表裡兩面上，將此兩面介著玻璃遮罩 3、4以紫外光曝光。 曝光後將玻璃遮罩3、4拆下，將附有乾膜的金屬板 1浸入顯影液予以顯影，則如圖1 ( b )所示，只有照到 (請先閱讀背面之注意事項再填寫本頁) 訂 本纸乐尺度適用中國國家標準（CNS ) A4規格（MOXW7公釐） 1264099 B7 五、發明説明（6 ) 紫外光的部分亦即金屬線接合部和半導體元件搭載部等需 要鍍上鈀部分的乾膜2會被去除。 (讀先閲讀背面之注意事項再填寫本頁) 然後，將此放入電鍍槽，如圖1 ( c )放大所示，逐 次在必要的部分進行鎳（N 1 )、鈀（P d )、金（A u )等必要的電鍍處理。然後，剝離乾膜2就能獲得附有如 圖1 ( d )所示的剖面形狀的電鍍層1 a的金屬板1 。 於如此獲得的附有電鍍層1 a的金屬板1的表裡兩面 全部再設置乾膜2，如圖1 ( e )所示，在其上面被覆著 形成有僅已施行電鍍部分會被遮光的式樣的玻璃遮罩5、 6，再將兩面以紫外光曝光。然後，與在圖1 ( b )所說 明的一樣進行顯影，而獲得附有如圖1 ( f )所示的剖面 形狀的電鍍層1 a的金屬板1。 在此附有電鍍層1 a的金屬板1的兩面，如圖1 ( g )所示，.由噴嘴7噴灑蝕刻液進行蝕刻處理。由此蝕刻處 理’未施予電鍍部分的金屬被溶解去除，最後剝離乾膜2 就能獲得具有如圖1 ( h )所示的剖面形狀亦即僅在必要 的最少限度部分施予電鍍處理的二架分的導線架。 圖1 ( a )至（h )的各製程，是包含導線架數架分 經濟部智慧財產局資工消費合作社印說 的長度的金屬板以適當的輸送帶運送而連續地進行，於製 程最後截斷而完成各個導線架。由此說明可知，各導線架 成爲僅於表裡兩面的必要位置鍍上鈀的結果。 實施例2 圖2爲本發明導線架製造方法的另一實施例的製程圖 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -9 - 1264099 經濟部智慧財產局員工消費合作社印製 五、發明説明（7 ) 。圖中’與圖1所使用的實質上相同的構件及部分，賦予 相同的圖號 > 對於這些則省略其說明。與圖1比較可知， (a) 、 （b) 、 （c)及（d)所示的各製程因與 圖1相同故省略其說明，茲說明圖2 ( e )以下所示的製 程。 如圖2 ( e )所示，在附有電鍍層1 a的金屬板1的 兩面，由噴嘴7噴灑蝕刻液進行蝕刻處理。此融刻處理是 進行到未施予電鍍部分的金屬絕大部分被溶解去除只剩下 極薄的程度。 於如此獲得的附有電鍍層1 a金屬板1的一邊全面， 如圖2 ( f )所不黏貼膠帶8後，如圖2 ( g )所示從沒 有貼膠帶8的一邊，再以噴嘴7噴灑蝕刻液進行蝕刻處理 ’將剩下極薄的未施予電鍍的金屬部分（連接導線部的繫 條（tie bar )和吊導線部等’於組裝後要被切斷不要的部 分）完全溶解去除。此時，剩下的施有電鍍的金屬部分亦 即要搭載半導體元件的焊墊部和導線部等必要部分，如圖 2 ( h )所示’由膠帶8確實保持其相對關係位置而不致 移位。 實施例3 圖3爲本發明導線架製造方法的再一實施例的製程圖 。圖中，與圖1所使用的實質上相同的構件及部分，賦予 相同的圖號，對於這些則省略其說明。與圖1比較可知， 圖3 ( a )及（b )所示的各製程因與圖1相同故省略其 (請先閲讀背面之注意事項再填寫本頁) 裝--- 訂 I# 本纸張尺度適用t國國家標準（CNS ) A4規格（210χ297公釐） -10- 1264099
五、發明説明（8 ) 說明 '纽說明圖3 ( c )以下所示的製程。 如圖3 ( c )所示，對應導線架式樣而剩有乾膜2的 金屬板1的兩面，由噴嘴7噴灑融刻液進行融刻處理。此 蝕刻處理，沒有乾膜2存在的部分的金屬會被溶解去除， 一直進行到如圖3 ( d )所示金屬板1穿孔的狀態。從穿 孔狀態的金屬板1的兩面剝離乾膜2 ，製作成具有圖3 ( d )所示的橫剖面的導線架材料。 於如此獲得的導線架材料（金屬板1 )的表裡兩面的 必要位置，各施予如圖3 ( e )放大所示的鍍鎳（N i ) 、鍍銷（P d )、鍍金（A u )，而完成導線架。亦即， 如圖3 ( f )所示’首先在導線架表裡兩面全部施予鍍鎳 (N i )作爲基層’然後如圖3 (g)所示，僅於半導體 搭載部分和金屬線接合部分以及基板安裝面側的焊接部分 等必要的最少限度的位置鍍上銷（p d )，最後如圖3 ( h )所示，在導篇架表裡兩面全部鍍金（a u )，而完成 導線架。如此’導線架的完成品抑制了高價的鈀的使用量 於最少限度’因而比以往的導線架價廉。 實施例4 圖4爲本發明導線架製造方法的再另一實施例的製程 圖。圖中，與圖1所使用的實質上相同的構件及部分，賦 予相同的圖號’對於這些則省略其說明。與圖1比較可知 ，圖4 ( a )至（d )所示的各製程因與圖丄相同故省略 其說明，茲說明圖4 ( e )以下所示的製程。 〈%先聞讀弩”&之：泛意事項再填寫本頁) 一裝----^---訂— 經濟部智慧財產局員工消f合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 1264099 B7 五、發明説明（9 ) 此實施例不進行第2次的曝光及顯影，而如圖4 ( e )所示，於4 ( d )所獲得的作完電鍍處理的金屬板1兩 面，以噴嘴7噴灑蝕刻液予以蝕刻處理而獲得製品這一點 與第1實施例不同。依照此實施例能夠提供更廉價的製品 〇 如上所述，依照本發明，不但能夠提供遠比以往的方 法廉價的導線架，並且能夠提供不會產生導線脫落或樹脂 破損等不良品質的導線架。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標孪（CNS ) A4現格（2丨0X 297公釐） -12 -

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12640雜 i 中文申請圍省辱,丨 ]18 上替換魂 民國94年9月19日修正 六、申請專利範圍 1 1 . 一種導線架的製造方法，其特徵爲： 在要用來形成導線架的金屬板設置抗蝕層，作成用來 實施電鍍處理的遮罩，在金屬板表面設置了含有鈀層的電 鍍層，將上述遮罩剝離，再度設置抗蝕層，藉由具有預定 式樣的蝕刻用遮罩進行蝕刻處理，藉由作成導線部、焊墊 部以及其他的形狀，於半導體元件搭載部分與金屬線接合 部分以及基板安裝面側的焊接部分的最少需要限度的位置 ，局部性地實施鍍鈀處理。 -- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）
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Publication number Priority date Publication date Assignee Title
US6943434B2 (en) * 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US8120152B2 (en) 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US8375577B2 (en) * 2008-06-04 2013-02-19 National Semiconductor Corporation Method of making foil based semiconductor package
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5629969B2 (ja) 2008-09-29 2014-11-26 凸版印刷株式会社 リードフレーム型基板の製造方法と半導体装置の製造方法
JP4670931B2 (ja) * 2008-09-29 2011-04-13 住友金属鉱山株式会社 リードフレーム
JP5493323B2 (ja) * 2008-09-30 2014-05-14 凸版印刷株式会社 リードフレーム型基板の製造方法
JP5549066B2 (ja) * 2008-09-30 2014-07-16 凸版印刷株式会社 リードフレーム型基板とその製造方法、及び半導体装置
KR101148100B1 (ko) * 2008-10-22 2012-05-22 엘지이노텍 주식회사 다열형 리드프레임 및 반도체 패키지의 제조방법
KR101064755B1 (ko) * 2008-12-24 2011-09-15 엘지이노텍 주식회사 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
CN102324414B (zh) * 2011-09-13 2013-06-26 江苏长电科技股份有限公司 有基岛预填塑封料先镀后刻引线框结构及其生产方法
CN102403282B (zh) * 2011-11-22 2013-08-28 江苏长电科技股份有限公司 有基岛四面无引脚封装结构及其制造方法
CN102661829A (zh) * 2012-04-28 2012-09-12 无锡永阳电子科技有限公司 So8塑料封装传感器
CN103456645B (zh) * 2013-08-06 2016-06-01 江阴芯智联电子科技有限公司 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法
CN103413766B (zh) * 2013-08-06 2016-08-10 江阴芯智联电子科技有限公司 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法
CN103400771B (zh) * 2013-08-06 2016-06-29 江阴芯智联电子科技有限公司 先蚀后封芯片倒装三维系统级金属线路板结构及工艺方法
US10141197B2 (en) 2016-03-30 2018-11-27 Stmicroelectronics S.R.L. Thermosonically bonded connection for flip chip packages
JP6777365B2 (ja) * 2016-12-09 2020-10-28 大口マテリアル株式会社 リードフレーム
CN113838761A (zh) * 2021-11-24 2021-12-24 新恒汇电子股份有限公司 物联网工业级卡的制备方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050349B2 (ja) * 1980-07-09 1985-11-08 住友金属鉱山株式会社 リ−ドフレ−ムの製造方法
US4770899A (en) 1987-06-10 1988-09-13 Unisys Corporation Method of coating copper conductors on polyimide with a corrosion resistant metal, and module produced thereby
KR920008359Y1 (ko) * 1989-11-28 1992-11-20 현대전자산업 주식회사 리드프레임
US5235139A (en) 1990-09-12 1993-08-10 Macdermid, Incorprated Method for fabricating printed circuits
US5234139A (en) * 1991-08-06 1993-08-10 Korenstein Michael W Apparatus for the management of paired garments
JP3275413B2 (ja) * 1993-01-21 2002-04-15 凸版印刷株式会社 リードフレームおよびその製造方法
JP2004343136A (ja) * 1995-09-29 2004-12-02 Dainippon Printing Co Ltd 半導体装置
US5804880A (en) * 1996-11-04 1998-09-08 National Semiconductor Corporation Solder isolating lead frame
JP2002511187A (ja) * 1997-01-30 2002-04-09 ジィ・シィ・ビィ・テクノロジーズ・リミテッド・ライアビリティ・カンパニー 予めめっきされたリードを有する改善されたリードフレーム構造およびその製造方法
DE19704689A1 (de) * 1997-02-07 1998-08-13 Emitec Emissionstechnologie Wabenkörper mit im Inneren freiem Querschnittsbereich, insbesondere für Kleinmotoren
US5923090A (en) * 1997-05-19 1999-07-13 International Business Machines Corporation Microelectronic package and fabrication thereof
CN1068064C (zh) * 1997-05-27 2001-07-04 旭龙精密工业股份有限公司 引线框架及其制造方法
US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
EP0921562A3 (en) * 1997-10-28 2002-06-05 Texas Instruments Incorporated Improvements in or relating to lead frames
KR100275381B1 (ko) * 1998-04-18 2000-12-15 이중구 반도체 패키지용 리드프레임 및 리드프레임도금방법
JP4156087B2 (ja) * 1998-08-07 2008-09-24 大日本印刷株式会社 電着処理装置
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
US6469386B1 (en) * 1999-10-01 2002-10-22 Samsung Aerospace Industries, Ltd. Lead frame and method for plating the same
KR100450091B1 (ko) * 1999-10-01 2004-09-30 삼성테크윈 주식회사 반도체 장치용 다층 도금 리드 프레임
JP2001185670A (ja) * 1999-12-10 2001-07-06 Texas Instr Inc <Ti> リードフレームとその製法
KR100421774B1 (ko) * 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
US6827584B2 (en) * 1999-12-28 2004-12-07 Formfactor, Inc. Interconnect for microelectronic structures with enhanced spring characteristics
US7026710B2 (en) * 2000-01-21 2006-04-11 Texas Instruments Incorporated Molded package for micromechanical devices and method of fabrication
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
KR100371567B1 (ko) * 2000-12-08 2003-02-07 삼성테크윈 주식회사 Ａｇ 선도금을 이용한 반도체 패키지용 리드프레임
US20020170878A1 (en) * 2001-03-27 2002-11-21 Bmc Industries, Inc. Etching resistance of protein-based photoresist layers
JP2002299540A (ja) * 2001-04-04 2002-10-11 Hitachi Ltd 半導体装置およびその製造方法
JP4173346B2 (ja) * 2001-12-14 2008-10-29 株式会社ルネサステクノロジ 半導体装置
US6713852B2 (en) * 2002-02-01 2004-03-30 Texas Instruments Incorporated Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin
JP2003297994A (ja) * 2002-03-29 2003-10-17 Hitachi Ltd 半導体装置およびその製造方法
TW558776B (en) * 2002-08-22 2003-10-21 Fu Sheng Ind Co Ltd Double leadframe package

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US20070141756A1 (en) 2007-06-21
CN1317762C (zh) 2007-05-23
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US20040169261A1 (en) 2004-09-02
US7235868B2 (en) 2007-06-26
HK1069010A1 (en) 2005-05-06
ATE546835T1 (de) 2012-03-15
US7521295B2 (en) 2009-04-21
US20050153482A1 (en) 2005-07-14
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