ATE546835T1 - Verfahren zur herstellung eines leiterrahmens - Google Patents
Verfahren zur herstellung eines leiterrahmensInfo
- Publication number
- ATE546835T1 ATE546835T1 AT02743870T AT02743870T ATE546835T1 AT E546835 T1 ATE546835 T1 AT E546835T1 AT 02743870 T AT02743870 T AT 02743870T AT 02743870 T AT02743870 T AT 02743870T AT E546835 T1 ATE546835 T1 AT E546835T1
- Authority
- AT
- Austria
- Prior art keywords
- producing
- conductor frame
- plated
- mounting surface
- palladium
- Prior art date
Links
- 239000004020 conductor Substances 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract 2
- 229910052763 palladium Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/48664—Palladium (Pd) as principal constituent
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85464—Palladium (Pd) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- ing And Chemical Polishing (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001207316A JP4852802B2 (ja) | 2001-06-19 | 2001-07-09 | リードフレーム |
PCT/JP2002/006933 WO2003007373A1 (fr) | 2001-07-09 | 2002-07-09 | Cadre de montage |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE546835T1 true ATE546835T1 (de) | 2012-03-15 |
Family
ID=19043321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT02743870T ATE546835T1 (de) | 2001-07-09 | 2002-07-09 | Verfahren zur herstellung eines leiterrahmens |
Country Status (9)
Country | Link |
---|---|
US (3) | US7235868B2 (de) |
EP (2) | EP2312630A1 (de) |
KR (2) | KR100908891B1 (de) |
CN (1) | CN1317762C (de) |
AT (1) | ATE546835T1 (de) |
ES (1) | ES2383874T3 (de) |
HK (1) | HK1069010A1 (de) |
TW (1) | TWI264099B (de) |
WO (1) | WO2003007373A1 (de) |
Families Citing this family (21)
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US6943434B2 (en) * | 2002-10-03 | 2005-09-13 | Fairchild Semiconductor Corporation | Method for maintaining solder thickness in flipchip attach packaging processes |
US8115285B2 (en) * | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
US8375577B2 (en) * | 2008-06-04 | 2013-02-19 | National Semiconductor Corporation | Method of making foil based semiconductor package |
US20100044850A1 (en) * | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
JP4670931B2 (ja) * | 2008-09-29 | 2011-04-13 | 住友金属鉱山株式会社 | リードフレーム |
JP5629969B2 (ja) | 2008-09-29 | 2014-11-26 | 凸版印刷株式会社 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
JP5493323B2 (ja) * | 2008-09-30 | 2014-05-14 | 凸版印刷株式会社 | リードフレーム型基板の製造方法 |
JP5549066B2 (ja) * | 2008-09-30 | 2014-07-16 | 凸版印刷株式会社 | リードフレーム型基板とその製造方法、及び半導体装置 |
KR101148100B1 (ko) * | 2008-10-22 | 2012-05-22 | 엘지이노텍 주식회사 | 다열형 리드프레임 및 반도체 패키지의 제조방법 |
KR101064755B1 (ko) * | 2008-12-24 | 2011-09-15 | 엘지이노텍 주식회사 | 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법 |
US8124447B2 (en) * | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US20110163430A1 (en) * | 2010-01-06 | 2011-07-07 | Advanced Semiconductor Engineering, Inc. | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof |
CN102324414B (zh) * | 2011-09-13 | 2013-06-26 | 江苏长电科技股份有限公司 | 有基岛预填塑封料先镀后刻引线框结构及其生产方法 |
CN102403282B (zh) * | 2011-11-22 | 2013-08-28 | 江苏长电科技股份有限公司 | 有基岛四面无引脚封装结构及其制造方法 |
CN102661829A (zh) * | 2012-04-28 | 2012-09-12 | 无锡永阳电子科技有限公司 | So8塑料封装传感器 |
CN103456645B (zh) * | 2013-08-06 | 2016-06-01 | 江阴芯智联电子科技有限公司 | 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法 |
CN103400771B (zh) * | 2013-08-06 | 2016-06-29 | 江阴芯智联电子科技有限公司 | 先蚀后封芯片倒装三维系统级金属线路板结构及工艺方法 |
CN103413766B (zh) * | 2013-08-06 | 2016-08-10 | 江阴芯智联电子科技有限公司 | 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法 |
US10141197B2 (en) | 2016-03-30 | 2018-11-27 | Stmicroelectronics S.R.L. | Thermosonically bonded connection for flip chip packages |
JP6777365B2 (ja) * | 2016-12-09 | 2020-10-28 | 大口マテリアル株式会社 | リードフレーム |
CN113838761A (zh) * | 2021-11-24 | 2021-12-24 | 新恒汇电子股份有限公司 | 物联网工业级卡的制备方法 |
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KR100371567B1 (ko) * | 2000-12-08 | 2003-02-07 | 삼성테크윈 주식회사 | Ag 선도금을 이용한 반도체 패키지용 리드프레임 |
US20020170878A1 (en) * | 2001-03-27 | 2002-11-21 | Bmc Industries, Inc. | Etching resistance of protein-based photoresist layers |
JP2002299540A (ja) * | 2001-04-04 | 2002-10-11 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP4173346B2 (ja) * | 2001-12-14 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US6713852B2 (en) * | 2002-02-01 | 2004-03-30 | Texas Instruments Incorporated | Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin |
JP2003297994A (ja) * | 2002-03-29 | 2003-10-17 | Hitachi Ltd | 半導体装置およびその製造方法 |
TW558776B (en) * | 2002-08-22 | 2003-10-21 | Fu Sheng Ind Co Ltd | Double leadframe package |
-
2002
- 2002-07-09 TW TW091115221A patent/TWI264099B/zh not_active IP Right Cessation
- 2002-07-09 US US10/482,962 patent/US7235868B2/en not_active Expired - Fee Related
- 2002-07-09 AT AT02743870T patent/ATE546835T1/de active
- 2002-07-09 ES ES02743870T patent/ES2383874T3/es not_active Expired - Lifetime
- 2002-07-09 EP EP11153697A patent/EP2312630A1/de not_active Ceased
- 2002-07-09 WO PCT/JP2002/006933 patent/WO2003007373A1/ja active Application Filing
- 2002-07-09 KR KR1020037003365A patent/KR100908891B1/ko active IP Right Grant
- 2002-07-09 KR KR1020097000226A patent/KR101021600B1/ko active IP Right Grant
- 2002-07-09 EP EP02743870A patent/EP1406300B1/de not_active Expired - Lifetime
- 2002-07-09 CN CNB028137310A patent/CN1317762C/zh not_active Expired - Lifetime
-
2004
- 2004-12-31 HK HK04110373A patent/HK1069010A1/xx not_active IP Right Cessation
-
2005
- 2005-03-10 US US11/075,878 patent/US20050153482A1/en not_active Abandoned
-
2007
- 2007-02-15 US US11/706,360 patent/US7521295B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050153482A1 (en) | 2005-07-14 |
HK1069010A1 (en) | 2005-05-06 |
TWI264099B (en) | 2006-10-11 |
WO2003007373A1 (fr) | 2003-01-23 |
US20040169261A1 (en) | 2004-09-02 |
ES2383874T3 (es) | 2012-06-27 |
EP2312630A1 (de) | 2011-04-20 |
EP1406300A4 (de) | 2007-11-21 |
US20070141756A1 (en) | 2007-06-21 |
EP1406300B1 (de) | 2012-02-22 |
CN1526167A (zh) | 2004-09-01 |
KR20030060885A (ko) | 2003-07-16 |
EP1406300A1 (de) | 2004-04-07 |
KR101021600B1 (ko) | 2011-03-17 |
CN1317762C (zh) | 2007-05-23 |
KR100908891B1 (ko) | 2009-07-23 |
KR20090009995A (ko) | 2009-01-23 |
US7521295B2 (en) | 2009-04-21 |
US7235868B2 (en) | 2007-06-26 |
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