CN1068064C - 引线框架及其制造方法 - Google Patents

引线框架及其制造方法 Download PDF

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CN1068064C
CN1068064C CN97113487A CN97113487A CN1068064C CN 1068064 C CN1068064 C CN 1068064C CN 97113487 A CN97113487 A CN 97113487A CN 97113487 A CN97113487 A CN 97113487A CN 1068064 C CN1068064 C CN 1068064C
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lead frame
layer
palladium
silver layer
manufacture method
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CN1200568A (zh
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黄志恭
赖威仁
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Fusheng Co Ltd
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XULONG PRECISION INDUSTRY Co Ltd
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Abstract

一种引线框架及其制造方法，其具有如下镀层结构；一引线框架底材；一银层在该底材表面；以及一钯层在银层表面。其中，银层与底材之间可以有一铜层及一镍层，银层与钯层之间可以有一钯镍层，而钯层上可以有一金层。然而，钯层及钯镍层可全面性分布在引线框架表面，或选择性分布在引线框架封装区域之外。金层则是选择性分布在引线框架封装区域之外。

Description

引线框架及其制造方法
本发明是有关于一种引线框架及其制造方法，且特别是有关于一种镀有银及钯的引线框架及其制造方法。
在半导体生产业中，集成电路的封装(IC package)是制造的重要步骤之一。其中，IC引线框架(IC lead frame)是提供集成电路芯片安放导线的基座，并将IC芯片与印刷电路板连接起来。已知引线框架制造至少需要考虑三种特性，即接合性(bondability)，封装性(molding compound characteristic)以及焊接性(solderability)，因此引线框架的表层常有一些镀层用来调整此三种特性。
已知的引线框架为了让连接IC芯片的金导线(gold wire)与引线(lead)间有较佳的电接合性，会在焊接区(bonding area)电镀一层银(Ag)。在焊上金导线及塑胶外壳封装后，外引线(extemal lead)再镀上一层锡铅(Sn/Pb)，以增加其焊接性。由于已知的封装程序中锡铅的电镀是在塑料外壳封装后进行，而镀锡铅的步骤中具有高温，可能会损害IC芯片。此外，锡铅电镀会造成重金属污染，并由于银的电镀在封装前实施，而锡铅电镀则在封装后实施，造成封装自动化的困难。因此开发出了预镀引线框架(Pre-Plated Frame,PPF)技术。
所谓PPF技术，是选择贵金属钯(palladium,Pd)以取代常用的银与锡铅(参见美国专利US874916,USl74060)。由于钯具有较好的接合性及焊接性，已知PPF技术是在封装前将引线框架全面性镀钯，以便今后继续进行自动化封装，而无需镀锡铅。已知PPF技术不但解决了环保问题，还实现了自动化制作。为了让引线框架具有较佳的耐蚀性，已知会在镀钯之前选镀上一层镍及一层钯镍合金。由于钯属于贵金属，价钱昂贵，为了节省成本，镀钯层都很薄，约0.075～0.1μm。因此在封装过程中，容易形成针孔(pin hole)缺陷使得镍层或钯镍层极易局部裸露，造成接合性及焊接性不良，影响产品品质。
因此本发明的目的在于提供一种新型的引线框架及其制造方法，在镀钯层前，全面性镀一层银，避免镍层裸露，且钯可选择性或全面性电镀在引线框架的银层上。
本发明的目的是这样实现的，即采用一种引线框架的制造方法，应用于引线框架的电镀过程中，该制造方法包括下列步骤：提供一引线框架，并封该引线框架作一电镀前处理，该引线框架包括一封装区，该封装区中有一焊接区；刮镀一银层在该导线表面；以及电镀一钯层在该银层表面。
根据本发明的又一方面，提供一种为一集成电路提供电连接的引线框架，其中该引线框架包括一芯片座及多个引线，其中该芯片座用来承载该集成电路，这些引线用来与该集成电路连接；且该引线框架包括一封装区，而该封装区具有一焊接区，该引线框架包括：一底材；一第一银层在该底材表面；以及一钯层在该第一银层表面。
根据本发明的再一方面，提供一种为一集成电路提供电连接的引线框架，其特征在于，该引线框架包括一芯片座及多个引线，其中该芯片座用来承载该集成电路，这些引线用来与该集成电路连接；且该引线框架包括一封装区，而该封装区具有一焊接区，该引线框架包括：一底材；一在该底材表面的第一银层；以及一在该第一银层表面的钯层。
本发明的优点在于可降低制造成本，并取代常用锡铅，解决环保问题。同时兼顾了引线框架的接合性，封装性及焊接性。
下面借助附图所示实施例对本发明作进一步的详细说明，附图中：
图1为一种引线框架的平面结构图；
图2A为本发明第一实施例的引线框架的剖示图；
图3A为该第一实施例的第一变型的剖示图；
图4A为该第一实施例的第二变型的剖示图；
图5A为该第一实施例的第三变型的剖示图；
图2B至图5B为相对于图2A至图5A的另一种引线框架的变化结构；
图6A为本发明第二实施例的引线框架的剖示图；
图6B至6C为相对于图6A的另一种引线框架的变化结构。
图1所示为一种引线框架的平面结构。一般引线框架依其平面结构可区分为两部分，一是平坦部，一是引线部份。平坦部就是所谓的芯片座2(bar pador die pad)，用以承载芯片。引线的部份一般又区分为几部分：内引线区4(internal lead)，引线肩部6(lead shoulder)及外引线区8(external lead)。整体而言，又可区分一封装区12(package area，中心线所包围的区域)，即集成电路(IC)封装的区域，而封装区12内又包含一焊接区10(bonding area or coinarea)，即焊接用的区域。内引线区4中包含在焊接区中的部份又称为焊接引线端14(coin lead tip)，用来连接芯片的导线固定在引线上。此外，为了配合装配及自动化，引线框架还包括导轨16(side rail)，用以连接各片引线框架。导引孔18(pilot hole)作为装配时对准用。连接杆20(tie bar)使芯片座2与导轨16连接固定。阻挡杆22(dam bar)用以封装时防止塑胶外溢。
图2A为本发明第一实施例的引线框架的剖示图。图2A中，区域120是封装区；区域121是封装区120外的区域，即引线肩部及外引线区；区域100是焊接区；而区域200是芯片座。
此引线框架的制造程序包括：提供一引线框架30，此引线框架30具有类似图1的结构，其材质包括铜合金(Alloy194,C7025,KCF125,EFTEC等)或镍铁合金(Ni-Fe 42 Alloy)。将此引线框架30经过一连串电镀前处理，比如：脱脂，活化，蚀刻及中和，以及全面性刮镀(strike)一铜层32，再全面性电镀(plating)一镍层34。全面性刮镀铜层32是当所获得的原料表面性质不佳时，用来改善底材表面性质。全面性电镀镍层34，则是用来防止腐蚀。因此，铜层32及镍层34皆非必要的镀层，当原料表面性质良好时，刮镀铜层32的步骤得以省略，而镍层34也可由其后续的防腐蚀性镀层所取代。
接着，全面性刮镀一第一银层36。选择性地在焊接区100点镀(spot)一第二银层39，及选择性地在封装区外121电镀一钯层38。然后，剥除封装区120内未被第二银层39覆盖的第一银层36，以暴露出其下方的镍层34。至此即完成本发明的引线框架。
经过上述制造程序，本发明引线框架具有下列结构：一引线框架底材30，比如是铜合金。一铜层32在此底材30表面。一镍层34在铜层32表面。一第一银层36在焊接区100与封装区外121的镍层34表面。一钯层38在封装区外121的第一银层36表面。一第二银层39在焊接区100内的第一银层表面。其中，铜层32及镍层34并非必要，第一银层36亦可以直接镀在底材表面。
制造完成的引线框架经过自动化的封装过程，芯片40将借助粘结剂42(一般为银胶，AgEpoxy)固定在引线框架的芯片座上；再经过导线键合程序，金质导线44将芯片与引线连接起来，而塑胶46是用来封装芯片40与导线44。
此实施例的特征在于选择性镀钯层38在封装区域外，并于钯层38之下具有一银层36。本实施例除上述制造程序与结构之外，依照本实施例特征的引线框架，在选择性镀钯层38的步骤中还有下列几种类似的变化型：
(1)请参照图3A，在全面性刮镀第一银层36在镍层34表面之后，在焊接区100点镀第二银层39。选择性地在封装区外121电镀一钯镍层48，然后再选择性地在封装区外121电镀钯层38。剥除封装区120内未被第二银层39覆盖的第一银层36，以暴露出其下方的镍层34。因此，在结构上第一银层36在封装区外121的表面有一钯镍层48，而钯镍层48上为一钯层38。
(2)请参照图4A，在全面性刮镀第一银层36在镍层34表面之后，在焊接区100点镀第二银层39。选择性地在封装区外121电镀钯层38，然后再选择性地在封装区外121闪镀(flash)一金层50。剥除封装区120内未被第二银层39覆盖的第一银层36，以暴露出其下方的镍层34。因此，在结构上第一银层36在封装区外121的表面有一钯层38，而钯层38上为一金层50。
(3)请参照图5A，在全面性刮镀第一银层36在镍层34表面之后，在焊接区100点镀第二银层39。并选择性地在封装区外121电镀一钯镍层48，然后再选择性地在封装区外121电镀钯层38。接着，选择性在封装区外121闪镀一金层50。剥除封装区120内未被第二银层39覆盖的第一银层36，以暴露出其下方的镍层34。因此，在结构上第一银层36在封装区外121的表面有一钯镍层48，而钯镍层48上为一钯层38，而钯层38上为一金层50。
然而，上述四种形式的引线框架中，第一银层36与第二银层39也可以用环型电镀(ring plating)的方式来形成。即全面性刮镀第一银层36，改为环型刮镀第一银层36在芯片座200外区域的镍层34表面。而在焊接区100点镀第二银层39，则改为在焊接区100环型点镀第二银层39在芯片座200外的焊接区100。因此上述四种引线框架变成如图2B，图3B，图4B及图5B的结构。图2B，图3B，图4B及图5B相对于图2A，图3A，图4A及图5A的差异在于芯片座200部份没有第一银层及第二银层。
本发明第一实施例的引线框架，具有下列特征及优点：
A．封装区外以电镀钯层取代常用的锡铅层，可解决环保问题。
B．采用选择性镀钯取代常用全面性镀钯，可降低制造成本。
C．焊接区内表面为银，故常用的封装机器封装及组装的自动化参数无需更改，可方便地使用在现有机器，且银与金质导线及银胶有不错的接合性。
D．由于钯层下方有镀银层，故在封装时可解决针孔裸露造成的焊接性不良的问题。
E．引线框架的电镀过程在封装前完成，具有PPF特性，可与自动化封装过程结合。
F．采用选择性镀钯，封装区内非焊接区为裸露的镍层或铜材具有较佳的封装性。
图6A所示为本发明另一实施例的引线框架的剖示图。此引线框架的制造程序包括：提供一引线框架30，此引线框架30具有类似图1的结构，其材质包括铜合金(Alloy 194,C7025,KCF125,EFTEC等)或镍铁合金(Ni-Fe42 Allov)。将此引线框架30经过一连串电镀前处理，例如：脱脂，活化，蚀刻及中和，及全面性刮镀(strike)一铜层32，再电镀(plating)一镍层34。全面性刮镀铜层32是当所获得的原料表面性质不佳时，用来改善底材表面性质。全面性电镀镍层34，则是用来防止腐蚀。因此，铜层32及镍层34均非必要的镀层，当原料表面性质良好时，刮镀铜层32的步骤得以省略，而镍层34也可由其后续的防腐蚀性镀层所取代。
接着刮镀一银层36，全面性地电镀一钯镍层52，以及电镀一钯层54，至此即完成本发明的引线框架。其中钯镍层52可视需要选用，亦可不采用而直接电镀钯层54。
经过上述制造程序，本发明的一引线框架具有下列结构：一引线框架底材30，例如是铜合金。一铜层32在此底材30表面。一镍层34在铜层32表面。一银层36在镍层34表面。一钯镍层52在银层36表面。一钯层54在钯镍层52表面。其中，铜层32及镍层34并非必要，银层36亦可以直接镀在底材表面。此实施例的特征在于钯层54之下具有一银层36。
制造完成的引线框架经过自动化封装过程，芯片40将借助粘结剂42固定在引线框架的芯片座上；再经过导线键合程序，金质导线44将芯片与引线连接起来，而塑胶46是用来封装芯片40与导线44。
然而，在第二实施例中，刮镀银层36亦有几种变型：
(1)银层36只刮镀在导线键合区100的镍层34表面，而后续的钯镍层52或钯层54的电镀均为全面性。因此可得到如图6B的结构。
(2)银层36只刮镀在导线键合区100及封装区外121的镍层34表面，而后续的钯镍层52或钯层54的电镀均为全面性。因此可得到如图6C的结构。
依照本发明第二实施例的引线框架，在镀钯层之前，以银刮镀在其底下，可免除导线键合过程中因针孔裸露造成焊接区接合性劣化，及封装区域外焊接性劣化的问题。此外，无须闪镀一层金，以补强厚度较薄的钯层，可降低制造成本。而两种变型则可预防封装时因针孔裸露造成封装区封装性劣化。

Claims (43)

1．一种引线框架的制造方法，应用于引线框架的电镀过程中，其特征在于，该制造方法包括下列步骤：
提供一引线框架，并对该引线框架作一电镀前处理，该引线框架包括一封装区，该封装区中有一焊接区；
刮镀一银层在该引线框架表面；以及
电镀一钯层在该银层表面。
2．如权利要求1所述的制造方法，其特征在于，该引线框架材质包括铜合金。
3．如权利要求1所述的制造方法，其特征在于，该引线框架材质包括镍铁合金。
4．如权利要求1所述的制造方法，其特征在于，该电镀前处理包括：
对该引线框架进行脱脂、活化、蚀刻以及中和处理；
在该引线框架表面刮镀一铜层；以及
在该铜层表面电镀一镍层。
5．如权利要求1所述的制造方法，其特征在于，该电镀前处理包括对该引线框架进行脱脂、活化、蚀刻以及中和处理。
6．如权利要求1所述的制造方法，其特征在于，该电镀前处理包括：
对该引线框架进行脱脂、活化、蚀刻以及中和处理；以及
刮镀一铜层在该引线框架表面。
7．如权利要求1所述的制造方法，其特征在于，该电镀前处理包括：
对该引线框架进行脱脂、活化、蚀刻以及中和处理；以及
刮镀一镍层在该引线框架表面。
8．如权利要求1所述的制造方法，其特征在于，电镀一钯层的步骤更包括下列步骤：
在该银层表面电镀一钯镍层；以及
在该钯镍层表面电镀一钯层。
9．如权利要求1所述的制造方法，其特征在于，该银层仅刮镀在焊接区的引线框架表面。
10．如权利要求1所述的制造方法，其特征在于，该银层仅刮镀在该焊接区及该封装区外的引线框架表面。
11．如权利要求9所述的制造方法，其特征在于，该底材材质包括镍铁合金。
12．根据权利要求1所述的制造方法，其特征在于，所述焊接区中有一芯片座；所述方法还包括在该焊接区的该第一银层表面选择性点镀一第二银层的步骤；
电镀钯层的步骤是在该引线框架封装区外的第一银层表面选择性电镀钯层；以及所述方法还包括剥除该封装区中未被该第二银层覆盖的该第一银层的步骤。
13．如权利要求12所述的制造方法，其特征在于，该电镀前处理包括：
对该引线框架进行脱脂、活化、蚀刻以及中和处理；
刮镀一铜层在该引线框架表面；以及
电镀一镍层在该铜层表面。
14．如权利要求12所述的制造方法，其特征在于，该电镀前处理包括对该引线框架进行脱脂、活化、蚀刻以及中和处理。
15．如权利要求12所述的制造方法，其特征在于，该电镀前处理包括：
对该引线框架进行脱脂、活化、蚀刻以及中和处理；以及
刮镀一铜层在该引线框架表面。
16．如权利要求12所述的制造方法，其特征在于，该电镀前处理包括：
对该引线框架进行脱脂、活化、蚀刻以及中和处理；以及
刮镀一镍层在该引线框架表面。
17．如权利要求12所述的制造方法，其特征在于，该引线框架的材质包括铜合金。
18．如权利要求12所述的制造方法，其特征在于，该引线框架的材质包括镍铁合金。
19．如权利要求12所述的制造方法，其特征在于，选择性电镀一钯层的步骤更包括下列步骤：
在该引线框架封装区外的该第一银层表面选择性电镀一钯镍层；以及
在该引线框架封装区外的该钯镍层表面选择性电镀一钯层。
20．如权利要求12所述的制造方法，其特征在于，还包括在该引线框架封装区外的该钯层表面上选择性闪镀一金层。
21．如权利要求19所述的制造方法，其特征在于，还包括在该引线框架封装区外的该钯层表面上选择性闪镀一金层。
22．如权利要求12所述的制造方法，其特征在于，该第一银层以环型电镀方式刮镀在该芯片座外的引线框架表面，且该第二银层以环型电镀方式点镀，仅覆盖在该焊接区中该芯片座外的第一银层表面。
23．如权利要求12所述的制造方法，其特征在于，该第一银层全面性刮镀在该引线框架表面，且该第二银层选择性点镀覆盖在该焊接区中该第一银层表面。
24．如权利要求23所述的制造方法，其特征在于，该引线框架材质包括铜合金。
25．一种引线框架为一集成电路提供电连接，其特征在于，该引线框架包括一芯片座及多个引线，其中该芯片座用来承载该集成电路，这些引线用来与该集成电路连接；且该引线框架包括一封装区，而该封装区具有一焊接区，该引线框架包括：
一底材；
一在该底材表面的第一银层；以及
一在该第一银层表面的钯层。
26．如权利要求25所述的引线框架，其特征在于，该底材材质包括铜合金。
27．如权利要求25所述的引线框架，其特征在于，该底材材质包括镍铁合金。
28．如权利要求25所述的引线框架，其特征在于，该底材与该第一银层间还包括一镍层。
29．如权利要求25所述的引线框架，其特征在于，该底材与该第一银层间还包括一铜层。
30．如权利要求25所述的引线框架，其特征在于，该底材与该第一银层间还包括一铜层，及一镍层在该铜层表面。
31．如权利要求25所述的引线框架，其特征在于，该第一银层及该钯层之间包括一镍钯层。
32．如权利要求25所述的引线框架，其特征在于，该第一银层仅在该焊接区与该封装区外的底材表面，该焊接区内的第一银层还包括一第二银层在其表面，且该钯层仅在该封装区外的第一银层表面。
33．如权利要求32所述的引线框架，其特征在于，在该钯层与该第一银层之间有一钯镍层在该封装区外的第一银层表面。
34．如权利要求32所述的引线框架，其特征在于，在该钯层表面有一金层在该封装区外的钯层表面。
35．如权利要求32所述的引线框架，其特征在于，在该钯层与该第一银层之间有一钯镍层在该封装区外第一银层表面，且在该钯层表面有一金层在该封装区外的钯层表面。
36．如权利要求25所述的引线框架，其特征在于，该第一银层仅在该焊接区中该芯片座以外的区域，以及封装区外的底材表面，该焊接区内的第一银层还包括一第二银层在其表面，且该钯层仅在该封装区外的第一银层表面。
37．如权利要求36所述的引线框架，其特征在于，在该钯层与该第一银层之间有一钯镍层在该封装区外的第一银层表面。
38．如权利要求36所述的引线框架，其特征在于，在该钯层表面有一金层在该封装区外的钯层表面。
39．如权利要求36所述的引线框架，其特征在于，在该钯层与该第一银层之间有一钯镍层在该封装区外的第一银层表面，且在该钯层表面有一金层在该封装区外的钯层表面。
40．如权利要求25所述的引线框架，其特征在于，该第一银层仅在该焊接区与该封装区外的该底材表面，而该钯层则覆盖该底材整个表面。
41．如权利要求25所述的引线框架，其特征在于，该第一银层仅在该焊接区的底材表面，而该钯层则覆盖该底材整个表面。
42．根据权利要求25所述的引线框架，其特征在于，在底材上具有一铜层，在铜层上具有一镍层，所述第一银层在焊接区的所述镍层表面，所述钯层还处于未被所述第一银层所覆盖的镍层表面。
43．根据权利要求25所述的引线框架，其特征在于，在底材上具有一铜层，在铜层上具有一镍层，所述第一银层在焊接区与封装区外的所述镍层表面，所述钯层还处于未被所述第一银层所覆盖的镍层表面，在导线连接区的第一银层表面具有一第二银层，所述钯层处于封装区外的第一银层表面，其中该引线框架还包括一在封装区外的该钯层表面的金层。
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KR101646094B1 (ko) * 2011-12-12 2016-08-05 해성디에스 주식회사 리드 프레임 및 이를 이용하여 제조된 반도체 패키지
CN111199940B (zh) * 2018-11-16 2022-03-25 泰州友润电子科技股份有限公司 一种用于引线框架的涂覆料涂覆方法
CN112376094A (zh) * 2020-11-06 2021-02-19 东莞市川富电子有限公司 充放电模组块连接端子的功能电镀镀层方法

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