TW577127B - Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment and methods of fabricating same - Google Patents

Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment and methods of fabricating same Download PDF

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TW577127B
TW577127B TW091104382A TW91104382A TW577127B TW 577127 B TW577127 B TW 577127B TW 091104382 A TW091104382 A TW 091104382A TW 91104382 A TW91104382 A TW 91104382A TW 577127 B TW577127 B TW 577127B
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Richard Peter Smith
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

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Description

577127 A7 B7 五、發明説明(1 ) 相關申請t 本申請案與2000年12月1日提出之美國臨時申請案第 60/250,755號有關,並為申稱其優先權,其標題為 MAlGaN/GaN HEMT with Improved Gate Barrier Layer and Low Access Resistance" ’茲以引用之方式併入本文。 政府參與磬明 本發明至少部分係在Office of Naval Research Contract第 N00014-99-C-0657號下發展有關。故政府對本發明具一定 權利。 發明領域 本發明與高度電子遷移率電晶體(HEMT)有關,尤其與氮 化鋁鎵(AlGaN)/氮化鎵(GaN)HEMTs有關。 發明背景
AlGaN/GaN HEMT元件係在半導體領域中眾所週知。 美國專利第5, 192,987與5,296,395號即描述AlGaN/GaN HEMT結構及其製造方法。經改良之HEMT結構揭示於一 般指定之美國專利申請案第09/096,967號,於1998年6月 12 曰提出,標題為"NITRIDE BASED TRANSISTORS ON SEMI-INSULATING SILICON CARBIDE SUBSTRATES", 茲以引用之方式併入本文。 典型的AlGaN/GaN HEMT結構110示如圖1。在基板112上 之緩衝層1 13上形成GaN通道層1 14。在GaN通道層1 14上形 成AlGaN障壁層1 16。源極丨18與汲極1 20構成穿越AlGaN層 1 1 6表面至位於GaN通道層1 14頂之電子層之歐姆接點。在 -4- 本紙張尺度適用中國®家標準(CNS) A4規格(210X297公釐)
装 訂
線 577127 A7 ___B7 五、發明説明(2 ) 一習知AlGaN/GaN HEMT結構中,閘極122即構成對八丨匕以 障璧層[1 6表面之非歐姆接觸。 由於晶格中存有鋁,故AlGaN之能帶隙較GaN寬。因此, GaN通道層114與八10-障壁層116間介面形成異質結構。圖 2係一能量圖,顯示元件中沿圖夏A_A,段之部分能階。如圖 2所示,AlGaN障壁層Π6中之傳導與價帶^與&因極化效 應而杻曲。結果在GaN通道層1 14與AlGaN障壁層Π6間之異 質接面導致二維電子氣(2DEG)片電荷區115,同時因傳導帶 之外型導致AlGaN障壁層116之遷移載體空乏。如圖2所示 ,傳導帶Ec係浸於費米能階(Ef)區之下,GaN通道層與 AlGaN障壁層116極時相鄰區域中。 2DEG片電荷區115中電子之載體遷移率較高。此區之 傳導率受施加於閘極122之電壓調變。當施加逆向偏壓時 ,片電荷區115之空穴中的傳導帶昇至費米能階之上,部 分片電荷區115經載體空乏,藉此避免電流自源極丨丨8流 至汲極1 2 0。 如圖1所示,AlGaN/GaN HEM丁一般均製有共面金屬接點 。亦即對源極1 1 8與汲極120之歐姆接點均與閘極122在同一 石石日日層上(亦即八1(;}心層丨丨6)。所具歐姆接點係為提供低電 阻非整流性接點於材料之用,而閘極接點係為抑制大逆 向偏壓蚪之電流之非歐姆接點,所有在相同磊晶層上形成 之接點,可造成特性間之妥協。換言之,在習知 AlGaN/GaN HEMT元件中,在選擇α1&ν障壁層之摻雜 /、’ ’且成77日守,在兀件設計令面臨一方面欲最佳化源極與汲 本紙狀度適用中_家標準((:卿/\4馳2似297公發) 577127 五、發明説明(4 罩區段並具與汲極相鄰但不相接之第二側壁。一在帽幕區 段上之非歐姆接點,係用以提供閑極接點。問極接點具第 一側壁1大抵上與帽罩區段之第―側壁對齊。閘極接點 僅延伸於帽罩區段之第一惻壁與第二側壁間一段距離。在 特殊具體實施例中,帽罩區段係_ GaN帽罩區段。 在本發明之另一具體實施例中,非歐姆接點延伸於,但 不通過GaN帽罩區段之第一側壁。㈣帽罩區段厚度自约1〇 至約60A。GaN帽罩區段包含未摻雜GaN。 在本發明之一特殊具體實施例中,源極與汲極間距自約2 至約4 μπι。此外,GaN帽罩區段之第一側壁儘可能接近源 極較佳,例如自約〇至約2 μπι。GaN帽罩區段之第二側壁距 離汲極自約0.5至約1 μιτι。 在本發明之一附加具體實施例中,A1GaN障壁層包括約 15%至約40%之鋁。八1(^>^障壁層亦摻雜矽,其摻雜濃度高 達約4xl〇18Cm_3或更高,俾具高達約5xl〇12c〆之片濃度較佳, 其厚度自約1 5至約4 0 n m,約2 5 n m較佳。 在本發明之另一具體實施例中,GaN通道層係位於基板 上。基板可為碳化矽、藍寶石等。在一特殊具體實施例中 ’基板係4H碳化矽或6H碳化矽。此外,GaN緩衝層係配置 於GaN通道層與基板間。 在本發明之另一具體實施例中,閘極係一 T型閘極。 在本發明之方法具體實施例中,提供製造高度電子遷移 率電晶體(ΗEMT)之方法,其包括:在基板上形成第一氮化 鎵(GaN);在第一 GaN層上形成氱化鋁鎵(AIGaN)。將第二 本紙張足度適用中國國家標準(CMS) A4規格(im) X 297公绛) 577127 五、發明説明(5 ) =㈣⑸W層上,提供AIGaN層上之GaN區段, 層。形成對AK}a_之卜歐姆接點,其 與GaN區段相鄰但不相接 〜 *肖以做為源極:形成對AIGaN層 之弟-歐姆接點,其與GaN區段相鄰但不相接,並與第一 歐姆接點相對,使得GaN區段配置於第一歐姆接點與第二 歐姆接點間,用以做為沒極。在GaN區段上圖樣化一非歐 姆接點,用以做為閘極接點。該閘極接點具大抵上與源極 接點及閘極接點相鄰之G a N區段之第一侧壁對齊之第一側 壁。閘極接點並僅延伸一段距離於與沒極接點相鄰之_ 區段之第一側壁及第二歐姆接點間。 在本發明之另一具體實施例中,提供第二層以及非 歐姆接點之圖樣化,其係藉由在層上形成第二_層 j在GaN層上形成非歐姆接點,以及圖樣化非歐姆接點及 第二GaN層為之,俾提供GaN區段.及閘極接點。此類圖樣化 更可藉由形成覆蓋部分非歐姆接點及第二GaN層之罩層, 俾界定與源極接點相鄰之非歐姆接點及GaN區段側壁以及 與汲極接點相鄰之GaN區段側壁;並蝕刻非歐姆接點及第 二GaN層’露出部分a丨(^Ν層。 圖式簡述 圖1係習知AlGaN/GaN HEMT元件橫剖圖; 圖2係闡釋存在於習知AlGaN/GaN HEMT元件中的能帶略 圖; 圖3係依本發明具體實施例之AlGaN/GaN HEMT元件橫剖 圖; -8 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 577127
A7 ------------ B7 五、發明説明1 η-- 本發明《具體實施%包含諸如圖3所示元件以及制圖3所 示帽罩區段與閘極接點,具複數個單位胞體之元件。 一種依本發明製造A1GaN/GaN ΗΕΜΤ之方法,係利用圖 从至40所示㈣帽罩區段為之,並可視需要包括在基板12 上形成緩衝層13。一 GaN通道層14係形成於緩衝層13上, 而一 AlGaN障壁層16則係形成於通道層上。一薄帽罩層 、係幵v成於J1 早壁層16上。這些層可藉由M〇c / 或任何其它熟悉此技藝者週知之方法形成。
GaN帽罩層30,經圖樣化提供對閘極之帽罩區段3〇。 例如圖4A所不,可在GaN帽罩層3〇,上形成蝕刻罩扣,並利 用習知蝕刻製程於障壁層16,移除部分GaN帽罩層3〇,,留 下如圖4B所示GaN帽罩區段30。但諸如選擇性磊晶長成等 其它技術亦適用之。 如圖4C所示’利用習知技術在障壁層16之暴露部分形成 源極18與沒極20。閘極22係形成於GaN區段30上。在圖4A 至4C所不具體實施例中,利用習知微影技術及罩對齊工具 使問極接點之源極側之側壁與GaN帽罩區段3〇之源極側之 側壁對齊。在圖4A至4C所示具體實施例中,閘極22並非與 GaN帽罩區段3〇之源極側之側壁自行對齊。因此閘極22可 月έ不會與源極側或及極側對齊,分別示如圖5 a與5 B。雖然 輕微失準可能不致對元件操作有負面影響,但嚴重失準可 能即對元件不利。故閘極22之源極側之側壁與GaN帽罩區 段30之源極側之側壁對齊較佳,示如圖4C,但閘極22之源 極側之惻壁可能僅大抵上與GaN帽罩區段30之源極側之惻 本紙張玟度適川中國國家標準(CNS) Λ4規格(210 X 297公婕) 577127 A7 B7 五、發明説明(12 ) 噎對與、,示如圖5 A與)B,而仍係出自本發明之教導下之優 點。故如本文所述,大抵上對其係指對齊範圍可包含失準 狀況。 另一種依本發明之具體實施例製造元件之方法示如圖6 a 至6C。在這些具體貫施例中,GaN帽罩區段3 〇之源極惻之 側壁係自行對齊閘極22之源極側之側壁。 參閱圖6A ’可視需要在基板丨2上形成緩衝層13。GaN通 道層14係形成於GaN緩衝層1 3或基板12上,而AlGaN障壁層 16係形成於GaN通道層14上。薄GaN帽罩層3 〇,係形成於 AlGaN障壁層16上,如上述。閘極金屬22,係形成於〇.帽 罩層30’上’閘極金屬22,並經部分圖樣化,俾提供閘極22之 汲極側之側壁,以及提供通過閘極22之源極側之側壁部分 之閘極金屬22’。蝕刻罩44係沉積於GaN帽罩層30,上,其部 分與閘極金屬22 ’重疊,俾界定閘極22之源極側之側壁與 GaN帽罩層3 0以及GaN帽罩層3 0之沒極側之側壁。 如圖6B所示,GaN帽罩層30,之暴露部分經蝕除,留下 GaN帽罩層3 0之一側壁與閘極22之側壁自行對齊,並露出 部分AlGaN障壁層16。而後移除罩44。如圖6C所示,接著 在A1GaN卩早壁層16之暴露部分形成源極1 8與;;及極2 〇,並以 習知方式處理殘留元件部分。 雖然已參考操作之特殊程序描述本發明之具體實施例, 熟悉此技藝者應可瞭解,可將程序内某些操作重新排序, 而仍保持本發明教導之優點。此外,某些操作可與單一操 作合併或分成多種操作’而仍保持本發明教導之優點。故 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(21.0X 297公釐)
裝 訂

Claims (1)

  1. 577127 厂 第09U04382號專利申請案 ! 8 中文申請專利範圍替換本(92年11月) g _m_;_ 六、申請專利範園 1. 一種高度電子遷移率電晶體(HEMT),其包括: 一氮化錄(GaN)通道層; 一位於通道層上之氮化鋁鎵(AlGaN)障壁層; 一位於障壁層上之第一歐姆接點,用以提供一源極; 一位於障壁層上,與源極相間之第二歐姆接點,用以 提供一汲極; 一以GaN為基之帽罩區段,其位於障壁層上,源極與 汲極間,該以GaN為基之帽罩區段之鋁濃度低於障壁層 ,並具與源極相鄰但不相接之第一側壁;以及 一在以GaN為基之帽罩區段上之非歐姆接點,用以提 供閘極接點,該閘極接點具第一側壁,其大抵上與以 GaN為基之帽罩區段之第一側壁對齊,以及閘極接點僅 延伸於以GaN為基之帽罩區段之第一側壁與第二側壁間 一段距離。 2. 如申請專利範圍第1項之HEMT,其中以GaN為基之帽罩 區段具與汲極相鄰但不相接之第二側壁。 3. 如申請專利範圍第1項之HEMT,其中以GaN為基之帽罩 區段包括一 GaN帽罩區段。 4. 如申請專利範圍第3項之HEMT,其中非歐姆接點延伸於 ,但不通過GaN帽罩區段之第一側壁。 5. 如申請專利範圍第3項之HEMT,其中GaN帽罩區段厚度 自約10至約60A。 6. 如申請專利範圍第5項之HEMT,其中GaN帽罩區段包含 未摻雜GaN。 O:\76\76968-921118.<J〇C 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 577127 Λ 8 Β8 C8 08 六、申請專利範固 7. 如申請專利範圍第2項之HEMT,其中源極與汲極間距自 約2至約4 μπι。 8. 如申請專利範圍第3項之ΗΕΜΤ,其中GaN帽罩區段之第 一側壁距離源極小約2 μπι。 9. 如申請專利範圍第8項之ΗΕΜΤ,其中GaN帽罩區段之第 一側壁距離源極自約0.3至約1 · 5 μηι。 10. 如申請專利範圍第2項之ΗΕΜΤ,其中GaN帽罩區段之第 二側壁距離没極自約0.5至約1 μηι。 11. 如申請專利範圍第3項之ΗΕΜΤ,其中AlGaN障壁層包括 約15%至約60%之鋁。 12. 如申請專利範圍第11項之ΗΕΜΤ,其中AlGaN障壁層摻雜 有矽,俾具高達約5xlOl2ci2之片濃度。 13. 如申請專利範圍第11項之ΗΕΜΤ,其中AlGaN障壁層厚度 自約1 5至約40 nm。 14. 如申請專利範圍第13項之ΗΕΜΤ,其中AlGaN障壁層厚度 約 25 nm 〇 15. 如申請專利範圍第3項之ΗΕΜΤ,更包括一基板,以及其 中GaN通道層係位於基板上。 16. 如申請專利範圍第15項之ΗΕΜΤ,其中基板含碳化矽。 17. 如申請專利範圍第15項之ΗΕΜΤ,其中基板含藍寶石。 18. 如申請專利範圍第15項之ΗΕΜΤ,其中基板包含至少4Η 碳化矽與6Η碳化矽之一。 19. 如申請專利範圍第15項之ΗΕΜΤ,更包括一配置於GaN通 道層與基板間之GaN緩衝層。 O:\76\76968-921118.doc - 2 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 577127 Λ 8 Β8 C8 08 六、申請專利範圍 20. 如申請專利範圍第1項之HEMT,其中閘極包括一 T型閘 極。 21. —種製造高度電子遷移率電晶體(HEMT)之方法,其包 括: 在基板上形成第一氮化鎵(GaN); 在第一 GaN層上形成氮化鋁鎵(A丨GaN); 在AlGaN層上形成以GaN為基之區段,該以GaN為基之 區碌之鋁濃度低於AlGaN層; 形成對AlGaN層之第一歐姆接點,其與GaN區段相鄰 但不相接,用以做為源極; 形成對AlGaN層之第二歐姆接點,其與GaN區段相鄰 但不相接,並與第一歐姆接點相對,使得GaN區段配置 於第一歐姆接點與第二歐姆接點間,用以做為汲極;以 及 在GaN區段上形成一非歐姆接點,用以做為閘極接點 ,該閘極接點具大抵上與源極接點及閘極接點相鄰之 GaN區段之第一側壁對齊之第一側壁,並僅延伸一段距 離於第一側壁及第二歐姆接點間。 22. 如申請專利範圍第2 1項之方法,其中非歐姆接點僅延伸 一段距離於與汲極接點相鄰之GaN區段之第一側壁及第 二側壁間。 23. 如申請專利範圍第22項之方法,其中形成以GaN為基之 區段包括形成在AlGaN層上之GaN區段。 24. 如申請專利範圍第23項之方法,其中形成GaN區段以及 O:\76\76968-921118.doc - 3 - 本紙張尺度適用中國國家標準(CNS) A4規格(2i0 X 297公釐)
    577127 Λ8 B<S C8 D8 六、申請專利範園 形成非歐姆接點包括: 在AlGaN層上形成第二GaN層; 在GaN層上形成非歐姆接點; 圖樣化非歐姆接點及第二GaN層,俾提供GaN區段及 閘極接點。 25·如申請專利範圍第24項之方法,其中圖樣化非歐姆接點 及第二GaN層包括·· 在非歐姆接點及第二GaN層上形成罩層,使罩層覆蓋 部分非歐姆接點及第二G a N層,俾界定與源極相鄰之非 歐姆接點及第二GaN區段側壁以及與汲極接點相鄰之 GaN區段側壁; 蚀刻非歐姆接點及第二GaN層,露出部分AlGaN層。 26. 如申請專利範圍第23項之方法,其中所形成之區段 厚度自約10至約60A。 27. 如_請專利範圍㈣項之方法,其中⑽區段包含未捧 雜 GaN。 28.如申請專利範圍第23項之方法,其t形成第—歐姆接點 與形成第二歐姆接點包括形成間距自約2至約4叫之第 一歐姆接點與第二歐姆接點。 29·如申請專利範圍第23項之方法,甘占%…丄 也 乃忠其中所形成之第一歐姆 楱點與GaN區段間距低於約2 μηι。 3〇·如申請專利範圍第29項之方法,甘a <万决,其中所形成之第一歐姆 接點與GaN區段間距自約〇·3至約1 5 。 3 1 ·如申清專利範圍第2 3項之方半 甘 万/务 其中非歐姆接點經圖樣 O:\76\76968-921118.doc -4
    577127 Λ8 B8 C8 D8 六、申請專利範園 化使得非歐姆區接點側壁與GaN區段之第二側壁間距自 約0.5至約1 μηι。 3 2.如申請專利範圍第23項之方法,其中形成AlGaN層包括 形成含約15%至約60%鋁之AlGaN層。 3 3.如申請專利範圍第32項之方法,其中形成AlGaN層包括 形成摻雜有高達約5xl012W2片濃度之矽之AlGaN層。
    裝 34. 如申請專利範圍第32項之方法,其中形成AlGaN層更包 括形成厚度自約15至約40 nm之AlGaN層。 35. 如申請專利範圍第34項之方法,其中形成AlGaN層更包 括形成厚度約25 nm之AlGaN層。 36. 如申請專利範圍第23項之方法,其中基板含碳化矽。 37. 如申請專利範圍第23項之方法,其中基板含藍寶石。 3 8.如申請專利範圍第23項之方法,其中基板包含至少4H碳 化矽與6H碳化矽之一。 39. 如申請專利範圍第23項之方法,更包括性成配置於第一 GaN層與基板間之第三GaN層。
    40. 如申請專利範圍第23項之方法,更包括在非歐姆接點上 形成金屬化層,做為T型閘極。 41. 一種高度電子遷移率電晶體(HEMT),其包括: 一氮化鎵(GaN)通道層; 一氮化鋁鎵(AlGaN)障壁層; 位於AlGaN障壁層上之歐姆接點,用以提供源極於汲 極; 配置於源極與汲極間之非歐姆閘極接點;以及 O:\76\76968-921118.doc - 5 本紙張尺度適用_國國家標準(CNS) A4規格(210 X 297公釐) 577127 A B c D 々、申請專利範圍 用以降低歐姆接點電阻並增加閘極之限制電壓之裝置 ,可併同非歐姆閘極接點與AlGaN障壁層操作,俾與不 具用以降低歐姆接點電阻並增加閘極之限制電壓裝置之 元件比較之。 42. 如申請專利範圍第41項之HEMT,其中用以降低歐姆接 點電阻並增加閘極之限制電壓之裝置包括位於閘極接點 與AlGaN障壁層間之GaN區段,該GaN區段具與源極接點 相鄰之GaN區段的一部份上之閘極接點,以及GaN區段 延伸通過閘極接點朝向汲極接點。 43. 如申請專利範圍第42項之HEMT,其中閘極接點延伸但不 通過GaN區段之側壁,與源極相鄰但相間。 44. 如申請專利範圍第42項之HEMT,其中GaN區段延伸距離 自約0.5至約1 μιη。 O:\76\76968-921118.doc - 6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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US6548333B2 (en) 2003-04-15
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US6777278B2 (en) 2004-08-17
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