TW557522B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW557522B TW557522B TW091112902A TW91112902A TW557522B TW 557522 B TW557522 B TW 557522B TW 091112902 A TW091112902 A TW 091112902A TW 91112902 A TW91112902 A TW 91112902A TW 557522 B TW557522 B TW 557522B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- substrate
- wiring pattern
- wiring
- thin film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 239000000758 substrate Substances 0.000 claims abstract description 130
- 229920005989 resin Polymers 0.000 claims abstract description 37
- 239000011347 resin Substances 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 120
- 229910052751 metal Inorganic materials 0.000 claims description 63
- 239000002184 metal Substances 0.000 claims description 63
- 239000010409 thin film Substances 0.000 claims description 56
- 230000003014 reinforcing effect Effects 0.000 claims description 45
- 229920001225 polyester resin Polymers 0.000 claims description 3
- 239000004645 polyester resin Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000009719 polyimide resin Substances 0.000 claims description 3
- 230000005855 radiation Effects 0.000 claims 1
- 230000002787 reinforcement Effects 0.000 claims 1
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 20
- 238000007789 sealing Methods 0.000 description 11
- 230000008646 thermal stress Effects 0.000 description 8
- 230000037303 wrinkles Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000008602 contraction Effects 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000013585 weight reducing agent Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
557522 A7 -------------- B7 五、發明説明(i ) —- 發明的技術領域 本發明係係和例如行動電話、移動式資訊終端機、及液 晶顯示用面板等電子機器所使用之半導體裝置相關。 習知技術 近年來’如订動電話、移動式資訊終端機、液晶顯示用 面板、及筆記型電腦等電子機器之小型化、薄化、及輕量 化的發展十分快速。因此,以裝配於這些機器上之半導體 裝置為首,所有構件也同樣追求小型化、輕量化、高機能 化、及高密度化。 在刖述之狀況下,現在之半導體裝置,以使用薄膜狀基 板來實現輕量化,並以在前述薄膜狀基板上安裝半導體元 件追求高密度化來實現形體之小型化及薄化。此種安裝方 式被稱為 COF(Chip on FPC)。 利用圖6至圖9來說明前述C0F方式之習知半導體裝置。 如圖6所示,此習知之半導體裝置係由半導體元件丨8及配 線基板16所構成。半導體元件18上會形成複數電極。此電 極係由半導體元件1 8上形成之銘墊(aluminium pad) 12、及 在該鋁墊12上形成之凸塊(bump)電極(Au凸塊)13所構成。 如圖7所示,配線基板16係由形成配線圖案15之薄膜基板14 所構成。此配線圖案15會形成於和Au凸塊13相對應之位置 上。且Au凸塊13及配線圖案15會互相連接。 利用圖8來說明前述半導體裝置之製造方法。 首先,先針對配線基板16調整半導體元件18之位置。亦 即,調整Au凸塊13之位置,使其和相對應之配線圖案15的 -5- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 557522 A7 ________B7_ 五、發明説明(2 ) 特定位置一致。接著,使用接合工具19,以熱壓接合法將 Αιι凸塊13及配線圖案15連接(接合)在一起。然後,再以樹 脂將半導體元件18及配線基板16密封起來。 如上面所述,半導體裝置之Au凸塊13及配線圖案15的連 接上,目前係以熱壓接合法為主流。因此,熱壓接合時, 必須對配線基板16之薄膜基板14及配線圖案15施加熱應力 。利用此熱應力,使薄膜基板14及配線圖案1 5分別依據膨 脹係數進行伸縮(實際上為加熱伸長)。此時,因薄膜基板14 之線膨脹係數大於配線圖案15之線膨脹係數,故薄膜基板 14會有較大的伸長。 而實際上,因配線圖案15係在薄膜基板14上形成,故配 線圖案15會隨著薄膜基板14之伸長程度(被拉伸)而有較大之 伸長。相反的,薄膜基板14亦會隨著配線圖案1 5之伸長程 度而縮小伸長。換言之,配線基板16之尺寸安定性並非十 分良好,而使配線圖案15產生位置偏離,而無法和Au凸塊 13之位置一致。因此,會產生Au凸塊13及配線圖案15連接 不良的問題。 又,對應因熱壓接合時所施加之溫度變化而產生製造誤 差之配線基板16的完成尺寸,實施位置偏離補正,進行半 導體元件1 8及配線基板16之連接。然而,此時因需針對各 配線基板16改變溫度,而降低生產效率。 又,如圖7所示,設置於配線基板16上之半導體元件18(參 照圖6)的半導體元件設置位置17(以虛線圍繞部份)中,除了 連接Au凸塊13(參照圖6)之部位以外,並未形成配線圖案。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) -6- 557522 A7
五、發明説明(3 亦即,配線圖案15之内側,並未形成配線圖案,薄膜基板 14因而外露。因此,施加熱應力時,在配線圖案15之内侧 ’因薄膜基板14之伸長會大於形成配線圖案1 5之部份,故 會產生皺紋。產生此種皺紋之半導體裝置,會有外觀檢查 上不良之問題。同時,此皺紋中,可能會蓄含水份等,因 此水份等會使Au凸塊13附近腐蝕,而產生半導體元件18及 配線基板16連接不良之問題。 因此,曰本特開2000-286309號公報(2000年1〇月13曰公開 )發表’防止因熱之伸縮而變形(反翹)的配線基板。此配線 基板16之構成上,如圖9所示,在薄膜基板14上以折線方式 形成配線圖案1 5(含有向第1方向及第2方向延伸之部份)。此 折線式配線圖案1 5利用複數方向來承受薄膜基板之伸長 ’而可減輕因薄膜基板14之伸長而產生的反麵。又,前述 配線基板16中,以突出於元件孔(device hole)21之内導線 (inner lead)(配線圖案15之一部份)22連接半導體元件。因此 ’產生則述皺紋之區域為元件孔21之部份,故不會產生敏 紋造成之連接不良。 然而’曰本特開2000-286309號公報之配線基板中,連接 半導體元件部份之周邊,並未形成折線式配線圖案。因此 ,連接半導體元件部份之周邊,配線圖案15無法以複數方 向來承受熱應力造成之薄膜基板14的伸長。所以,會產生 配線基板16(薄膜基板14)之伸長,而相對於半導體元件位置 之内導線22就會產生位置偏離。此位置偏離會導致無法將 半導體元件連接於内導線22上,而產生連接不良(導電不良)
裝 訂
557522 A7 --------_B7__ 五、發明説明(4 ) " "-- 的問題。 發明之摘要 本發明之目的,係利用提高配線基板之尺寸安定性來防 止半導體元件及配線基板之配線圖案的位置偏離,提供可 確實連接半導體元件及配線圖案之半導體裝置。 為了達成前述目的,本發明之半導體裝置係由半導體元 件、及在薄膜基板上形成配線圖案之配線基板所構成,且 為半導體元件和配線圖案相連接,並以樹脂密封半導體元 件及配線基板之半導體裝置,其特徵則為,在前述薄膜基 板之至少一側未形成配線圖案之區域,以線膨脹係數小於 薄膜基板之材料形成補強膜。 利用前述構成,可以在薄膜基板上形成補強膜,薄膜基 板之伸長會受到抑制,而為補強膜之較小伸長。亦即,補 強膜會抑制薄膜基板之伸長。利用此方式,可以提升配線 基板之尺寸安定性。所以,可以減少半導體元件及配線圖 案之位置偏離,可提供半導體元件及配線圖案可確實連接 之半導體裝置。又,如前面所述,因為形成補強膜,而使 薄膜基板不易伸長,亦可防止薄膜基板上產生皺紋。 本發明之其他目的、特徵、及優點由下面記載可知。又 ’本發明之利益由下述參照圖面之說明亦可了解。 圖式之簡單說明 圖1係本發明一實施形態半導體裝置之主要部位的剖面圖。 圖2係前述半導體裝置之配線基板的平面圖。 圖3(a)〜(c)係本發明另一實施形態半導體裝置之配線基板 本紙張尺度it财國國家標準(CNS) A4規格(210 X 297公爱) 557522
的平面圖。 圖4係本發明另一實施形態半導體裝置之配線基板的平面 圖。 圖5係本發明另一實施形態半導體裝置之配線基板(帶載體 (tape carrier))的平面圖。 圖6係習知半導體裝置之主要部位的剖面圖。 圖7係習知半導體裝置之配線基板的平面圖。 圖8係說明習知半導體裝置之製造方法的剖面圖。 圖9係習知配線基板的平面圖。 發明之實施形態 [實施形態1] 利用圖1至圖5,針對本發明一實施形態相關半導體裝置 說明如下。又’本實施形態所採用之各步驟條件等,和習 知之半導體積體電路(半導體元件)製造方法(安裝步驟)所使 用之條件相同,除了特殊情形以外,省略其詳細說明。 本貫施形態相關半導體裝置如圖1所示,係由半導體元件 1及配線基板6所構成。半導體元件1上形成複數之輸出入用 電極。此電極係由在半導體元件1上形成之墊2、及在該墊2 上形成之凸塊電極(Au凸塊)3所構成。配線基板6之構成如 圖2所示,係由在薄膜基板4上形成之金屬膜(補強膜)8及配 線圖案5所構成。此配線圖案5形成於和Au凸塊3相對應之位 置上。又,配線圖案5則是由連接半導體元件1之内導線、 液晶顯示用面板等電子機器之連接部的外導線、及連接内 導線及外導線之中間導線所構成。且Au凸塊3和配線圖案 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公袭:) 557522 A7
557522 A7 B7 五、發明説明(7 凸塊3及配線圖案(内導線)5。亦即,實施JLB。 ILB後,以如環氧樹脂或矽樹脂等材料所構成之熱硬化性 樹脂(樹脂)密封半導體元件1及配線基板6。此樹脂密封則係 利用如噴嘴對半導體元件1周圍之1邊至3邊(4邊密封因無排 氣口而不可能)塗敷(滴下)前述樹脂。樹脂會流入半導體元 件1及配線基板6之間,利用回流(refjow)方式等進行加熱, 使樹脂硬化。前述樹脂亦可使用紫外線硬化性樹脂。此時 ’照射紫外線使樹脂硬化。 如前面所述,利用本實施形態之半導體裝置,如圖2所示 ’在半導體元件設置位置7未形成配線圖案之區域,會形成 金屬膜8 ^此時,薄膜基板4係以聚醯亞胺樹脂或聚酯樹脂 等材料形成,金屬模8則係以銅等之金屬材料形成。利用此 等材料之特性(聚醯亞胺樹脂或聚酯樹脂等材料的線膨脹係 數大於金屬屬材料),薄膜基板4之線膨脹係數的值會大於 金屬膜8之線膨脹係數的值。所以,對薄膜基板4及金屬膜8 施加同程度之熱應力時,熱膨脹係數較大之薄膜基板4側的 伸縮會大於金屬膜8(此處,只有加熱時之伸長)。 然而,因金屬膜8黏著於薄膜基板4上,薄膜基板4之伸長 ’會因為金屬膜8之較小伸長而受到抑制。利用此方式,金 屬膜8可以抑制薄膜基板4之伸長,可提高配線基板6之尺寸 安定性。又,亦可減少半導體元件1及配線基板6之位置偏 離,亦即,減少Au凸塊3及配線圖案(内導線)5之位置偏離 ,而降低Au凸塊3及配線圖案(内導線)5之連接不良。因而 有良好之ILB。 -11 - 本紙張尺度適用巾g s家標準(CNS) A4規格㈣χ挪公爱)
裝 訂
557522 A7 B7 五、發明説明(8 ) 以具體實例而言,前述薄膜基板4具有20 ρριη/Κ程度之熱 膨脹係數。相對於此,形成金屬膜8之薄膜基板4之線膨脹 係數則只有較小之15 ppm/K程度。因此可知,實際加熱時 ,薄膜基板4不易伸長。亦即,配線基板6之尺寸安定性提 高了。 又,未形成前述金屬膜之薄膜基板4的區域上,因為薄膜 基板4及配線圖案5之伸長差異,而可能產生皺紋。然而, 因為形成此金屬膜8,而使薄膜基板4不易伸長,故亦可防 止薄膜基板4上之敏紋。 又,前述金屬膜8可以阻隔透過薄膜基板4而照射於半導 體元件1表面之外部光線(α射線)。所以,亦可防止因α線 照射而產生之半導體裝置的錯誤動作。 又,前述配線圖案5及金屬膜8最好以相同材料形成。如 此,配線圖案5及金屬膜8較容易同時形成,而提高生產效 率。又,無需另設新製造步驟,可以低成本形成金屬膜8。 此外,前述配線圖案5及金屬膜8最好以同一製作方法(同 一步驟)形成。如此,配線圖案5及金屬膜8較容易同時形成 ,而提高生產效率。又,無需另設新製造步驟,可以低成 本形成金屬膜8。 以相同厚度形成前述金屬膜8及配線圖案5時,較容易同 時形成,而且可進一步提高生產效率。又,”相同厚度,,係 扣金屬膜8及配線圖案5具有實質相同之厚度。因無需另設 新製造步驟,可以更低成本形成金屬膜8。 前述金屬膜8之厚度,最好小於配線圖案5之厚度。又, -12- 本紙張尺度適财目目豕標準(CNS) A4規格(210X297公爱)
裝 訂
557522
配線圖案5之實質厚度和金屬膜8相同亦可。此時,將半導 體元件1連接至配線基板6時,半導體元件丨可能接觸到金屬 膜8。然而,若在半導體元件〗之表面形成保護膜,則即使 半導體元件1及金屬膜8輕輕接觸,亦不會破壞半導體元件i 。又,因為金屬膜8之厚度小於配線圖案5之厚度,半導體 元件1及配線基板6之間只會產生Au凸塊3之厚度的空間。樹 脂密封時,樹脂會利用此空間流入半導體元件丨及配線基板 6之間。故容易貫施樹脂密封。 又’金屬膜8厚度為配線圖案5厚度之1/3〜2/3時更好。金 屬膜8厚度為配線圖案5厚度之1/3以下時,因厚度太薄而不 易製造,而且,製造上也需要較大的製造成本。又,金屬 膜8厚度超過2/3(接近或等於配線圖案5厚度),將半導體元 件1連接於配線基板6時,半導體元件丨可能接觸到金屬膜8 。半導體元件1接觸到金屬膜8時,半導體元件丨可能因短路 而損壞。亦即,前述範圍内之厚度,金屬膜8之製造較為容 易,且可以降低半導體元件1因接觸金屬膜而損壞之可能性 。又,半導體元件1及配線基板6之間因有薄薄的金屬層8而 具有較大的空間。實施樹脂密封時,樹脂可以利用此空間 而較易流入半導體元件1及配線基板6之間。所以,樹脂密 封亦會更為容易。 此外,金屬膜8最好為和配線圖案5分開形成,且未實施 電氣連接。前述金屬膜8的目的,就是要抑制薄膜基板4因 熱應力而伸長,故構成上必須以提升尺寸安定性為目的。 所以,金屬膜8及配線圖案5不需要電氣連接。 -13 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 557522 A7 ________ B7 五、發明説明(1〇 ) 其次,亦可以圖3(a)所示之複數個三角形金屬膜8取代一 個長方形金屬膜8。 如前面所述,形成複數個金屬膜8,可使相鄰金屬膜8之 間形成空間。前述空間可以成為樹脂密封時之樹脂通路, 可促進樹脂之流動。利用此方式,樹脂密封會更為容易。 又,形成複數金屬膜8時,相鄰之金屬膜8間的間隔最好 大於相鄰配線圖案5間的間隔。 利用此方式,相鄰金屬膜8間之空間會較大,樹脂更容易 流入。又,前述空間可以促進並更易流入充足量之樹脂, 而降低樹脂密封不充份或密封不良的機會。 又,如圖3(b)所示,亦可形成複數個圓形之金屬膜8。亦 可如圖3(c)所示,形成複數個長條形之金屬膜8。圖上未標 不出來,金屬膜之形狀也可以為四角形、菱形、梯形等。 如上面所述,形成複數個金屬膜時,最好為數十個〜數百 個之均一配列。亦可只形成1個前述形狀之金屬膜。 此外,半導體元件設置位置7上之前述金屬膜8最好為點 對稱或線對稱之(配置)^此處將點對稱及線對稱合併稱為對 稱。 薄臈基板4一般會以上下左右對稱(薄膜基板4面上之所有 方向為均一)方式伸長。然而,因為形成金·屬膜8 ,可抑制 形成金屬膜8之薄膜基板4區域的伸長β所以,利用如上所 不之金屬膜8的配列,在薄膜基板4上形成金屬膜8之區域, 在所有方向會有均一之伸|。因此,因Α薄膜基板4整體可 以向所有方向伸長,故可更進一步防止皺紋之產生。 -14- 557522 A7 B7 11 五、發明説明( 另外,三角形之金屬膜8時,最好採相鄰金屬膜8之三角 形一邊(底邊)相向方式形成。又,梯形之金屬膜8時,最好 採上底或下底相向方式形成。 又如圖4所示,前述金屬膜8亦可在薄膜基板4之兩面上同 時形成。利用此方式,可更進一步抑制熱應力造成之薄膜 基板4的伸縮,亦可更進一步減少配線圖案5及半導體元件工 之連接不良。又,前述金屬膜8亦可以只在未形成配線圖案 5之配線基板6的一面上形成。 連續形成半導體裝置時,如圖5所示,可以在膠帶上連續 並列(複數)前述配線基板6來實施形成,亦即帶载體^此 處,並列配線基板6之方向為縱向,和縱向互相垂直之方向 為橫向。 ° 前述帶載體10上,橫向之兩側邊沿著縱向以一定間隔形 成傳送孔11。此傳送孔丨丨會和圖上未標示之傳送裝置互相 咬合,使帶載體10朝縱向移動。如此,可連續實施半導體 元件及配線基板6之連接,而可提高半導體裝置之生產效率。 將半導體元件連接於帶載體10之配線基板6上,並對安裝 半導體元件之部份的帶載體1〇實施切刀或鑽頭之衝切。衝 切所得即為個別之半導體裝置。此半導體裝置會被安裝至 電子機器。 、 本發明之半導體裝置,如前面所述,因為可以減少各配 線基板6及半導體元件之連接上的位置偏離,而實施連續連 接之帶載體10的累積位置偏離亦可減少。所以,連續執行 半導體元件之安裝時,可降低Au凸塊及配線圖案之連接不 -15-
557522 A7 ___^_ B7 五、發明説明(12 ) 良。 本發明之半導體裝置除了前述構成以外,最好以和配線 圖案相同之材料來形成前述補強膜。 利用前述構成,很容易同時形成配線圖案及補強膜,可 提高生產效率。又,因無需另設新製造步驟,可以低成本 形成補強膜。 此外,因前述補強膜係以和配線圖案相同之材料(例如, 金屬等)形成,可以阻隔透過薄膜基板而照射於半導體元件 表面之外部光線(α射線)。所以,亦可防止因〇;線照射而產 生之半導體裝置的錯誤動作。 又,本發明之半導體裝置除了前述構成以外,前述補強 膜之厚度最好小於配線圖案之厚度。 利用前述構成,補強膜之厚度小於配線圖案之厚度,半 導體元件及配線基板間會產生空間。因為有此空間,密封 時’則述樹脂容易流入半導體元件及配線基板間。所以, 容易實施密封。又,因和半導體元件之距離較遠,可以避 免半導體元件及補強膜相相接觸。利用此方式,可以避免 半導體元件因和補強膜接觸而損壞。 又,本發明之半導體裝置除了前述構成以外,補強膜厚 度最好為配線圖案厚度之1/3〜2/3。 利用前述構成,前述樹脂更容易流入半導體元件及配線 基板之間,所以,樹脂密封亦會更為容易。 本發明之半導體裝置,除了前述構成以外,最好能在前 述薄膜基板上形成相互獨立之複數個前述補強膜。 •16-
557522 A7 __^___B7_ 五、發明説明(13 ) 利用前述構成,相鄰補強膜之間會形成空間。前述空間 可以成為樹脂密封時之樹脂通路,可促進樹脂之流動。利 用此方式,樹脂密封會更為容易。 本發明之半導體裝置,除了前述構成以外,相鄰之前述 補強膜間的間隔最好大於相鄰配線圖案間的間隔。 利用前述構成,補強膜間之空間會較大,樹脂更容易流 入。又,前述空間可以促進並更易流入充足量之樹脂,而 降低樹脂密封不充份或密封不良的機會。 本發明之半導體裝置,除了前述構成以外,前述補強膜 最好以對稱方式在薄膜基板上形成。 利用前述構成,補強膜係以對稱(點對稱或線對稱)形成, 在薄膜基板上形成補強膜之區域,在所有方向會有均一之 伸長因此,因為薄膜基板整體可以向所有方向伸長,故 可更進一步防止皺紋之產生。 本發明之半導體裝置,除了前述構成以外,最好在配線 基板之兩面形成前述補強膜。 利用前述構成,可以更進—步抑制薄膜基板因熱應力而 產生的伸縮,亦可更進一步減少配線圖案及半導體元件之 連接不良。 本發明之半導體裝置除上述構造外,上述補強膜較佳為 二角形、四角形或圓形。 ,本發明之半導體裝置,除了前述構成以外,前述補強膜 為二角形或四角形時,相鄰補強膜之一邊應相互對向。 為了解則述問題,本發明之配線基板係在薄膜基板上形 -17-
557522 A7 發明説明(14 成-線圖案之配線基板,前述薄膜基板上未形成配線圖案 之區垃卜 ,-r· ’、可以線膨脹係數小於薄膜基板之線膨脹係數 的材料,形成補強膜。 利用刖述構成’因薄膜基板上會形成補強膜,薄膜基板 之=長會抑制為補強膜之較小伸長。亦即,補強膜會抑 i薄膜基板之伸長。利用此方式,可以提升配線基板之尺 寸安定性。 又,如前面所述,因形成補強膜而使薄膜基板不易伸長 ’故可防止薄膜基板上產生皺紋。 本發月之帶載體較佳者為在帶上形成有複數之上述 配線基板。 、利用前述構成,例如在製造半導體裝置時,可連續實施 半導體7G件及配線基板之連接,因而提高半導體裝置之生 產效率。 發明之詳細說明中的具體實施形態或實施例只是為了 說明本發明之技術内容而已’不能採取狹義解釋而將範圍 限定於此具韹實例,只要符合本發明之精神及在下面記載 之申請專利範圍内者,可實施各種變更。 -18- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐)
Claims (1)
- 557522 A8 B8 C8 _____ D8_ 六、申請專利範圍 1· 一種半導體裝置,其特徵為··其係包含半導體元件、及 在薄膜基板上形成配線圖案之配線基板,且半導體元件 和配線圖案相連接,並以樹脂密封半導體元件及配線基 板者;且 在前述薄膜基板之至少一側未形成配線圖案之區域, 以線膨脹係數小於薄膜基板之材料形成補強膜。 2·如申請專利範圍第1項之半導體裝置,其中 前述補強膜係以和配線圖案相同之材料形成。 3·如申請專利範圍第1項之半導體裝置,其中 刖述補強膜之厚度小於配線圖案之厚度。 4.如申請專利範圍第3項之半導體裝置,其中 月1J述補強膜之厚度為配線圖案之厚度的丨/3〜2/3。 5·如申請專利範圍第1至4項中任一項之半導體裝置,其中 前述薄膜基板上形成互相獨立之複數個前述補強膜。 6. 如申請專利範圍第5項之半導體裝置,其中 相郴刖述補強膜間之間隔大於相鄰配線圖案間之間隔。 7. 如申請專利範圍第5項之半導體裝置,其中 前述補強膜係以對稱方式在薄膜基板上形成。 8·如申請專利範圍第1至4項中任一之半導體裝置,其中 前述補強膜在配線基板之兩面上形成。 9·如申印專利範圍第1至4項中任一之半導體裝置,其中 刖述補強膜為三角形、四角形、或圓形。 1〇·如申請專利範圍第9項之半導體裝置,其中 刖述補強膜為三角形或四角形,且相鄰補強膜之一邊乃 7522 A8 B8相互對向。 U.如^請專利範圍第!至4項中任一之半導體裝置,其中 前述補強膜可以阻隔射線。 12.如^請專利範圍第li4項中任一之半導體裝置,其中 刚述補強膜係和前述配線圖案分開形成。 13·如申請專利範圍第項中任一之半導體裝置,其中 刖述薄膜基板係以聚醯亞胺樹脂、聚酯樹脂等絕 料所構成。 '何 4.如申凊專利範圍第1至4項中任一之半導體裝置,其中 前述補強膜係為金屬構成之金屬膜。 15· —種配線基板,係在薄膜基板上形成配線圖案,其特徵 為: 前述薄膜基板上未形成配線圖案之區域,以線膨脹係 數小於薄膜基板之材料形成補強膜。 、 ^ 一種帶載體,其特徵為: 膠帶上形成複數之如申請專利範圍第丨5項配線基板。 -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001205121A JP3866058B2 (ja) | 2001-07-05 | 2001-07-05 | 半導体装置、配線基板及びテープキャリア |
Publications (1)
Publication Number | Publication Date |
---|---|
TW557522B true TW557522B (en) | 2003-10-11 |
Family
ID=19041489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091112902A TW557522B (en) | 2001-07-05 | 2002-06-13 | Semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US7193328B2 (zh) |
JP (1) | JP3866058B2 (zh) |
KR (1) | KR100475618B1 (zh) |
CN (1) | CN1246899C (zh) |
TW (1) | TW557522B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI693870B (zh) * | 2017-09-15 | 2020-05-11 | 韓商斯天克有限公司 | 電路板及其製造方法 |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3892650B2 (ja) | 2000-07-25 | 2007-03-14 | 株式会社日立製作所 | 液晶表示装置 |
JP4212255B2 (ja) * | 2001-03-30 | 2009-01-21 | 株式会社東芝 | 半導体パッケージ |
US20070023877A1 (en) * | 2003-09-10 | 2007-02-01 | Hideo Yamazaki | Chip on flex tape with dimension retention pattern |
JP2005086098A (ja) * | 2003-09-10 | 2005-03-31 | Three M Innovative Properties Co | チップオンフレックス(cof)テープ |
KR100568224B1 (ko) | 2003-11-04 | 2006-04-07 | 삼성전자주식회사 | 테이프 배선 기판 및 그를 포함하는 반도체 장치 |
JP2006148072A (ja) * | 2004-10-18 | 2006-06-08 | Hitachi Chem Co Ltd | 配線板 |
JP2006286852A (ja) * | 2005-03-31 | 2006-10-19 | Sumitomo Bakelite Co Ltd | 樹脂組成物、樹脂層、樹脂層付きキャリア材料および回路基板 |
JP4619214B2 (ja) * | 2005-07-04 | 2011-01-26 | 日東電工株式会社 | 配線回路基板 |
TWI285523B (en) * | 2005-08-19 | 2007-08-11 | Chipmos Technologies Inc | Flexible substrate capable of preventing lead thereon from fracturing |
JP4685601B2 (ja) * | 2005-11-16 | 2011-05-18 | 新光電気工業株式会社 | 実装基板および半導体装置 |
JP2009528933A (ja) | 2006-03-06 | 2009-08-13 | エルジー・ケム・リミテッド | 金属積層板およびその製造方法 |
KR100788415B1 (ko) | 2006-03-31 | 2007-12-24 | 삼성전자주식회사 | 이엠아이 노이즈 특성을 개선한 테이프 배선기판 및 그를이용한 테이프 패키지 |
JP5273333B2 (ja) * | 2006-12-28 | 2013-08-28 | 株式会社ジャパンディスプレイ | 表示装置 |
JP2008177351A (ja) * | 2007-01-18 | 2008-07-31 | Fujitsu Ltd | 電子装置および電子装置の製造方法 |
JP5029026B2 (ja) * | 2007-01-18 | 2012-09-19 | 富士通株式会社 | 電子装置の製造方法 |
JP4378387B2 (ja) * | 2007-02-27 | 2009-12-02 | Okiセミコンダクタ株式会社 | 半導体パッケージ及びその製造方法 |
JP5014945B2 (ja) * | 2007-10-17 | 2012-08-29 | シャープ株式会社 | 半導体装置 |
JP2009182228A (ja) * | 2008-01-31 | 2009-08-13 | Nitto Denko Corp | 配線回路基板およびその製造方法 |
JP5238274B2 (ja) * | 2008-01-31 | 2013-07-17 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
EP2286449A1 (en) * | 2008-05-30 | 2011-02-23 | Nxp B.V. | Thermo-mechanical stress in semiconductor wafers |
JP5644286B2 (ja) * | 2010-09-07 | 2014-12-24 | オムロン株式会社 | 電子部品の表面実装方法及び電子部品が実装された基板 |
JP5597564B2 (ja) * | 2011-02-04 | 2014-10-01 | 株式会社日本マイクロニクス | プローブ装置及びその製造方法 |
JP5296116B2 (ja) * | 2011-02-16 | 2013-09-25 | シャープ株式会社 | 半導体装置 |
JP5962285B2 (ja) * | 2012-07-19 | 2016-08-03 | 日亜化学工業株式会社 | 発光装置およびその製造方法 |
US9997676B2 (en) | 2014-05-14 | 2018-06-12 | Genesis Photonics Inc. | Light emitting device and manufacturing method thereof |
US10439111B2 (en) | 2014-05-14 | 2019-10-08 | Genesis Photonics Inc. | Light emitting device and manufacturing method thereof |
TWI557952B (zh) | 2014-06-12 | 2016-11-11 | 新世紀光電股份有限公司 | 發光元件 |
JPWO2017037828A1 (ja) * | 2015-08-31 | 2018-06-14 | オリンパス株式会社 | 内視鏡、電子ユニットおよび電子ユニットの製造方法 |
CN106549092A (zh) | 2015-09-18 | 2017-03-29 | 新世纪光电股份有限公司 | 发光装置及其制造方法 |
US10388838B2 (en) | 2016-10-19 | 2019-08-20 | Genesis Photonics Inc. | Light-emitting device and manufacturing method thereof |
CN109755220B (zh) | 2017-11-05 | 2022-09-02 | 新世纪光电股份有限公司 | 发光装置及其制作方法 |
TW201919261A (zh) | 2017-11-05 | 2019-05-16 | 新世紀光電股份有限公司 | 發光裝置 |
KR102088920B1 (ko) * | 2017-12-13 | 2020-03-13 | 주식회사 엘비루셈 | 2층 패턴형 cof 패키지용 필름 |
CN110416078A (zh) | 2019-08-02 | 2019-11-05 | 武汉新芯集成电路制造有限公司 | 光刻工艺的扩张补偿的确定方法、装置及器件的制造方法 |
US11393746B2 (en) | 2020-03-19 | 2022-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reinforcing package using reinforcing patches |
TWI784661B (zh) * | 2021-08-09 | 2022-11-21 | 頎邦科技股份有限公司 | 軟性電路板之佈線結構 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156239A (ja) | 1984-12-28 | 1986-07-15 | Canon Inc | 閃光撮影装置 |
JPS61156239U (zh) * | 1985-03-19 | 1986-09-27 | ||
JPH01286430A (ja) | 1988-05-13 | 1989-11-17 | Matsushita Electric Ind Co Ltd | 半導体チップの実装方法 |
JP2707903B2 (ja) * | 1992-01-28 | 1998-02-04 | 日本電気株式会社 | 多層プリント配線板の製造方法 |
US5616520A (en) * | 1992-03-30 | 1997-04-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and fabrication method thereof |
US5510758A (en) | 1993-04-07 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps |
JPH0837208A (ja) | 1994-07-25 | 1996-02-06 | Toshiba Corp | 半導体素子の実装方法およびその装置 |
JPH0867976A (ja) | 1994-08-26 | 1996-03-12 | Mitsubishi Materials Corp | 耐熱応力割れ性に優れたシリサイド薄膜形成用複合スパッタリングターゲット |
JP3724606B2 (ja) * | 1995-05-22 | 2005-12-07 | 日立化成工業株式会社 | 半導体チップの接続構造及びこれに用いる配線基板 |
EP0827632B1 (en) * | 1995-05-22 | 2002-01-09 | Hitachi Chemical Co., Ltd. | Semiconductor device having a semiconductor chip electrically connected to a wiring substrate |
JPH0992683A (ja) * | 1995-09-25 | 1997-04-04 | Fujitsu Ltd | 半導体装置 |
JPH1098072A (ja) * | 1996-09-20 | 1998-04-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2962351B2 (ja) | 1997-03-31 | 1999-10-12 | 日本電気株式会社 | 半導体チップへの接合構造及びそれを用いた半導体装置 |
US6088901A (en) * | 1997-06-10 | 2000-07-18 | Siemens Aktiengesellschaft | Method for producing a carrier element for semiconductor chips |
JPH11354684A (ja) | 1998-06-09 | 1999-12-24 | Nitto Denko Corp | 低熱膨張配線基板および多層配線基板 |
WO2000026959A1 (en) * | 1998-10-30 | 2000-05-11 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board and electronic device |
JP3613098B2 (ja) | 1998-12-21 | 2005-01-26 | セイコーエプソン株式会社 | 回路基板ならびにそれを用いた表示装置および電子機器 |
JP3640155B2 (ja) | 1999-01-26 | 2005-04-20 | セイコーエプソン株式会社 | 可撓性配線基板、フィルムキャリア、テープ状半導体装置、半導体装置、回路基板並びに電子機器 |
JP3555502B2 (ja) * | 1999-05-27 | 2004-08-18 | 日立電線株式会社 | Cof用tabテープキャリアの製造方法 |
-
2001
- 2001-07-05 JP JP2001205121A patent/JP3866058B2/ja not_active Expired - Lifetime
-
2002
- 2002-06-11 US US10/166,076 patent/US7193328B2/en not_active Expired - Lifetime
- 2002-06-13 TW TW091112902A patent/TW557522B/zh not_active IP Right Cessation
- 2002-07-04 KR KR10-2002-0038532A patent/KR100475618B1/ko not_active IP Right Cessation
- 2002-07-05 CN CNB021406251A patent/CN1246899C/zh not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI693870B (zh) * | 2017-09-15 | 2020-05-11 | 韓商斯天克有限公司 | 電路板及其製造方法 |
US11147160B2 (en) | 2017-09-15 | 2021-10-12 | Stemco Co., Ltd. | Circuit board and method for manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
JP3866058B2 (ja) | 2007-01-10 |
KR100475618B1 (ko) | 2005-03-15 |
US20030006509A1 (en) | 2003-01-09 |
KR20030005022A (ko) | 2003-01-15 |
CN1246899C (zh) | 2006-03-22 |
US7193328B2 (en) | 2007-03-20 |
JP2003023035A (ja) | 2003-01-24 |
CN1396653A (zh) | 2003-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW557522B (en) | Semiconductor device | |
US7911050B2 (en) | Semiconductor device and method for manufacturing the same | |
KR100793468B1 (ko) | 반도체 장치 및 그 제조 방법과, 상기 반도체 장치를 구비한 액정 모듈 및 반도체 모듈 | |
US7750457B2 (en) | Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus | |
US20110204497A1 (en) | Semiconductor integrated circuit and method for manufacturing the same | |
TW201038148A (en) | Flexible printed circuit board | |
JPH09260579A (ja) | フレキシブル配線基板の端子構造およびそれを用いたicチップの実装構造 | |
JP3722223B2 (ja) | 半導体装置及びその製造方法、電子モジュール並びに電子機器 | |
JP3679989B2 (ja) | チップキャリアフィルムおよびその製造方法ならびにこのチップキャリアフィルムを使用した液晶表示装置 | |
KR100837281B1 (ko) | 반도체 소자 패키지 및 그 제조 방법 | |
US7474007B2 (en) | Semiconductor package | |
JP2006228932A (ja) | 半導体パッケージ | |
JP3736638B2 (ja) | 半導体装置、電子モジュール及び電子機器 | |
JP2004119474A (ja) | 半導体装置 | |
JP2004119650A (ja) | 半導体装置 | |
JPH11330318A (ja) | 半導体装置の実装体の製造方法 | |
JP2009128779A (ja) | 液晶表示装置及びその製造方法 | |
JP2004063805A (ja) | 半導体装置 | |
CN201072757Y (zh) | 薄膜覆晶封装 | |
JP2002208608A (ja) | 半導体装置 | |
JP2002299387A (ja) | 半導体装置用テープキャリアおよびその製造方法 | |
JP2005121757A (ja) | 基板接続構造、電子部品、液晶表示装置および電子部品の製造方法 | |
JP2006053338A (ja) | 液晶表示装置 | |
JP2002305219A (ja) | テープキャリアパッケージ半導体装置およびその製造方法 | |
US20050127523A1 (en) | Semiconductor device, method of manufacturing semiconductor device, semiconductor chip, electronic module and electronic equipment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |