TW494450B - Communicating device - Google Patents

Communicating device Download PDF

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Publication number
TW494450B
TW494450B TW090102845A TW90102845A TW494450B TW 494450 B TW494450 B TW 494450B TW 090102845 A TW090102845 A TW 090102845A TW 90102845 A TW90102845 A TW 90102845A TW 494450 B TW494450 B TW 494450B
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TW
Taiwan
Prior art keywords
layer
composition
semiconductor
single crystal
buffer layer
Prior art date
Application number
TW090102845A
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English (en)
Inventor
Jamal Ramdani
Ravindranath Droopad
Lyndee L Hilt
Kurt William Eisenbeiser
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Motorola Inc
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Publication of TW494450B publication Critical patent/TW494450B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261—Non-optical elements, e.g. laser driver components, heaters
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
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  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Lasers (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Description

494450 經濟部智慧財產局員工消費合作社印製 A7 B7_五、發明說明（1 ) 發明範噃 本發明通常與包含半導體結構的通信裝置有關，尤其， 本發明與組合物半導體結構及半導體結構之製造暨使用有 關，其中該半導體結構包含一單晶組合物半導體材料。 發明背景 絕大部分的半導體離散裝置及積體電路都是以矽爲材料 所製造而成，至少在某種程度上是因爲低成本、高品質單 晶矽基材的可用性所致。諸如所謂的組合物半導體材料之 類的其他半導體材料具有物理屬性包括比碎更寬的帶隙及 /或更高的遷移率，或是使這些材料非常適用於特定半導體 裝置的直接帶隙。可惜，組合物半導體材料的成本通常高 於矽，並且在大型晶圓中，不如矽那樣容易取得。晶圓中 可取得的神化鎵（Gallium arsenide ; GaAs)(最容易取得的組 合物半導體材料）的直徑最大只有大約150微米（mm)。相反 地，可取得的矽晶圓具有最大大約3 00毫米（mm)的直徑，並 且最廣泛使用的是200 mm。150 mm GaAs晶圓的成本高於 對應的矽晶圓許多倍。其他的組合物半導體材料晶圓更不 容易取得，並且成本比GaAs更高。 因爲希望有組合物半導體材料的特性，並且因爲通常目 前其成本高及較無法取得大容積形式，所以許多年來已嘗 試在異質基材上生長組合物半導體材料薄膜。然而，爲了 實現最佳的組合物半導體材料特性，需要高結晶品質的單 晶膜。例如，已嘗試在鍺、矽及各種隔離體上生長單晶組 合物半導體材料層。這些嘗試尚未成功，因爲主晶與生長 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 — — — — — — — — — > 經濟部智慧財產局員工消費合作社印製 494450 A7 __B7 五、發明說明（2 ) 晶間的晶格不匹配，導致所產生的組合物半導體材料薄膜 的結晶品質不佳。 如果以低成本取得大面積高品質單晶組合物半導體材料 .薄膜，則有助於以低成本在該薄膜上製造各種半導體裝置 ，其成本低於在組合物半導體材料的大容積晶圓上製造此 類裝置的成本，或是低於在組合物半導體材料之大容積晶 圓上此類材料的系晶膜中製造此類裝置的成本。此外，如 果能夠在諸如矽晶圓的大容積晶圓上體現高品質單晶組合 物半導體材料的薄膜，則可利用矽及組合物半導體材料的 特性來實現積體裝置結構。 因此，需要有一種使用一半導體結構的通信裝置存在， 其中該半導體結構能夠提供優於另一種單晶材料的高品質 單晶組合物半導體膜。 圖式簡單説明 本發明將藉由範例及附圖來進行解説，但本發明未限定 在這些範例及附圖内，其中相似的參照代表相似的元件， 並且其中： 圖1、2、4、5顯示根據本發明各種具體實施例之裝置結 構的斷面圖； 圖3以圖表顯示可獲得的最大膜厚度與主晶和生長結晶 覆蓋層間晶格不匹配間的關係； 圖6顯示通信裝置一部分的方塊圖； 圖7到11顯示包括組合物半導體部分、雙極性部分及MOS 部分之積體電路一部分的斷面圖；以及 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂—------- > 經濟部智慧財產局員工消費合作社印製 494450 A7 __B7_____ 五、發明說明（3 ) 圖12到18顯示包括半導體雷射及MOS電晶體之另一積體 電路·一部分的斷面圖。 熟知技藝人士應明白，圖中的元件是簡化的圖解，並且 不需要按比例繪製。例如，相對於其他元件，圖中部分元 件的尺寸可能過度放大，以利於更容易瞭解本發明的具體 實施例。 圖式詳細説明 圖1顯示根據本發明一項具體實施例之半導體結構20之 一部分的斷面圖。半導體結構20包括單晶基材22、包含單 晶材料的容納緩衝層2 4以及單晶組合物半導體材料層2 6。 在此上下文中，術語「單晶」應具有半導體產業内常用的 意義。術語「單晶」應代表屬於單晶或實質上屬於單晶的 材料，並且應包含具有相當少量缺陷（諸如矽或矽化鍺或混 合物之基材中常發現的位錯等等）的材料，以及半導體產業 中常發現之此類材料的磊晶層。 根據本發明一項具體實施例，結構20還包括位於基材22 與容納緩衝層24之間的非結晶中間層28。結構20還可包括 位於容納緩衝層與組合物半導體層26之間的模板層30。如 下文中詳細的説明，模板層有助於在容納緩衝層上開始生 長組合物半導體層。非結晶中間層有助於減緩容納緩衝層 應變，並藉此協助生長高結晶品質容納緩衝層。 根據本發明一項具體實施例，基材22是單晶矽晶圓，最 好是大尺寸單晶矽晶圓。晶圓可能屬於周期表第IV族材料 ，並且最好是第IVA族材料。第IV族半導體材料的範例包 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 -----訂-------- 494450 A7 ___B7 _ 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 括矽、鍺、混合矽與鍺、混合矽與碳、混合矽、鍺與碳等 等。基材22最好是包含矽或鍺的晶圓，並且最好是如半導 體業產中使用的高品質單晶矽晶圓。容納缓衝層24最好是 基礎基材上磊晶生長的單晶氧化物或氮化物材料。根據本 發明一項具體實施例，非結晶中間層28係在基材22上生長 ，並位於基材22與生長的容納緩衝層之間，其方式是在生 長容納緩衝層24期間氧化基材22。非結晶中間層係用來減 緩由於基材與緩衝層間晶格常數差異而導致容納緩衝層可 能會發生的應變。在本文中，晶格常數代表在表面平面上 所測量之細胞原子間的距離。如果非結晶中間層未減缓此 類的應變，則應變會導致容納緩衝層中結晶結構中的缺陷 。接著，容納緩衝層中結晶結構中的缺陷將導致難以實現 单晶組合物半導體層2 6中的南品質結晶結構。 經濟部智慧財產局員工消費合作社印製 容納緩衝層24最好是選用與基礎基材結晶相容及與覆蓋 組合物半導體材料結晶相容的單晶氧化物或氮化物材料。 例如，此類的材料可能是具有與基材匹配且與後續供應的 半導體材料匹配之晶格結構的氧化物或氮化物。容納緩衝 層所適用的材料包括氧化金屬，諸如鹼土金屬鈦酸鹽、鹼 土金屬錘酸鹽、鹼土金屬給酸鹽、鹼土金屬妲酸鹽、鹼土 金屬釕酸鹽、鹼土金屬鈮酸鹽、鹼土金屬飢酸鹽、鹼土金 屬錫基 #5 鈥礦（alkaline earth metal tin_based perovskites) 、鑭鋁酸鹽、氧化鑭銃及氧化釓。另外，容納緩衝層也可 使用諸如氮化鎵、氮化鋁及氮化硼之類的氮化物。這些材 •料大部分是隔離體，雖然（例如）鳃、釕是導體。一般而言 -7- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 494450 A7 ___B7 _ 五、發明說明（5 ) ，這些材料是氧化金屬或氮化金屬，尤其，這些氧化金屬 •或氮化金屬包括至少兩個不同的金屬元素。在某些特定應 用中，氧化金屬或氮化金屬包括至少三個或三個以上不同 的金屬元素。 非結晶中間層28最好是藉由將基材22表面氧化所形成的 氧化物，尤其是由氧化矽所組成。非結晶中間層28的厚度 足以減缓因基材22與容納緩衝層24的晶格常數間不匹配所 導致的應變。通常，非結晶中間層2 8的厚度大約是0.5到5 毫微米（nm)。 可按照特定半導體結構的需求，從第ΠΙΑ與VA族元素 (III-V半導體組合物）、混合III-V組合物、第ΙΙ(Α與Β)與VIA 族元素（II-VI半導體組合物），以及混合II-VI組合物中選用 單晶組合物半導體層26的組合物半導體材料。範例包括砷 化鎵（GaAs)、砷化鎵銦（GalnAs)、砷化鎵鋁（GaAlAs)、磷 化銦（InP)、硫化鎘（CdS)、碲化鎘汞（CdHgTe)、硒化鋅（ZnSe) 、硒化鋅硫（ZnSSe)等等。適合的模板材料以化學方式键合 在容納緩衝層24表面上的選取部位，並提供後續組合物半 導體層26磊晶生長集結（nucleation)的部位。下文中將説明 適用於模板層30的材料。 圖2顯示根據本發明另一項具體實施例之半導體結構40 之一部分的斷面圖。結構40類似於前文説明的半導體結構 20，除了介於容納緩衝層24與單結構組合物半導體材料層 2 6間的額外緩衝層3 2以外。具體而言，額外缓衝層位於模 板層30與覆蓋組合物半導體材料層之間。當容納緩衝層無 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------·
五、發明說明（6 法適當匹配覆蓋單晶組合物半導體材料層時，半導體或組 合物丰導體材料所形成的額外緩衝層係用來提供晶格補償 〇 下列非限制性、作例證的範例說明根據本發明各種替代 具體實施例之結構20與結構40中可用的各種材料組合。這 些完全是用來説明，並且本發明不限定於這些作例證的範 例〇 範例1 根據本發明一項具體實施例，單晶基材22係以（1〇〇)方向 爲目的之碎基材。矽基材可能是（例如）用來製造直徑大約 爲200到3 00 mm之互補金屬氧化物半導體（CM〇s)積體電路 中常用的矽基材。根據本發明的此項具體實施例，容納緩 衝層24是SrzBa^TiO3單晶層，其中z介於0到1範圍内，而 非結晶中間層是在介於矽基材與容納緩衝層間之界面上形 成的氧化石夕（SiOx)層。所選用的z値是爲了獲得緊密匹配對 應之後績形成層26之晶格常數的一個或一個以上晶格常數 。例如’容納緩衝層的厚度大約在2 nm到100 nm的範圍内 ，並且最好是大約10 nm的厚度。一般而言，希望容納緩衝 層的厚度足以隔離組合物半導體層與基材，以獲得所希望 的電子及光學特性。厚度低於100 nm的層通常提供較少的 額外優點，並增加不必要的成本；然而，若需要，可製造 較厚的層。氧化矽非結晶中間層厚度大約在〇·5 nm到5 nm 的範圍内’並且最好是大約1 5 nm到2.5 nm的厚度。 根據本發明的此項具體實施例，組合物半導體材料層26 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------. 經濟部智慧財產局員工消費合作社印製 494450 經濟部智慧財產局員工消費合作社印製 A7 _______B7____ 五、發明說明（7 ) .是砷化鎵（GaAs)或砷化鋁鎵（AiGaAs)層，其厚度大約是丄 nm到大約1〇〇微米（μπι)，並且最好是大約〇.5 μηι到1〇 ^的 厚度。厚度通常視所準備之層的應用而定。爲了促進在單 晶氧化物上磊晶生長砷化鎵或砷化鋁鎵，將藉由覆蓋氧化 層來形成模板層。模板層最好是Ti-As、Sr-O-As、Sr-Ga-0 或Sr-A1 -Ο的1到10層單分子層（m〇n〇iayer)。藉由較佳範例 ，已證實Ti-As或Sr-Ga-Ο的1到2層單分子層可成功生長 GaAs 層0 範例2 根據本發明進一步具體實施例，單晶基材22是如上文所 述的梦基材。容納缓衝層24是立體或斜方晶相之鳃或鋇锆 酸鹽或铪的單晶氧化物，而非結晶中間層是在介於矽基材 與容納缓衝層間之界面上形成的氧化矽層。容納緩衝層的 厚度大約在2 nm到100 nm的範圍内，並且最好是至少5 nm 的厚度，以確保足夠的結晶及表面品質，並且是由單晶
SrZi:03、BaZr03 ' Si:Hf03、BaSn03 或 BaHf03所組成。例如 ，可在大約700度C的溫度下生長BaZr〇3單晶氧化層。所產 生心結晶氧化物的晶格結構呈現相對於基材矽晶格結構的 45度旋轉。 由這些鋇锆酸鹽或給材料所形成的容納缓衝層適合在磷 化銦（InP)系統中生長組合物半導體材料。組合物半導體材 料可旎疋（例如）厚度大約是1.〇 ηη^ 1〇 的磷化銦（Inp) 或砷化銦鎵（InGaAs)。適用於此結構的模板層是锆-砷 (Zi*-As)、锆-轉（Zr-Ρ)、铪·绅（Hf_As)、铪·、鐵一氧 _ -10- 本紙張尺度適用中國國家標準（CNS)A4規格⑵G x 297公爱) Μ--------IT--------- (請先閱讀背面之注意事項再填寫本頁) 494450 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（8 ) -石申（Sr-0-As)、銘-氧-轉（Sr-O-P)、鎖-氧-神（Ba-Q-As)、铜_ 鳃-氧（Ιη-Sr-O)或鋇-氧-磷（Ba-Ο-Ρ)的1到1〇層單分子層 (monolayer)，並且最好是這些材料其中一個的1到2層單分 子層。藉由範例，就鋇錘酸鹽容納緩衝層而言，表面係以 結的1到2層單分子層終止，之後接著沈積碎的1到2層單分 子層，以形成Zr-As模板。然後，在模板層上生長以轉化銦 系統爲材料的組合物半導體材料的單晶層。所產生之組合 物半導體材料的晶格結構呈現相對於容納緩衝層晶格結構 的45度旋轉，並且不匹配（100) InP的晶格小於2 5%，並且 最好小於大約1.0%。 範例3 根據本發明進一步具體實施例，假設結構適合生長π_νι 材料磊晶膜，以覆蓋;?夕基材。如上文所述，基材最好是石夕 晶圓。適合的容納緩衝層材料是SrxBai xTi〇3，其中χ介於〇 到1範圍内’厚度大約在2 nm到100 nm的範園内，並且最好 是大約5 nm到15 nm的厚度。Π-VI組合物半導體材料可能是 (例如）鋅亞硒酸鹽（znSe)或鋅硫亞硒酸鹽（ZnSSe)。適用於 此材料系統的模板層包括鋅-氧（Zn-O)的1到1 〇層單分子層 ’心後接著過量的鋅的1到2層單分子層，之後接著位於表 面上的鋅亞涵酸鹽。或者，模板層可能是（例如）鐵_硫（Sr_s) ，之後接著ZnSeS。 範例4 ’發明的此項具體實施例是圖2所示之結構4 〇的範例。基 材22、單晶氧化層24及單晶組合物半導體材料層％可能類 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------
494450 A7 B7 經濟部智慧財產局員工消費合作社印制π 五、發明說明（9 似於範例1中所説明對應項。此外，額外緩衝層3 2係用來減 缓應變’其中應變是由於容納緩衝層晶格與單晶半導體材 料間不匹配所致。緩衝層32可能是砷磷化鎵（GaASxPix)或 磷化銦鎵（InyGai_yP)應變補償超晶格。在砷磷化鎵超晶格中 ，X値介於0到1範圍内，而在磷化銦鎵超晶格中，y値介於q 到1範圍内。藉由看情況來改變χ値或y値，晶格常數會隨之 橫跨超晶格從下到上變改，以產生基礎氧化物與覆蓋組合 物半導體材料之晶格常數間的匹配。超晶格的厚度大約在 50 nm到500 !^的範圍内，並且最好是大约2〇〇 1^到1〇〇 nm 的厚度。此結構的模板可能與範例1中説明的模板相同。或 者’緩衝層可能是厚度爲1 nm到5 〇 nm的的單晶錯，並且最 好是大約2 nm到20 nm的厚度。在使用鍺緩衝層的過程中， 可使用厚度大約一個單分子層的鍺·鳃（Ge_Sr)或鍺鈦 (Ge-Ti)的模板層。形成氧化層的方式是覆蓋單分子層翅或 單分子層鈥，以作爲後續沈積單晶鍺的集結部位。單分子 層銘或單分子層鈦提供第一單分子層鍺可鍵合的集結部位 〇 範例5 此範例還説明圖2所示之結構40中使用的材料。基材材料 22、容納緩衝層24及單晶組合物半導體材料層26及模板層 30可能與範例2中所説明對應項相同。此外，會在容納緩二 層與覆蓋單晶組合物半導體材料層之間插入緩衝層32。缓 衝層（進一步的單晶半導體材料）可能是（例如）砷化銦鎵 (InGaAs)的粒級層（graded layer)，其中銦成份大約從〇到 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------. -12- 494450
47%間變化。緩衝層的厚度最好大約是10到30 nm。將緩衝 層成份從GaAs變化成InGaAs，以提供基礎單晶氧化材料與 單晶組合物半導體材料覆蓋層間的晶格匹配。如果容納緩 衝層24與早晶組合物半導體材料層％間晶格不匹配，則此 類的緩衝層特別有利。 請重新參考圖1及2，基材22是諸如單晶矽基材之類的單 晶基材。單晶基材結晶結構的特徵在於晶格常數及晶格方 向。在類似的方法中，容納緩衝層24也是單晶材料，並且 單晶材料晶格的特徵在於晶格常數及晶體方向。容納緩衝 層與早晶基材的必須緊密匹配，或者，必須某一晶體方向 係對著另一晶體方向旋轉，才能達成實質上晶格常數匹配 。在此上下文中，「實質上等於」及「實質上匹配」表示 晶格常數間有充足的相似點，而能夠在基礎層上生長高品 質結晶層。 ％ 圖3顯示可達成之高結晶品質生長晶體層厚度的關係，作 爲主晶與生長晶的晶格常數之間不匹配的函數。曲線4)古 結晶品質財料的界限。曲線42右方的區域代表愈來貪晶格 匹配的多晶體，因此能夠在主晶上生長無限厚度、高品^ 蟲晶層。由於晶格常數不匹配遞增，所以可達成、高。^ 結晶層的厚度迅速遞減。例如，作爲參考點，如果主#與 生長層間的晶格常數不匹配超過大約2%，則無法達成#、尚 大約20 nm的單晶磊晶層。 根據本發明一項具體實施例，基材22是以（1〇〇)或（lii 爲方向的單晶矽晶圓，而容納緩衝層24是鳃鋇欽酸骑層 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） f請先閱讀背面之注意事項再填寫本頁) 裝 ----訂------ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 494450 A7 ___B7 _ 五、發明說明（11) 達成這兩種材料之晶格常數實質上匹配的方式爲，將鈥酸 鹽材料晶體方向往相對於矽基材晶圓晶體方向45°旋轉。在 此範例中，非結晶中間層24結構中所包含的氧化矽層係用 來降低鈦酸鹽單晶層應變，因爲鈦酸鹽單晶層應變會導致 主矽晶圓與生長鈦酸鹽層的晶格常數不匹配。結果，根據 本發明一項具體實施例，可達成高品質、更厚的單晶層鈦 酸鹽層。 請重新參考圖1及2,層26是磊晶生長單晶組合物半導體 •材料層，並且該結晶材料的特徵在於晶格常數及晶體方向 。爲了達成高結晶品質的磊晶生長層，容納緩衝層必須具 有高結晶品質。此外，爲了達成高結晶品質的層26，希望 主晶（在此情況下，主晶是單晶容納緩衝層）與生長晶體的 晶格常數之間實質上匹配。配合正確選用的材料，由於生 長晶體的晶體方向會相對於主晶方向旋轉，所以可達成晶 格常數實質上匹配。如果生長晶體是砷化鎵、砷化鋁鎵、 鋅亞硒酸鹽或鋅硫亞硒酸鹽，而容納緩衝層是單晶 SrxBa^TiOs，則可達成這兩種材料的晶格常數實質上匹配 ，其中會將生長層的晶體方向往相對於主單晶氧化物方向 旋轉45。。同樣地，如果主晶材料是鳃或鋇錘酸鹽或鳃或鋇 铪或鋇錫氧化物，而組合物半導體層是磷化銦或砷化鎵銦 或砷化鋁銦，則可達成晶格常數實質上匹配，其方式是將 生長晶體層的方向往相對於主氧化物晶體方向旋轉45%在 某些情況中，主晶氧化物與生長組合物半導體層之間的結 晶半導體緩衝層可用來降低生長單晶組合物半導體層的應 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 訂--------- 經濟部智慧財產局員工消費合作社印製 494450 A7 B7 _ 五、發明說明（12) 變，因爲應變會導致晶格常數的微幅差異。藉此可達成最 佳的生長單晶組合物半導體層結晶品質。 下文説明根據本發明一項具體實施例之製造諸如圖1與2 所示之結構之半導體結構的方法。方法的開始步驟是提供 一種包括矽或鍺的單晶半導體基材。根據本發明較佳具體 實施例，半導體晶基材是具有（100)方向的矽晶圓。基材最 好是以軸線爲方向，最多偏離軸線大約0.5°。半導體基材 的至少一部分具有裸面，然而基材的其他部分可能圍繞著 其他結構，如下文所述。在此上下文中，術語「裸」表示 已清除基材的部分表面，以去除氧化物、致污物或其他異 質材料。眾所皆知，裸矽具有高度反應性，並且很容易形 成天然氧化物。術語「裸」包含此類的天然氧化物。還可 能故意在半導體基材上生長薄型氧化矽，然而此類的生長 氧化物不是根據本發明之方法的必要項。爲了磊晶生長單 晶氧化層以覆蓋單晶基材，必須先去除天然氧化層，以暴 露基礎基材的結晶結構。下列的方法最好是藉由分子束磊 晶生長（molecular beam epitaxy ; MBE)方法來實現。藉由 先在MBE裝置中熱沈積薄型鳃層，以去除天然氧化物。然 .後，將基材加熱到大約750°C，使鳃與天然矽氧化層產生化 學反應。鳃係用來分解氧化矽，而留下無氧化矽表面。所 產生的表面包括總、氧及碎，並呈現整齊的2x 1結構。整齊 的2 X 1結構形成模板，用以有序生長單晶氧化物的覆蓋層。 模板提供必要的化學及物理特性，以集結結晶生長的覆蓋 層。 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------. A7
(請先閱讀背面之注意事項再填寫本頁) 裝--------訂----
-n ϋ I I i. A7
494450 五、發明說明（14) 覆盖單晶總鈥故鹽，以促進後續生長所希望的組合物半導 體材料磊晶層。就後續生長砷化鎵層而言，覆蓋MBE生長 的鳃鈦酸鹽單晶層的方式爲，以1到2層單分子層鈦、1到2 層單分子層鈦-氧或1到2層單分子層锶-氧來終止生長。在 形成此覆蓋層後’接著沈積砷，以形成Ti_As键合、Ti_0_As 鍵合或Sr-O-As。這些的任一種都可形成適合沈積及形成砷 化鎵單晶層的模板。在形成模板後，接著導入鎵，以與坤 產生化學反應，並形成砷化鎵。或者，可在覆蓋層上沈積 鎵，以形成Sr-0-Ga鍵合，並且導入與鎵反應的砷，以形成 GaAs 〇 藉由如上文所述的方法並加上額外緩衝層沈積步驟，即 可形成如圖2所示的結構。在沈積單晶組合物半導體層之前 ’會先形成覆蓋模板層的緩衝層。如果緩衝層是組合物半 導體超晶格，則可在如上文所述的模板上藉由（例如）MBE 來沈積此類的超晶格。如果用鍺層來取代緩衝層，則會修 改上述的方法，以最後的鳃層或鈦層來覆蓋鳃鈦酸鹽單晶 •層，然後藉由沈積鍺，以利於與鳃或鈦產生化學反應。然 後，可在此模板上直接沈積鍺緩衝層。 如上文所述的方法説明一種藉由分子束磊晶生長方法來 形成半導體結構的方法，其中該半導體結構包含一矽基材 、一單晶锶鈦酸鹽容納緩衝層及一單晶坤化鍺組合物半導 體層。然而，還可能藉由化學蒸汽化澱積（chemical vapor deposition ; CVD)、金屬有機化學蒸汽澱積（metal 〇rganic chemical vapor deposition ; MOCVD)、遷移率增強型磊晶 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公爱） -----------41^^--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 494450 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（15) 生長（migration enhanced epitaxy ; MEE)、原子層羞晶生長 (atomic layer epitaxy ; ALE)等等來實現此項方法。另外， 藉由類似的方法，還可生長其他的單晶容納緩衝層，諸如 ，驗土金屬鈦酸鹽、鹼土金屬锆酸鹽、鹼土金屬給酸鹽、 鹼土金屬鈒酸鹽、鹼土金屬釩酸鹽、鹼土金屬釕酸鹽、鹼 土金屬說酸鹽、鹼土金屬錫基鈣鈦礦&1]^111^ earth metal tin-based perovskites)、鑭鋁酸鹽、氧化鑭銳及氧化釓。另 外’藉由諸如MBE的類似方法，還可沈積其他的第Η〗 —乂及 II-VI族單晶組合物半導體層，以覆蓋單晶氧化物容納緩衝 層0 組合物半導體材料與單晶氧化物容納緩衝層的每種變化 都是使用適當的模板層，以利於開始生長組合物半導體層 。例如，如果容納缓衝層是鹼土金屬锆酸鹽，則可藉由薄 型锆層來覆蓋氧化物。沈積錘之後，接著沈積要與锆產生 化學反應的坤或磷，作爲分別沈積神化錮鎵、绅化銦鋁或 磷化銦的前導。同樣地，如果單晶氧化物容納緩衝層是鹼 土金屬铪酸鹽’則可藉由薄型給層來覆蓋氧化層。沈積铪 之後，接著沈積要與給產生化學反應的砷或磷，作爲分別 生長砷化銦鎵、砷化銦鋁或磷化銦層的前導。在類似的方 法中，可用锶或鳃暨氧層來覆蓋锶鈦酸鹽，並且用鋇或鋇 暨氧層來覆蓋鋇鈦酸鹽。沈積前述各項之後，接著沈積要 與覆蓋材料產生化學反應的砷或磷，以形成用來沈積組合 物半導體材料層的模板，其中組合物半導體材料層包括绅 化銦鎵、砷化銦鋁或磷化銦層。 Μ,--------IT--------- (請先閱讀背面之注意事項再填寫本頁) -18- 494450 A7
經濟部智慧財產局員工消費合作社印製 示根據本發明進-步具體實施例之裝置結構50的 斷面圖。裝置結構50包括單晶半導體基材52，其最好是單 晶梦晶圓。單晶半導體基材52包括53及54兩個區域。虛線 56所指示的電子半導體組件通常是在區域53中形成。電子 組件56可能是電阻器、電容器、諸如二極體或電晶體之類 的王動式半導體組件，或者諸如互補金屬氧化物半導體 (CMOS)積體電路之類的積體電路。例如，電子半導體組件 56可能是CMOS積體電路，用來執行數位信號處理，或用來 執行相當適合矽積體電路的另一種功能。可藉由眾所皆知 且半導體產業中廣泛實施的傳統半導體處理來形成區域53 中的電子半導體組件。諸如二氧化矽層之類的隔離材料層 58可覆蓋電子半導體組件56。 區域54的表面上會移除半導體組件56處理期間在區域53 中形成或沈積的隔離材料58或任何其他層，以便在區域54 中提供裸矽表面。眾所皆知，裸矽表面具有高度反應性， 並且裸表面上可迅速形成天然氧化矽層。會在區域54表面 上的天然氧化物層上沈積鋇或鋇暨氧層，並且與氧化表面 產生化學反應，以形成第一模板層（圖中未顯示）。根據本 發明一項具體實施例，會藉由分子束磊晶生長方法來形成 單晶氧化物層60，以覆蓋模板層。在模板層上沈積包括鋇 、鈦暨氧的反應物，以形成單晶氧化物層。首先，於沈積 期間，將部分壓力之氧氣維持在接近與鋇及鈥完全反應所 須的最小限度，以形成早晶鎖敌酸鹽層60。然後，遞增部 分壓力之氧氣以提供氧氣過壓，並允許氧氣通常生長中的 -19- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Μ.--------IT--------- (請先閱讀背面之注意事項再填寫本頁) 494450 A7 ---~--~__ 五、發明說明（17) 單晶氧化物層擴散。通過锶鈦酸鹽層擴散的氧氣會與位於 區域54表面上的矽產生化學反應，用以在第二區域上形成 氧化梦非結晶層62，非結晶層62位於矽基材與單晶氧化物 .之間的界面。 根據本發明一項具體實施例，終止沈積單晶氧化物層60 的方式是沈積第二模板層64,該第二模板層64可能是1到10 層單分子層鈦、鋇、鋇暨氧或鈦暨氧。然後，藉由分子束 慕晶生長方法來沈積單晶組合物半導體材料層66，以覆蓋 第二模板層。沈積層66的第一步驟是在模板層上沈積砷層 。第一步驟之後，接著沈積鎵及砷，以形成單晶砷化鎵。 或者，在上面的範例中，可用鳃來取代鋇。 根據本發明進一步具體實施例，通常會在組合物半導體 層66上形成虛線68所指示的半導體組件。可藉由製造砷化 鎵或其他第III-V族組合物半導體材料裝置中使用的傳統處 •理步驟來形成半導體組件68。半導體組件68可能是任何的 主動型或被動型組件，並且最好是利用組合物半導體材料 物理特性的半導體雷射、發光二極體、光檢測器、異質結 雙極性電晶體（heterojunction bipolar transistor ; HBT)、高 頻MESFET或其他的組件。可形成線條70所指示的金屬導體 ，以利於電子耦合裝置68及裝置56，以此方式建置積體電 路，該積體電路包括至少矽基材中形成的一個組件及單晶 組合物半導體材料層中形成的一個裝置。雖然已説明之作 爲例證的結構50是在矽基材52上形成的結構，並且具有鋇（ 或鳃）鈦酸鹽層60及砷化鎵層66，但是可使用本發表中他處 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝—— 訂---------AW. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 494450 A7 B7 _ 五、發明說明（13) 所説明的其他基材、單晶氧化層及其他組合物半導體層來 製造類似的裝置。 圖5顯示根據本發明另一項具體實施例之半導體結構72 的圖式。結構72包括單晶半導體基材74，諸如包含區域75 及區域76的單晶矽晶圓。將使用半導體產業中常用的傳統 矽裝置處理技術，在區域75中形成虛線78所指示的電子組 件。使用類似於如上文所述的方法步驟，來形成單晶氧化 層80及中間非結晶氧化矽層82，以覆蓋基材74的區域76。 接著形成模板層84及其後的單晶半導體層86，以覆蓋單晶 氧化物層80。根據本發明進一步具體實施例，藉由類似於 形成層80的方法步驟來形成額外單晶氧化物層88，以覆蓋 層8 6，並且，藉由類似於形成層8 6的方法步骤來形成額外 單晶半導體層90，以覆蓋單晶氧化物層88。根據本發明一 項具體實施例，會從組合物半導體材料來形成層86及90的 至少其中一層。 通常會在單晶半導體層86的至少一部分上形成虛線92所 指示的半導體部分。根據本發明一項具體實施例，半導體 組件92可包含場效電晶體，在某種程度上，該場效電晶體 的閘電介質係由單晶氧化物層88所形。此外，可使用單晶 半導體層92來建置該場效電晶體的閘電極。根據本發明一 項具體實施例，會從第III-V族組合物來形成單晶半導體層 86，並且半導體組件92是利用第III-V族組合物材料物理特 性的射頻（RF)放大器。根據本發明更進一步具體實施例， 線條94所指示的電子交接以電子方式交接組件78及組件92 -21- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------^裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 494450 A7 B7 五、發明說明（19) 。以此方式，結構72集成利用兩種單晶半導體材料唯一特 {生的組件。 藉由更多的特定範例，圖6到18顯示其他的積體電路及系 統。圖6顯示用以説明通信裝置100之一部分的簡化方塊圖 ，該通信裝置100具有信號收發裝置101、積體電路102、輸 出單元103及輸入單元104。信號收發裝置的範例包括天線 、數據機或任何其他的裝置，這些裝置可用來將資訊或資 料傳送至或自外部裝置。在本文中，收發功能係用來表示 可能只能夠傳輸、只能夠接收或可接收暨傳輸信號至通信 裝置或來自於通信裝置之信號的信號收發裝置。輸出單元 103可包括顯示器、監視器、揚聲器等等。輸入單元104可 包括麥克風、键盤等等。請注意，在替代具體實施例中， 可用諸如記憶體等等的單一單元來取代輸出單元103及輸 _入單元104。記憶體可包括隨機存取記憶體或非揮發性記憶 體，諸如硬碟、快閃記憶卡或模組等等。 積體電路通常是連續基材上或内不能分離組合的至少兩 個電路元件（例如，電晶體、二極體、電阻器、電容器等等 )的組合。積體電路102包括組合物半導體部分1022、雙極 性部分1024及金屬氧化物半導體（1^08)部分1〇26。組合物 半導體部分1022包括組合物半導體材料内至少部分形成的 電子組件。組合物半導體部分10 2 2内的電晶體及其他電子 組件能夠處理至少大約0.8 GHz的射頻信號。在其他具體實 施例，信號可能是較低或較高的頻率。例如，在諸如砷化 銦鎵之類的某些材料能夠處理大約27 GHz的射頻信號。 -22- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------· 經濟部智慧財產局員工消費合作社印製 494450 A7 B7 _ 五、發明說明（20) 組合物半導體部分1022進一步包括雙工器10222、射頻轉 •基頻帶轉換器10224 (解調變裝置或解調變電路）、基頻帶轉 射頻轉換器10226 (調變裝置或調變電路）、功率放大器 10228及隔離體10229。雙極性部分1024及MOS部分1026通 常係以IV族半導體材料所形成。雙極性部分1024包括接收 放大器10242、類比到數位轉換器10244、數位到類比轉換 器10246及傳輸放大器10248。MOS部分1026包括數位信號 處理裝置10262。此類裝置的範例包括市場上通常可購買到 的 DSP核心，諸如 Motorola DSP 566xx (Motorola，Incorporated of Schaumburg，Illinois銷售）及 Texas Instruments TMS 320C54x (Texas Instruments of Dallas，Texas销售）系列數位信號處理 器。數位信號處理裝置10262通常包括互補金屬氧化物半導 •體（CMOS)電晶體及類比到數位暨數位到類比轉換器。顯然 地，積體電路102中會出現其他的電子組件。 在某一操作模式中，通信裝置100自天線接收信號，其中 天線屬於信號收發裝置10 1的一部分。信號通過雙工器 10227傳送到射頻轉基頻帶轉換器10224。類比資料或其他 資訊經過接收放大器10224放大後，即傳輸到數位信號處理 裝置10262。數位信號處理裝置10262處理資訊或其他資料 後，將經過處理的資訊或其他資料傳輸到輸出單元1〇3。如 果通信裝置是傳呼機，則輸出單元可能是顯示器。如果通 信裝置是行動電話，則輸出單元103可包含揚聲器、顯示器 或兩項皆有。 通信裝置100可將資料或其他資訊進相反方向傳送。資料 -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂—-------- (請先閱讀背面之注意事項再填寫本頁)
494450 五、發明說明（21) 或其他資訊將通過輸入單元104。在行動電話中，輸入單元 104可包括麥克風或键盤。然後，會使用數位信號處理裝置 10262來處理資訊或其他資料。經過處理後，然後使用數位 到類比轉換器1〇246來轉換信號。傳輸放大器1〇248負責放 大已轉換的信號。已放大的信號經過基頻帶轉射頻轉換器 10226調變後，由功率放大器10228負責進一步放大。已放 大的射頻信號通過隔離體1〇229及雙工器ι〇222傳送到天線 〇 通k裝置100的先前技藝具體實施例將具有至少兩個分 開的積體電路：其中-個是組合物半導體部分則，而另 -個是MOS部分1〇26。雙極性部分1〇24可能位於與M〇s部 分1〇26相同的積體電路上，或可能位於另-個積體電路上 。現在，運用本發明具體實施例，可在單一積體電路内形 成這三個部分。因爲所有的電晶體都可駐存於單一積體電 路上所以可大幅小型化通信裝置，纟且更方便攜信 裝置。 現在，將况明如圖7到工丄所示之一種用以形成示範性積體 電路102部分的方法。於圖7中，所提供的p型摻雜式單晶石夕 基材i 1 〇具有，组合物半導體部分i 〇 2 2、冑極性部分i 〇 2 4及 则邵分1G26。在雙極性部分内掺雜單晶碎基材，以形成 N埋置區域1102。然後’在埋置區域ιι〇2與基材η。上面形 成輕微p型摻雜式羞晶單晶⑦層i 1G4。然後，實行摻雜步驟 ，以便在N+埋置區域11〇2上產生輕微n型摻雜式漂移區⑴7 。接雜步縣雙極性區域觀部分内的輕微pM晶層的接 (請先閱讀背面之注意事項再填寫本頁) 裝 — — — — — — — — — . 經濟部智慧財產局員工消費合作社印製 -24- ^4450
經濟部智慧財產局員工消費合作社印製 4物類型轉換成輕微η型單晶矽區域。然後，在雙極性部分 1024與MOS部分1026間形成場隔離區域i 1〇6。在M〇s部分 i〇26内的磊晶層11〇4部分上形成閘電介質層i丨1〇，然後， 在閘電介質層liio上形成閘電極i〗12。沿著閘電極1112與 閘電介質層1 1 1 0的垂直面形成側壁間隔丨丨丨5。 將p型掺雜物導入漂移區域丨丨i 7，以形成活性或本質基極 區域1114。然後，在雙極性部分1〇24内形成11型、深層集電 極區域1108，以允許電子連接到埋置區域11〇2。實行可有 選擇性η型摻雜，以形成矿摻雜區域1116及發射極區域ιΐ2〇 。Ν +摻雜區域1116係在沿著閘電極1112鄰接側的層11〇4内 形成，並且是MOS電晶體的源極、汲極或源/汲極區域。Ν + 摻雜區域1116及發射極區域1120的摻雜濃度爲每立方公分 至少1Ε19個原子，以允許形成歐姆接觸點。形成ρ型摻雜區 域，以建亙Ρ +摻雜區域的非活性或非本質基極區域〗丨丨8 ( 掺雜濃度爲每立方公分至少1E19個原子）。 在所説明的具體實施例中，已實行數項處理步驟，但是 有一些步躁無圖解或進一步説明，諸如形成井區域、門限 調整植入、通道穿通阻植入、場穿通阻植入及各種遮罩層 。到目前爲止，方法中使用傳統步驟來形成裝置。如上文 所述，MOS區域1026内已形成標準N通道MOS電晶體，並 且雙極性部分1024内已形成垂直式NPN雙極性電晶體。到 目前爲止，組合物半導體部分1022内尚未形成任何電路元 件。 現在，從組合物半導體部分1022的表面移除於積體電路 -25- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 裝--------訂---------%· (請先閱讀背面之注音？事項再填寫本頁) 494450 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（23 ) <雙極性及MOS部分方法期間已形成的所有層。以此方式 提供裸矽表面，以利於進行部分的後續處理，例如，用: 上文所述的方法。 然後，在基材1 1 〇上形成容納緩衝層i 24，如圖8所示。所 形成的客納緩衝層將作爲部分i022中適當準備之裸矽表面 上的單晶層。然而，在部分1024及1026上形成的層124部分 可能是多晶體或非結晶，這是因爲這是在非單晶材料上形 成’因此’不會集結單晶生長所致。容納緩衝層1 24通常是 單晶氧化金屬或氮化金屬層，並且其厚度大約在2 nm到1〇〇 毫微米（nm)的範圍内。在一項特定具體實施例中，容納缓 衝層厚度大約是5到15 nm。於形成容納緩衝層期間，會沿 著積體電路102最上面的矽表面上形成非結晶中間層122。 非結晶中間層122通常包括氧化矽，並且其厚度大約是丨到5 nm。在一項特定具體實施例中，非結晶中間層厚度大約是 2 nm。在形成容納缓衝層124及非結晶中間層122後，然後 形成模板層126，模板層的厚度大約在材料的1到丨〇層單分 子層範圍内。在一項特定具體實施例中，材料包括鈦-砷、 銳-氧-坤，或是如上文參考圖1到5所述的其他類似材料。 然後，磊晶生長單晶組合物半導體材料層13 2，以覆蓋容 納緩衝層124的單晶部分，如圖9所示。在非單晶層124部分 上生長的層13 2部分可能是多晶體或非結晶。可藉由數種方 式來形成早晶組合物半導體層，並且通常包括諸如珅化嫁 、砷化銦鋁、磷化銦或如上文所述的其他組合物半導體材 料。層的厚度大約在1 nm到5，000 nm的範圍内，益且最好 •26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 494450 A7 _________B7 —__ 五、發明說明（24) "~^ ~ 是大、100 nm到500 nm的厚度。在此項特定具體實施例中 ，模板層内的每個元件也會出現在容納緩衝層124、單晶组 合物半導體材料132,或兩者中。因此，於處理期間，模板 2 126與其兩層緊鄰層之間輪廓消失。因此，當拍攝透射式 電子顯微鏡（transmission electr〇n micr〇sc〇py; TEM)照片 時，可能看到介於容納緩衝層124與單晶組合物半導體材料 層13 2間的界面。 此時，將移除位於覆蓋雙極性部分1〇24與％〇3部分1〇26 之部分的組合物半導體層132及容納緩衝層124的區段，如 •圖10所示。移除此區段後，接著在基材110上形成隔離層142 二隔離層142可包含一些材料，諸如，氧化物、氮化物、氮 氧化物、低k電介質等等。在本文中，低]^是具有低於大约 J.5電介質常數的材料。沈積隔離層142後，接著拋光、移 除覆蓋單晶组合物半導體層132的隔離層142部分。 然後，在單晶組合物半導體部分1〇22内形成電晶體144 。然後，在單晶組合物半導體層132内形成閘電極148。然 後，在單晶組合物半導體層132内形成摻雜區域146。在此 項具體實施例中，電晶體144，是金屬半導體場效電晶體 (meial_semiconductor field_effect transist〇r ; mesfet)。如 果MESFET是η型MESFET，則摻雜區域146及單晶組合物半 .導體層132也是η型摻雜式。如果要形成p型MESFET，則摻 4區域146及單晶組合物半導體層132是相反的掺雜型。重 接4 (N )區域14 6允终製作單晶組合物半導體層部分13 2的 歐姆接觸點。此類，已形成積體電路内的主動裝置。此項 •27- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝--------訂--------- 經濟部智慧財產局員工消費合作社印剩衣 經濟部智慧財產局員工消費合作社印製 494450 A7 __B7 _ 五、發明說明（25) 特定具體實施例包括η型MESFET、垂直式NPN雙極性電晶 體及平面Ν通道MOS電晶體。可使用許多其他類型的電晶 體，包括Ρ通道MOS電晶體、ρ型垂直式雙極性電晶體、ρ 型MESFET及垂直式暨平面電晶體的組合。再次，一個或一 個以上的部分1022、1024及1026中可形成其他的電子組件 ，諸如電阻器、電容器、二極體等等。 繼續處理，以形成實質上完整的積體電路102，如圖11 所示。在基材110上形成隔離層152。隔離層152可包括蝕刻 終止或拋光終止區域，圖11中未顯示。然後，在第一隔離 層152上形成第二隔離層154。移除層154、152、142、124 及122部分，以確定接觸點開孔的界限，用以交接裝置。在 隔離層154内形成交接溝槽，以提供接觸點間的橫向連接。 如圖11所示，交接1562將部分1022内的η型MESFET源極或 汲極區域連接到雙極性部分1024内之NPN電晶體的深層集 電極區域1108。將NPN電晶體的發射極區域1120連接到 MOS部分1026内之N通道MOS電晶體之摻雜區域1116的其 中一區。將其他的摻雜區域1116電子連接到圖中未顯示之 積體電路的其他部分。 在交接1562、1564暨1566及隔離層154上形成鈍化層156 •。製作如圖所示之電晶體的其他連接，並製作積體電路1〇2 内其他的電氣或電子組件，但圖中未顯示。另外，若需要 ，可形成額外隔離層及交接，以形成積體電路内各種組 件間的適當交接。
從前面的具體實施例可得知，可將組合物半導體及第IV '\ -28- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 494450 A7 B7 ___ 五、發明說明（26 ) 半導體材料的主動裝置集成到單一積體電路中。因爲在同 一積體電路内併入雙極性電晶體及MOS電晶體存在一些困 難，所以可將雙極性部分内的某些組件移到組合物半導體 部分1022或MOS部分1024中。具體而言，請重新參考圖6 所示的具體實施例，可將放大器10248及10242移到組合物 半導體部分1022中，而將轉換器10244及10246移到MOS部 分1026中。因此，需要特殊的製造步驟，以排除雙極性電 晶體。因此，積體電路内只有組合物半導體部分及MOS部 分。 在還有另一項具體實施例中，可形成一種積體電路，該 積體電路包含位於組合物半導體部分中的光雷射，以及光 交接（波導），以連接到同一積體電路之第IV族半導體區域 内的MOS部分。圖12到18顯示一項具體實施例的圖式。 圖12顯示包括單晶矽晶圓161之積體電路160—部分的斷 面圖。晶圓161上已形成非結晶中間層162及容納緩衝層164 ，類似於上文所述。在此項特定具體實施例中，會先形成 要形成光雷射所需的層，之後形成要形成MOS電晶體所需 的層。在圖12中，上半部鏡射層166包含組合物半導體材料 •的間隔層。例如，光雷射内的第一、第三及第五膜可包含 諸如砷化鎵之類的材料，而下半部鏡射層166内的第二、第 四及第六膜可包含砷化鋁鎵，反之亦然。層168包含用來產 生光子的活性區域。形成上半部鏡射層17〇的方法類似於形 成下半部鏡射層166的方法，並且包含組合物半導體材料的 間隔膜。在一項特定具體實施例中，上半部鏡射層170可能 -29- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- 494450 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（27) 是P型掺雜組合物半導體材料，而下半部鏡射層166可能是n 型摻雜組合物半導體材料。 在上半部鏡射層170上形成另—層容納缓衝層172，其類 似於容納緩衝層164。在一項替代具體實施例中，容納缓衝 層164及172可能包含不同的材料。然而，容納緩衝層164 及1 72的功能實質上相同，因爲都是用來製作組合物半導體 層與單晶第iv族半導體層間的轉換。在容納緩衝層172上形 成單晶第IV族半導體層174。在一項特定具體實施例中，單 晶第IV族半導體層i74包含鍺、矽鍺、碳化矽鍺等等。 在圖13中，將處理MOS部分，以形成位於此上半部單晶 第IV族半導體層174内的電子組件。如圖13所示，從層174 的部分形成場隔離區域171。層174上形成閘電介質層173 ，在閘電介質層173上形閘電極175。摻雜區域177是電晶體 181的源極、汲極或源/汲極區域，如圖所示。在鄰接閘電 極175的垂直面形成側壁間隔179。可在層174的至少一部分 内製作其他的組件。這些其他的組件包括其他的電晶體0 通道或p通道）、電容器、電晶體、二極體等等。 在摻雜區域177的其中一區上磊晶生長單晶第IV族半導 體1。上半部分184是P +摻雜，而下半部分182實質上維持 本質（未摻雜），如圖13所示。可使用選擇性磊晶方法式形 成咸層。在一項具體實施例中，在電晶體i 8丨及場隔離區域 17 1上形成隔離層（圖中未顯示）。製作隔離層的圖樣，以確 疋用來暴露摻雜區域177之其中一區的開孔界限。至少一開 士口先形成不含摻雜物的選擇性系晶層。整個選擇性系晶
ffl t @ s ^ (2i〇；^TST (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- A7
請 先 閱 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 訂
494450 A7 -—~_____ 五、發明說明（29) —' 材，202上形成硬遮罩層咖。移除覆蓋開孔到接近圖η倒 邊範圍之部分上的硬遮罩層204部分及較高折射率材料2〇2 〇 /几成作爲光交接之光波導形成的平衡，如圖17所示。執 仃沈積私序（可能是沈積·蝕刻方法），以有效建立側壁區段 .212。在此項具體實施例，製成側壁區段212所使用的材料 與材料202相同。然後，移除硬遮罩層2〇4，並在較高折射 率材料212及202上形成較低折射率材料214㈠目對於材料 202及層2 12的低折射率），並暴露隔離層19〇的部分。圖η 中的虛線描繪出較高折射率材料2 12及2〇2間的邊界。此項 命名疋用來識別以相同材料所製成，但在不同時間形成。 繼續處理，以形成實質上完整的積體電路，如圖18所示 。然後，在光雷射180及MOSFET電晶體181上形成鈍化層 220。雖然圖中未顯示，但是可在積體電路内製作其他的電 子或光學連接，而圖18中未顯示。這些連接可包括其他的 光波導或可包括金屬交接。 在其他具體實施例中，可形成其他類型的雷射。例如， 另一種雷射類型可放射水平光（光子），而不是放射垂直光 。如果放射水平光，則可在基材161内形成MOSFET電晶體 ’並將重新配置光波導，使雷射能夠適當耦合（光連接）到 電晶體。在一項特定具體實施例中，光波導可包括容納緩 衝層的至少一部分。可能使用其他的組態配置。 顯然地，這些具有組合物半導體部分及第IV族半導體部 分的積體電路具體實施例都是用來解説本發明具體實施例 -32- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) ----- (請先閱讀背面之注意事項再填寫本頁) -丨裝
----^ ------II 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（3〇) ’而不是用來限制本發明。尚有其他組合的多樣性及本發 :的其他具體實施例。例如，組合物半導體部分可包括發 一極光榀測斋、二極體等等，而第IV族半導體可包 括數位邏輯、《憶體陣列以及可在傳統積體電路上形 士的大4刀、、’σ構。ϋ由運用本發明的具體實施例，現在更 谷易口併適合用組合物半導體材料運作的裝置與適合用第 IV狹半導體材料運作的其他組件。如此可縮小裝置、降低 製造成本並增加良率及可靠度。 雖；、、：未説明，但疋在晶圓上只形成組合物半導體電子詛 件的過程巾，可使用單晶第IV族晶圓。在此方法中，晶圓 實質上是在i造用I覆蓋晶圓之單晶组合物半導體層内的 組合物半導體電子組件的期間所使用的「處理」晶圓。因 此，可在直徑至少約200毫米且可能是至少約3〇〇毫米之晶 圓上的第III-V或II-VI族半導體材料内形成電子組件。 藉由使用此類型基材，相當低價的「處理」晶圓克服组 合物半導體晶圓的易碎性質，其方式是將此類晶圓放置在 相對更耐用且容易製造的基礎材料上。因此，可形成一種 積體電路，以便能夠在組合物半導體材料内形成所有的電 子组件，尤其是所有的主動式電子组件，即使基材本可包 括第IV族半導體材料。與相對小型且更易碎、傳統的組合 物半導體晶圓相比，因爲能夠以更經濟且更容易的方式來 處理大型基材，所以可降低組合物半導體裝置的製造成本 0 於前面的説明書中，已參考特定具體實施例來説明本發 -33- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂-----— 經濟部智慧財產局員工消費合作社印製 494450 A7 --—-*- 五、發明說明（31) '" =。然而，熟知技藝人士應明白本發明的各種修改並且容 易修改，而+會脱離如下文中申料利範例所提供之本發 明的範田壽與精神。因此，説明書暨附圖應視爲解説，而^ 應視爲限制，並且所有此類的修改皆屬本發明範疇内。 已說明關於特定具體實施例的優勢、其他優點及問題解 決万案。但是，可導致任何優勢、優點及解決方案發生或 更顯著的優勢、優點、問題解決方案及任何元件不應被理 解爲任何或所有申請專利範例的關鍵、必要項或基本功能 或元件。本文中所使用的術語「包括」、「包含」或其任 何其他的變化都是用來涵蓋非專有内含項，使得包括元件 清單的方法、方法、物品或裝置不僅包括這些元件，而且 還包括未明確列出或此類方法、方法、物品或裝置原有的 其他元件。 f請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -34- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 、申請專利範 經濟部智慧財產局員工消費合作社印製 :種包含-積體電路的通信裝置，其中該積體電路包括 一容納緩衝層； 全、且a物半導體部分，以覆蓋該容納緩衝層，其中該 =合物半導體部分包括—選自由—放大器、-調變電路 解調變電路所組成之群組的特徵；以及 一第IV族半導體部分，其包含一耦合該特徵的數位邏 科°卩分。 2 申明專利範圍第1項之通信裝置，其中該組合物半導 體部分之晶體方向係相對於該容納緩衝層之晶體方向 旋轉45。。 3 •如申請專利範圍第2項之通信裝置，其中： 該積體電路進一步包括一單晶第IV族基材，該單晶第 1乂族基材位於該組合物半導體部分下；以及 該容納緩衝層之晶體方向係相對於該單晶第IV族基 材之晶體方向旋轉4 5。。 4·如申請專利範圍第3項之通信裝置，其中該容納緩衝層 及"亥組合物半導體部分之間的晶格不匹配不會大於約 2·〇% ’並且該組合物半導體部分的厚度至少約2〇 ^瓜。 5·如申請專利範圍第1項之通信裝置，其中該積體電路具 有一選自由下列所組成之群組的特徵： 該容納緩衝層之晶體方向係相對於該組合物半導體 部分之晶體方向旋轉45。；以及 该容納緩衝層殳該組合物半導體部分之間的晶格不 _ -35- 本紙張尺度適用中國國家標準（αίϋΓ規格（210 χ 297公爱 ·裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) ^4450 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 ‘申請專利範圍 匹配不會大於約2.0%，並且該組合物半導體部分的厚产 至少約20 nm。 又 6.如申請專利範圍第1項之通信裝置，其中該積體電路進 一步包括一單晶第IV族基材，該單晶第IV族基材位於該 單晶組合物半導體部分下，其中·· 該容納緩衝層之晶體方向係相對於該單晶第IV族基 材之晶體方向旋轉45。；以及 土 該容納緩衝層及該組合物半導體部分之間的晶格不 匹配不會大於約2·0%，並且該組合物半導體部分的厚度 至少約20 nm。 7·如申請專利範圍第i項之通信裝置，其中該容納緩衝層 及該組合物半導體部分之間的晶格不匹配不會大於約 2.0% ’並且該組合物半導體部分的厚度至少約2〇 。 8· —種通信裝置，包括·· 一信號收發裝置； 一積體電路，包括： 一組合物半導體部分，其具有一耦合到該信號收發裝 置的放大器； 一第IV族半導體部分，其具有一耦合到該放大器的數 位信號處理裝置；以及 一耦合到該積體電路的單元。 9.如申叫專利範圍第8項之通信裝置，其中該通信裝置包 括一行動電話。 10·如申印專利範圍第8項之通信裝置，其中該通信裝置為 ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁}
    297公釐） §88
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KR100695662B1 (ko) 2007-03-19
US6392257B1 (en) 2002-05-21
CA2399394A1 (en) 2001-08-16
TW483050B (en) 2002-04-11
AU2001234972A1 (en) 2001-08-20
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AU2001234993A1 (en) 2001-08-20
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AU2001236820A1 (en) 2001-08-20
CN1416590A (zh) 2003-05-07
KR20020091089A (ko) 2002-12-05
EP1258031A1 (en) 2002-11-20
AU2001236895A1 (en) 2001-08-20
KR20020077907A (ko) 2002-10-14
WO2001059814A3 (en) 2002-04-18
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US20020047143A1 (en) 2002-04-25
AU2001238137A1 (en) 2001-08-20
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US7067856B2 (en) 2006-06-27
TWI301292B (en) 2008-09-21
KR20020075403A (ko) 2002-10-04
WO2001059836A1 (en) 2001-08-16
CN1398429A (zh) 2003-02-19
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CN1261978C (zh) 2006-06-28
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US20040149203A1 (en) 2004-08-05
CN1398430A (zh) 2003-02-19
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US20040150076A1 (en) 2004-08-05
CN1222032C (zh) 2005-10-05
KR20020077678A (ko) 2002-10-12
TW497152B (en) 2002-08-01
JP2003523084A (ja) 2003-07-29
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CN1416591A (zh) 2003-05-07
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US20020047123A1 (en) 2002-04-25
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