JPH01289108A - ヘテロエピタキシャル成長方法 - Google Patents

ヘテロエピタキシャル成長方法

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Publication number
JPH01289108A
JPH01289108A JP63118224A JP11822488A JPH01289108A JP H01289108 A JPH01289108 A JP H01289108A JP 63118224 A JP63118224 A JP 63118224A JP 11822488 A JP11822488 A JP 11822488A JP H01289108 A JPH01289108 A JP H01289108A
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Japan
Prior art keywords
compound semiconductor
gaas
temperature
layer
amorphous
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JP63118224A
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English (en)
Inventor
Kanetake Takasaki
高崎　金剛
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Fujitsu Ltd
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Fujitsu Ltd
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Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63118224A priority Critical patent/JPH01289108A/ja
Priority to US07/346,455 priority patent/US5019529A/en
Priority to DE68917021T priority patent/DE68917021T2/de
Priority to EP89304953A priority patent/EP0342937B1/en
Priority to KR1019890006558A priority patent/KR920008121B1/ko
Publication of JPH01289108A publication Critical patent/JPH01289108A/ja
Pending legal-status Critical Current

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概　要〕 ヘテロエピタキシャル成長方法に係り、特に例えばＳｉ
基板上にｍ−ｖ族化合物半導体（ＧａＡｓ等）結晶薄膜
を成長させる方法に関し、 Ｓｉ基板上にＧａＡｓ等のｍ−ｖ族化合物半導体を成長
させる際にヘテロ界面のストレスを減少させ、反りの少
ないウェハを得るヘテロエピタキシャル成長方法を提供
することを目的とし、 シリコン基板（１）上にｎｕ−Ｖ族化合物半導体をヘテ
ロエピタキシャル成長させる方法において、（イ）該シ
リコン基板（１）上に第１の非晶質ｍ−■族化合物半導
体層（２）を形成する工程、（ロ）該非晶質ｍ−ｖ族化
合物半導体層（２）上にｍ−ｖ族化合物半導体結晶層（
３）を形成する工程、 （ハ）該ｍ−ｖ族化合物半導体結晶層（３）上に所定の
厚さに第２の非晶質ｍ−ｖ族化合物半導体Ｎ（４）を形
成する工程、 （ニ）該第２の非晶質ｍ−ｖ族化合物半導体層（４）を
前記ｍ−ｖ族化合物半導体結晶層形成温度以下の温度で
固相エピタキシャル成長させ該第２の非晶質ｍ−ｖ族化
合物半導体Ｈ（４）を単結晶層に変化せしめる工程を含
んでなることを構成とする。
〔産業上の利用分野〕
本発明はへテロエピタキシャル成長方法に係り、特に例
えばＳｉ基板上にｍ−ｖ族化合物半導体（ＧａＡｓ等）
結晶薄膜を成長させる方法に関する。
〔従来の技術〕
従来Ｓｉ基板上にＧａＡｓ等のｍ−ｖ族化合物半導体結
晶薄膜をヘテロエピタキシャル成長はＭＯＣＶＤ法（有
機金属化学的気相成長法）あるいはＭＢＥ法で行なわれ
る。
Ｓｉ基板とＧａＡｓとは結晶格子定数において約４％（
Ｓｔ：５．４３人、　ＧａＡｓ　：　５．６５人）と異
なり、又熱膨張係数も大きく異なる（　Ｓ　ｉ：　２．
６　Ｘ　１０−”Ｃ−’。
ＧａＡｓ　：　５．９　Ｘｌ０−”Ｃ−’）ためにＳｉ
基板上にＧａＡｓを上記ＭＯＣＶＤ法を用いて成長した
場合ポリクリスタル（多結晶）状に成長してしまう。そ
こでシリコン基板上に約４５０℃の温度でアモルファス
（非晶質）状のＧａＡｓを１００〜２００人の厚さに成
長しアモルファスＧａＡｓ層２を形成した後、７００〜
７５０℃の温度で結晶賞状のＧａＡｓを３〜５Ｉ！ｍの
厚さに成長してＧａＡｓ結晶層を形成する２段階ＧａＡ
ｓ成長方法によって、格子定数のミスマツチをＳｉ　／
ＧａＡｓ界面に発生する欠陥によってＧａＡｓ単結晶薄
膜を得ていた。
〔発明が解決しようとする課題〕
上記２段階成長方法によってＳｉ基板上にＧａＡｓ成長
させてもＳｉ　とＧａＡｓとの熱膨張係数の差により、
ＧａＡｓ成長後基板を室温に戻した際、基板は第５図に
示すように成長したＧａＡｓ表面を凹にして大きく反り
、３Ｉ！ｍ以上の厚さにＧａＡｓが成長した際、Ｉ　Ｘ
１０’ｄｙｎ／ｃｄ以上の強い引張性のストレスが発生
ずる＊　３ｔｎａより以上の厚さに成長させたり、その
後の熱処理の際に格子欠陥（転位）が発生し、クラック
１０を生じるためにＳｉ基板上のＧａＡｓ層の形成は実
用化がなされていない。第５図においてｌはシリコン基
板、２は非晶質ＧａＡｓＪ！ｉ、　３はＧａＡｓ結晶層
である。
本発明は例えばＳｉ基板上にＧａＡｓ等のｍ−ｖ族化合
物半導体を成長させる際にヘテロ界面のストレスを減少
させ、反りの少ないウェハを得るヘテロエピタキシャル
成長方法を提供することを目的とする。
〔課題を解決するための手段〕
上記課題は本発明によればシリコン基板上（１）にＩＩ
Ｉ−Ｖ族化合物半導体をヘテロエピタキシャル成長させ
る方法において、 （イ）該シリコン基板（１）上に第１の非晶質■−■族
化合物半導体Ｎ（２）を形成する工程、（ロ）該非晶質
ｍ−ｖ族化合物半導体層（２）上にｍ−ｖ族化合物半導
体結晶層（３）を形成する工程、 （ハ）２１ｍ−ｖ族化合物半導体結晶層（３）上に所定
の厚さに第２の非晶ｚｍ−ｖ族化合物半導体Ｎ（４）を
形成する工程、 （ニ）該第２の非晶質ｍ−ｖ族化合物半導体層（４）を
前記ｍ−ｖ族化合物半厚体結晶層形成温度以下の温度で
固相エピタキシャル成長させ該第２の非晶質ｍ−ｖ族化
合物半導体層（４）を単結晶層に変化せしめる工程を含
んでなるヘテロエピタキシャル成長方法によって解決さ
れる。
〔作　用〕
本発明によれば非晶質ｍ−ｖ族半導体層を形成した後に
結晶成長温度以下の温度で固相エピタキシャル成長を行
なうのでウェハの反り、ストレス量が緩和される。
〔実施例〕
以下本発明の実施例を図面に基づいて説明する。
第１Ａ図から第１Ｄ図は本発明の１実施例を示す工程断
面図である。
まず第１Ａ図に示すように、２インチのＳｔ基板１上に
ＭＯＣＶＤ法を用いて従来同様に４５０℃の温度で１０
０〜２００人の厚さに第１の非晶質（アモルファス）　
ＧａＡｓＮ　２を形成する。
次に第１Ｂ図に示すように７００〜７５０℃の温度で１
０００〜２０００人の厚さにＧａＡｓ結晶Ｎ３を形成す
る。
次に第１Ｃ図に示すように再び４５０℃の温度で約３〜
５μの厚さに第２の非晶質（アモルファス）ＧａＡｓ結
晶層を形成する。
上記ＭＯＣＶＤ法による成長条件は、常圧で使用ガスを
Ａｓｌ＋２．４５０ｃｃ／分、トリメチルガリウム（Ｔ
ＭＧ）　１５　ｃｃ／分、Ｈ２ＩＯ１７分とし高周波加
熱とした。
第２図に本実施例で使用したＭＯＣＶＤ装置の反応主要
部概略図を示す。
第２図ではＭＯＣＶＤ反応容器５内に設けたカーボンサ
セプター６上にＳｉ基板（ウェハ）１が設けられており
、加熱用コイル７で加熱される。
第１Ｃ図で説明した第２のアモルファスＧａＡｓＮ４を
形成した後、ＧａＡｓ結晶層３を成長させた７００〜７
５０℃の温度よりも低い温度（約５００〜６５０℃）で
、ＡＳＨａ　１００ｃｃ／分及び１１／分のＨ２雰囲気
中でアニールし上記ＧａＡｓ結晶層３から固相エピタキ
シャル成長がなされ第１Ｄ図に示すようにアモルファス
ＧａＡｓ層４の下部はアモルファス状から結晶状に変化
せしめられる。その結果ウェハの反りは従来の６０１℃
ｍから２０−程度に改善された。またＧａＡｓ中のスト
レスは第３図に示すように固相エピタキシャル成長温度
６５０℃以下の場合引張性応力がＩ　ＸｌＯ”ｄｙｎ／
−と低い値が得られている。
また第４図には本発明に係る固相エピタキシャル成長速
度を示すグラフであり、５００℃未満の温度では固相エ
ピタキシャル成長速度が急に低下する。
本発明の実施例ではＭＯＣＶＤ法によりＧａＡｓをＳｉ
基板上に成長させる方法を説明したがＭＢ２法でも同様
に使用可能であり、しかもＧａＡｓ成長のみならず、他
のｍ−ｖ族生導体化合物例えばＧａｐ　　。
ＧａＡｓｘ　ＰＩ−１１＋　Ｉｎｘ　Ｇａｐ−、Ａｓ　
、　Ｉｎ、　Ｇａ、−、Ａｓｘ　Ｐ、−ＸあるいはＩｎ
Ｐについても実施される。
〔発明の効果〕
以上説明したように本発明によれば例えばＳｉ基板上に
ＧａＡｓ等のへテロエピタキシャル成長において得られ
たウェハは反り、ストレスが緩和され半導体デバイスの
電気的特性、特にＭＥＳ　ＦＥＴのスレッシュオールド
電圧（Ｖｔｈ）のシフト防止等に良好な効果をもたらす
。
【図面の簡単な説明】
第１Ａ図から第１Ｄ図は本発明の１実施例を示す工程断
面図であり、 第２図は本実施例で使用したＭＯＣＶＤ装置の反応主要
部概略図を示し、 第３図にＧａＡｓ中のストレス（引張性応力）と固相エ
ピタキシャル成長温度との関係を示すグラフであり、 第４図は固相エピタキシャル成長速度を固相エピタキシ
ャル成長温度（４５０°〜７００℃）で測定した結果を
示すグラフであり、 第５図は従来例を説明するための断面図である。 １・・・シリコン（Ｓ　ｉ）基板、 ２・・・非晶質ＧａＡｓｊｉ、　３−ＧａＡｓ結晶層、
４・・・非晶質ＧａＡｓ層、　４ａ・・・ＧａＡｓ結晶
層、６・・・カーボンサセプタ、 ７・・・加熱用コイル。

Claims (1)

  1. 【特許請求の範囲】 １、シリコン基板（１）上にIII−Ｖ族化合物半導体を
    ヘテロエピタキシャル成長させる方法において、 （イ）該シリコン基板（１）上に第１の非晶質III−Ｖ
    族化合物半導体層（２）を形成する工程、（ロ）該非晶
    質III−Ｖ族化合物半導体層（２）上にIII−Ｖ族化合物
    半導体結晶層（３）を形成する工程、 （ハ）該III−Ｖ族化合物半導体結晶層（３）上に所定
    の厚さに第２の非晶質III−Ｖ族化合物半導体層（４）
    を形成する工程、 （ニ）該第２の非晶質III−Ｖ族化合物半導体層（４）
    を前記III−Ｖ族化合物半導体結晶層形成温度以下の温
    度で固相エピタキシャル成長させ該第２の非晶質III−
    Ｖ族化合物半導体層（４）を単結晶層に変化せしめる工
    程 を含んでなることを特徴とするヘテロエピタキシャル成
    長方法。
JP63118224A 1988-05-17 1988-05-17 ヘテロエピタキシャル成長方法 Pending JPH01289108A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP63118224A JPH01289108A (ja) 1988-05-17 1988-05-17 ヘテロエピタキシャル成長方法
US07/346,455 US5019529A (en) 1988-05-17 1989-05-02 Heteroepitaxial growth method
DE68917021T DE68917021T2 (de) 1988-05-17 1989-05-16 Herstellung eines Halbleiterplättchens, das eine III-V-Gruppen-Halbleiterverbindungsschicht auf einem Siliziumsubstrat aufweist.
EP89304953A EP0342937B1 (en) 1988-05-17 1989-05-16 Manufacturing a semiconductor wafer having a III-V group semiconductor compound layer on a silicon substrate
KR1019890006558A KR920008121B1 (ko) 1988-05-17 1989-05-17 헤테로 에피택셜 성장법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63118224A JPH01289108A (ja) 1988-05-17 1988-05-17 ヘテロエピタキシャル成長方法

Publications (1)

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JPH01289108A true JPH01289108A (ja) 1989-11-21

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US (1) US5019529A (ja)
EP (1) EP0342937B1 (ja)
JP (1) JPH01289108A (ja)
KR (1) KR920008121B1 (ja)
DE (1) DE68917021T2 (ja)

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Also Published As

Publication number Publication date
EP0342937A1 (en) 1989-11-23
US5019529A (en) 1991-05-28
DE68917021T2 (de) 1994-11-17
EP0342937B1 (en) 1994-07-27
KR920008121B1 (ko) 1992-09-22
KR900019143A (ko) 1990-12-24
DE68917021D1 (de) 1994-09-01

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