TW437044B - Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity - Google Patents

Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity Download PDF

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TW437044B
TW437044B TW087108346A TW87108346A TW437044B TW 437044 B TW437044 B TW 437044B TW 087108346 A TW087108346 A TW 087108346A TW 87108346 A TW87108346 A TW 87108346A TW 437044 B TW437044 B TW 437044B
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layer
copper
pattern
deposited
intermetallic
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TW087108346A
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Hazara S Rathore
Hormazdyar M Dalal
Paul S Mclaughlin
Du Binh Nguyen
Richard G Smith
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Ibm
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Priority claimed from US08/866,777 external-priority patent/US6130161A/en
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Publication of TW437044B publication Critical patent/TW437044B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76858After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76867Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

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Γ' 437U4 4 Α7 ____________Β7 五、發明説明(1 ) 發明背景 本專利申請案爲美國專利申請案序號08/866,777之部份連 續案,該申請案之標題爲"具有提高電子遷移抗性及減低 缺陷感度之銅互連體及其形成方法”,於1997年5月30 EJ提 出申請。 1. 發明範園 本發明係關於半導體製造之領蠄,更明確言之,係關於 銅爲基材之互連體在次微米尺寸上之設計,其對於腐飯與 缺陷具有減低之感度’於是具有經改良之可靠性。本發明 亦關於提供用以形成所設計結構之方法^ 2. 相關技藝之描述 由於對超大沒積電路裝置之幾何形狀持續按_比例下降 ’故對於具有最小間距與咼導電率之互連線路,及對於具 有低介電常數之鈍化材料,有漸增之需求,同時需要比以 前更強效之可靠性。特別是在次四分之一微米線條宽度之 體系中,最重要之因素係爲高導電率與高電子遷移抗性。 經濟部中央標準局員工消費合作社印製 、:.}裝------訂 (請先聞讀背面之注項再填寫本頁) 一項研究途径係使用銅冶金材料,因其具有高導電率與 高電子遷移抗性’且伴隨著聚酸亞胺純化層,以提供低交 又電容。一種利用此研究途徑之方法,係由Luther等人揭帝 於VLSI多階互連會議(VMIC),第15-21頁,1993中。其他製程改 良係使用雙浊絞方法,以同時形成銅互遠線條與階層間通 孔銷釘,其係由Dalai等人陳述於美國專利\434,451中,與本 申請案共同讓受人。波紋方法係涉及充填狹窄壕溝或狹窄 孔洞或兩者之組合。此項技藝中習知,使用妝理蒸氣沈積 -4- 本紙張尺度適用中國國家標準(CNS ) A4規格(2IOX29?公芨) 4 3 7 0 4 4 Α7 Β7 2 五、發明説明( (PVD)方法’譬如濺射或蒸發,以充填此種狹窄孔洞與壕溝 是不適當的,因爲會形成經充填金屬線條或銷釘之高度推 拔狀橫截面。Joshi等人在美國專利5,300,813中,亦與本申$ 案共同讓受人’陳述使用PVD方法以沈讀篇—導電奉凌屬, 接著爲鎮罩..蓋層之化學蒸氣沈積(CVD),以充填該推拔狀 横截面之頂部部份。此封端程序會造成銅導體截面面積之 «员上降低’此係由於这推拔狀横截面所致。亦由於封端 金屬係伴隨著導體金屬沈積,故導體金屬之狹縫係沿著所 完成產物之導體邊緣外露。再者,於此封端程序之化學-機械拋光步驟期間,藉抛光移除之堅硬金屬粒子,會有磨 損金屬線條之傾向。因此’順應性沈積方法,譬如C VD或 電艘,係爲銅沈積所需要的。 但是’已發現CVD銅遭遇到所需要高度複雜先質之有限 貯架壽命之困難。關於CVD銅之—項更嚴重問題,係爲藉 銅先質之蒸氣製造線條之污染.,其會使半導體裝置中毒。 藉由.電鍍之銅沈積,已被使用於印刷電路板(PCB)達數十 年。由於電鍍之低成本、低沈積溫度及其順應地塗覆狹窄 間隙之能力’故其係爲在銅互連體上沈積之較佳方法。應 明瞭的是,銅之電鍍需要銅晶種層在基材上。PVD方法已 經常被用以沈積銅,以提供晶―種層。但是,已發現PVD沈 積之銅,當與電鍍鋼比較時,具有十倍較低之電子遷移抗 性,及當與CVD銅比較時,具有三倍較低之電子遷移抗性 。由於銅晶種層可構成互連線條橫截面面積之高達20% ’ 故此晶種層會嚴重地妨礙銅互連體之電子遷移特性。雖然 -5 - Γ- | ^.'.裳 訂 (請先閲讀背面之注意事項再填窝本頁) 經濟部中央標準局員工消費合作社印製 ! ' 4370 44 A7 B7 五、發明説明(3 ) 銅之電子遷移抗性係足夠高,以承受在正常設計導體線條 中之耗損,但已在PVD晶種層/電鍍銅導體線條中發現缺 陷所引致之電子遷移故障。由於銅之高導電率,故線條缺 陷,譬如導體線條寬度或厚度,當變薄降至數百埃時,能 夠未被發現地通過電篩選試驗。可暸解在此等區域中之電 流密度,在實際使用期間係相當地高,由於電子遷移,於 是造成早期場失效。 當互連線條爲次四分之一微米尺寸時,在使用PVD方法 以提供晶種層時,發生另一個主要問題°此處即使是藉 PVD技術沈積之薄晶種層,亦會相當大地使間隙變窄,如 上述。這會造成中空殼層線條。 CVD銅沈積技術呈現問題,例如藉銅先質之蒸氣製造線 條之污染,於是使半導體裝置中毒。CVD沈積銅之厚度愈 .大,則線條ί亏染傾向愈大。 不同元素奥銅共沈積,以供高溫應用或用以改良機械強 度,係由Thomas於美國專利5,414:301 ;由Shapiro等人於美國 專利七007,039 ;由Akutsu等人於美國專利4,872,〇48 ;及由 Woodford與Bricknell於美國專利4,406,858中陳述。但是,當銅 經濟部中央標準局J工消費合作社印製 ^^^1· B^i^i nn -1·一,^^^^1 一'·> - - -i T - (請先閱請背面之注意事項再填寫各頁) 與另一種元素共沈積時,電阻率增加,其會抗拒使 用銅在南性能系統中之興正目的。 在銅冶金學上之又另一個可靠性顧慮係爲腐银性。此係 藉助於圖1與la之圖解,描述於下文。圖1爲上述先前技藝 之互連體系之部份結構,説明金屬互連體之兩個階層,各 階層係由雙波紋方法所界定圖la爲互連體橫截面之放大 -6- 本紙張尺度適用令國國家榇準(CNS ) Λ4規格(210X297公釐) 437044 A7 B7 五、發明説明(4 ) )ί ^ 視圖;其中在一階層上之銅互連線條9,經顯示係經過通 孔銷釘11 ’與下方階層之金屬互連線條1〇2接觸。應明瞭 的是’在雙波紋方法中,通孔銷針11與導體線條1〇2係爲 彼此之完整部份。銅互連體係包含黏著層5,選用障壁層6 ;PVD銅晶種層8 ;整體銅層9與11,及無機絕緣體4在聚 醯亞胺絕緣體3之頂上。 已發現銅線條之腐韻,通常係择随著使用聚醯空胺作爲 層間絕緣體而發生。這是因爲無論何時使用聚醯亞胺作爲 層間絕緣體’其施用經常涉及添加無機絕緣體薄層4。添 加此無機絕緣體薄層,係爲充作敬剠止動層,如在頒予 Chow等人之美國專利4,789,648中所陳述者,或爲降低聚酸 亞胺碎屑在化學-機械抛光期間形成,如由joshi等人在美國 專利5,4〇3,779中所陳述者(兩專利均歸屬於本發明之讓受人) 。此無機絕緣體層4之有害作用,係爲妨礙聚酿亞胺薄膜 中之殘餘水分之逃逸。因此’路氣壓會蓄積在聚酿亞胺薄 膜中’其會找到通往銅之路徑。結果,形成銅之氧化物與 氫氧化物。隨著時間與溫度,此等氧化物與氫氧化物最後 會造成空隙I3 (圖1)在銅導體中形成。此等腐蝕所引致之 空隙I3,咸認會從銅導體之頂部表面?丨發,其原因有二。 其一,内襯層5與6係覆蓋導體線條之底部與侧面,而非頂 部表面。其次,無機絕緣體層4與在導體線條侧壁上之内 觀5與6間之接面’在處理溫度漂移期間變成分離,於是提 供水份與銅接觸之路徑。Joshi等人之美國專利5,426,33〇,歸 屬於本發明之讓受人,陳述一種提供鎢覃蓋在銅導體之顶 本紙張尺度適用中國國家標準(CMS ) A4規格(210X297公釐)
-m. I 1 n —i n tl· ^ n 1 (請先閱讀背面之注意事項再填寫本頁J -訂_ 經濟部中央標準局貝工消費合作社印裝 4370 4 4 A7 B7 五、發明説明(5 ) ./ 〆 上以防方法。如前文所討論者,此封端方法會 在抛光期間形成不期望之金屬碎屑,造成金屬線條磨損。 因此,儘管再二努力,及在先前技藝中之各種體系,但 由於對缺陷敏感之電子遷移故障與腐蝕所致 < 製造問題仍 然存在。必須發展用以製造具有經改良可靠性與減低缺陷 感度之銅積體電路圖樣之較佳方法。 將先前技藝之問題與缺失牢記在心,因此本發明之一項 目的係爲提供一種製造具有經改良製程良率與可靠性之次 半微米尺寸之高性能互連電路系統之方法。 本發明之另一項目的,係爲提供一種具有低介電常數聚 醯亞胺鈍化層之高導電率銅爲基材之冶金材料。 本發明之又另一項目的,係爲減低銅互連冶金材料之缺 陷感度,其方式是改良其電子遷移抗性。 本發明之又再另一項目的,係爲提供具有減低;PVX)銅晶 種層厚度之電鍍銅互連線條,以改良互連線條之電子遠移 抗性。 本發明之另一項目的,係爲提供一種金屬封端之銅線條 之方法,其不會影嚮金屬線條完整性。 經濟部中央標準局員工消費合作社印製 ϋ裝------訂 (請先閱讀背面之注意事項再填寫本頁) 發明摘述 上述及其他目的,對於熟諳此藝者而言係爲顯而易見的 ,其係在本發明中達成,其係關於一種在基材上提供具有 經改良電子遷移與腐蚀抗性之次半微米銅互連體之方法。 此方法可包括使用電鍍铜之雙政紋方法,其中係採用減低 厚度之PVD層,或其中-PVD層係被cVD銅晶種層之順應性 -8- ______ 本紙張尺度適用中國國家標华(CNS ) A4规格(2[〇〆297公瘦) 經濟部中央標準局員工消費合作社印製 4370 44 Α7 Β7 五、發明説明(6 ) r ‘·, β層取代,此塗層比PVD沈積銅具有約三倍較高之電子遷 移抗性。於本發明中,晶種層亦可轉化成金屬間屉。銅金 屬間層’譬如給、鑭、锆、錫及鈦,係經提供以改良電子 遷移抗性,及減低缺陷感度。亦提供一種方法以形成罩蓋 ,其係完全覆蓋基材中形成之銅線條頂部上之表面,以改 良腐蝕抗性。亦描述結構與方法,經由在銅間隙位置摻入 碳原子,以改良電子遷移與腐蝕抗性。 一方面,本發明係包括一種形成藉由介電絕緣體互相隔 離之銅線條之多階互連體,以造成對基材中之電特徵接觸 之方法。此方法包括之步驟爲,首先製備具有介電絕緣層 之基材’以在經界定之圖樣中接收鋼線條,及視情況在該 圖樣中沈積貪屬。接著,在該圖樣中沈積一層減低厚 麿之PVO銅,一層CVD銅或一層能夠與銅形成金屬間化合 物之无素’接著爲一成多層銅。在沈積可形成金屬間層之 元素之情況中,係接著將某材加埶,以使可形成金屬間層 之元素與銅層反應,以形成一暦合屬、間化合物_在銅層中。 此可形成金屬間層之元素,較隹係選自包括铪、鑭、鈦、 錫及锆。此可形成金屬間之元素之層可在銅層之前沈積, 或銅層可在形成金屬間之元素之前沈積。亦可在銅層之前 沈積該可形成金屬間之元素層,並可在銅層之後,沈積另 一個可形成金屬間之元素層。 金屬内襯、可形成金屬間元素之層及銅層,可藉共同或 個別涔積技術沈積,選自包括趟射、蓋發及CVD。金屬内 襯、可形成金屬間元素之層及銅層,較佳係藉逾射,以單 -9- 本紙張尺度適用中國國家標準(CNS > Α4現格(2〗〇Χ297公釐) c請先閎靖背面之注意事項异填窝本頁) •裝_ 訂_ 4370 4 4 A7 B7 玉、發明説明( 次抽氣降壓,在原位沈 ^ ^ 積其中趣射可爲反應性濺射、準 直-臭射、磁控管濺射、隈 ------1----ί-)裝------訂 (請先閲绩背面之注意事項再填寫本頁) 货甘化7 / 低&濺射、ECR濺射、離子束濺射 及其任何组合。 〜 在一更佳方法中,本發明 +々 贫Λ係關於—種形成銅線條之可作 賴多階互連體之方法,在 °
HiIr ^ , 在入被未間距下,並藉低介電絕緣 也互相隔離,以造成對美姑中+ μ 基材中%特徵之接觸。此方法包捂 之步驟爲,首先在具有I特徽泛其从^ 4狩徵(基材上沈積一對絕綾層, 在至少一個絕緣層上以弁 a元石即万式界足通孔銷釘圖樣,部 份蝕刻該對絕緣層,在至少一 , 主y 個知緣層上以光石印方式界 定互連線條圖樣,及蚀刻絕緣層直到電特徵外露爲止;於 是在該對1«中形成㈣與孔洞。接著,在♦溝與孔洞 中沈積料。沈積能夠與铜形成金11 化—全她之 -素層,以及-或多層自,以充填孔洞與壕溝。將銅抛光 以移除壕溝外側之過量金屬,並將基材加熱以使可形成金 屬間I 7G素與鋼反應,以形成金屬間化合物與銅之層。 經濟部中央橾準局貝工消资合作社印裝 -銅屉之一可藉由銅與含碳氣體之展應性積,以在 經沈積銅之晶格中摻入碳原子。可形成金屬間層之元素, 其厚度較佳係在約100埃與600埃之間。金屬間層可在孔洞 與壕溝中之銅下方,在孔洞與壕溝中之銅内部,或在孔洞 與壕溝中之銅上方形成。 在一相關方面,本發明係提供一種具有鋼線條互連體之 基材,其包含一對絕緣層,經配置在具有電特徵之基材上 ’此絕緣層具有經蚀刻之通孔銷針圖樣,及經触刻之互速 線條圖樣’在該對絕緣體中形成孔洞與壕溝。一金屬層係 -10 - 本紙張尺度適用中國國家揉準{ CNS ) A4規格(210 X 297公釐) 經濟部中央標準局員工消費合作社印製 Λ3Ί〇ά 4 Α7 --——__ Β7 五、發明说明(8 ) 作爲壕溝與孔洞之内襯,並以銅充填孔洞與壕溝,其中銅 之一部份係包含銅金屬間化合物之區域。 另一方面,本發明係關於一種在具有壕溝之基材上提供 具有經改良電子遷移與腐蝕抗性之鋼互連體之方法,其包 括之步驟爲,在眞空工具中加熱基材,將呈氣體形式之含 碳物質引進眞空中,並在基材壕溝中沈積銅金屬,同時使 間隙原子摻入銅晶格中,以在壕溝中形成銅線條。此基材 在沈積期間較佳係保持在100_40(rc間之溫度下,且含碳物 質爲一種具有式CxHy或CxHx,且未含有氧、氮或硫之烴。 在一相關方面,本發明係提供一種具有銅線條互連體之 基材,其包含一對絕緣層’經配置在具有電特徵之基材上 ,此絕緣層具有經蝕刻之通孔銷釘圖樣,及經蝕刻之互連 線條圖樣,在該對絕緣體中形成孔淘與壕溝,作爲壕溝與 孔洞内襯之金屬層,及充填孔洞與壕溝之銅’此銅含有約 〇·1 至 15 ppm 破。 在另一方面,本發明係關於一種在具有與周園絕緣體呈 平面狀表面之基材互連體上提供保護性罩蓋之方法,此方 法包括之步驟爲,提供一基材’其具有絕緣層於其上,經 蚀刻之通孔銷釘圖樣及經蝕刻之互連線條圖樣,在絕緣層 内形成孔洞與壕溝,及銅冶金材料充填該孔洞與壕溝至絕 緣層之上方表面,以形成基材互連體。然後將銅抛光,以 使其表面下凹至低於其周圍絕緣層表面。接著沈積—層罩 蓋用之物質,覆蓋該凹陷銅至高於周園絕緣層表面之程度 °然後,將基材抛光以自基材互連體外侧之區域移除罩苦 -11 - 本紙國家鮮(CNS ) Α4^格(_21〇Χ297公釐) ~~~- (請先閲讀背面之注意事項再填寫本頁〕 *裝· 訂
經濟部中央標準局員工消費合作杜印製 437044 ΑΊ B7 五、發明説明(9 材料,並形成與周園絕緣層表面呈平面狀之罩蓋表面。ε 陷厚度較佳爲約卿埃至埃,且罩蓋用之材料係經遠揭 I·生地沈積’並選自包括鎢、鎢_矽、鎢-氮、铪、鍺、钽、 艇-氮化物、欽、錫、襴、缺、π Λίι > 珣糊、鍺、奴、鉻、鉻-氧化鉻、錫、 麵及其组合。 於又另一方面,本發明係提供—種形成銅線條之多階互 連體之方法,該銅線條係藉介電絕緣體互相隔離,以造成 對基材中電特徵之接觸,此方法包括以下步驟: ⑻製備具有介電絕緣層之基材,以接收銅線條在嗖之 圖樣中; (b) 視情況沈積金屬内襯在該圖樣中; (c) f著在該圖樣中沈積銅之化學蒸氣沈積層,或銅之物理 蒸氣沈積層,其具有低於約8〇〇埃之厚度;及 (d) 在薇化學或物理蒸氣沈積之銅層上,藉不同方法沈積一 層銅,以實質上填滿該圖樣。 只 該化學蒸氣沈積銅層較佳可具有厚度爲約5〇至2〇㈨埃, 更佳爲約100至700埃。物理蒸氣沈積可藉銅濺射或藉铜蒸 發,且此物理崧氣沈積銅層較佳係具有厚度低於約6㈨埃 〇 在沈積化學或物理蒸氣沈積銅層之前,此方法可包括在 圖樣中沈積一層能夠與銅形成金屬間化合物之元素之+ Υ 。於沈積實質上填滿該圖樣之銅層後,本發 :: 」巴括加叙 基材,以使該可形成金屬間層之元素與實質上填滿該圖樣 之銅層反應,以形成一層金屬間化合物之步驟。 人7 -12 本紙浪尺度逍用中國國家標準(CNS ) Α4規格(210X297公兹) ^ 裝 訂------k (請先聞讀背面之注意事項再填寫本頁) A7 B7 五、發明説明(10 ) 附圖簡述 咸認係爲新穎之本發明特徵,及本發明之構件特性’係 特別在隨文所附申請專利範圍中提出。附圖僅爲説明目的 ,且未按一定比例晝出。但是,本發明本身,關於機體組 成與操作方法兩者,可參考下文詳述並搭配附圓而獲得最 良好地明瞭,其中: 圖1爲先前技藝之部份多階銅互連體之立视圖,其係使 用電鍍銅以雙波紋方法製成,並描述在正常製程中所造成 之金屬腐姓與線條缺陷。 圖la爲圖1互連體一部份之放大視圖,説明使用於先前 技藝中之不同金屬層。 圖2爲在開始本發明方法之前,基材之立視圖;其中係 將一層有機介電絕緣體與另一個介電絕緣體之薄層沈積, 並根據先前技藝之雙波紋方法之陳述内容,將通孔銷釘與 互連線條之合併圖樣蝕刻,以曝露出下方之金屬特徵。 圖3爲在剛形成之互連結構中之不同層之立視圖,此結 構係併入本發明之可形成鋼金屬間層之組合物。 經濟部中央標準局貝工消費合作社印製 C请先閱请背面之注意事項异填窝本莧) 圖4爲圖3互連結構根據本發明將銅晶種層轉化成互連體 用之金屬間下層後之立視圖 圖5a與5b爲本發明替代具體實施例之立视圖,其中金屬 間層係在鋼互連體之中間形成,其中圖5a顯示小尺寸通孔 銷釘,而圖5b顯示大尺寸通孔銷釘。 圖6a-d爲如圖3中所示之所形成結構之立視圖,但其中鋼 (薄層係自頂部表面移除,以説明處理步驟之順序,以形 ,-1 In ______ -13- 本紙張尺度適财卿~^準(CNS ) Μ規格(2】Qx297公 437044 A7 B7 五、發明説明(11) 成根據本發明之罩蓋層。 圖7爲在剛形成互連結構中不同層之立視圖,其係利用 根據本發明之PVD或CVD銅晶種層製成。 圖8爲圖7之結構,.於銅之電鍍層已被沈積於晶種層上, 及晶圓已被抛光以移除過量金屬後之立視圖。 致皇具體實施例之;城 在描述本發明之較佳具體實施钩時,可參考本文之附圖 ,其中類似數字係指本發明之類似特徵。本發明之 在附圖中未必按一定比例顯示。 參考圖2,其係顯示習用矽半導體結構之橫截面,此結 構包含矽基材105,於其上具有各種裝置接觸銷釘(通孔 )1〇!與局部互連體(線條)102,典型上爲具有鼓與_氮化敛 下層(未示出)之鎢,個別在絕緣體層1〇6、1〇3上形成。利 用絕緣體薄層以防止在通孔與線條間之金屬尖釘形成,例 如由於失調準所致者,係揭示於美國專利申請案序號(律 =案二目綠編號Η9_96_137)中,其標題爲"具有次半微米多 階高密度電互連體之自動對準複合絕緣體及其製程”,與 本案同一曰期提出申請。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) μ本發明之方法係形成銅線條之可信賴多階互連體,在次 微米間距下,並藉由低介電絕緣體互相隔離,造成對基材 中兔特徵之接觸。此基材結構可爲具有多個電子裝置、有 機電路载體或陶瓷電路載體之半導體。局部互連體1〇2較 佳係藉先則技藝之波紋方法形成,其中局部互連體之頂部 表面係實質上與周園絕緣體1〇3之表面呈平面狀,典型上 μ氏張尺度適用 -14- 4370 4 4 A7 B7 五、發明説明(12) .! f 爲經沈積I硼矽酸鹽或磷矽酸鹽破璃或Si02。接著沈積介 電絕緣層2、3及4,以開始進行形成高導電率互連體之程 序·>此對絕緣體可藉ECR、濺射 '電漿加強CVD、、 旋轉塗覆或此等方法之任何組合進行沈積。例如,此等絕 緣體可製自聚醯亞胺、氮化矽、氧化鋁、二氧化矽、磷矽 酸鹽玻璃、氧化釔、氧化鎂' 氣凝膠或此等物質之任何組 合0 於共待審美國專利申請案序號〇8/841,221中所陳述之絕緣 體I選擇及將其納入積體電路製造中之方法,可採用於此 處,且此申請案之揭示内容係併於本文供參考。 經濟部中央標準局貝工消费合作社印製 (請先閲請背面之注意事項再填窝本頁} 訂 通孔銷釘圖樣係接著界定在絕緣體4頂上,例如藉光石 印紅序,接著爲以適當蚀刻劑蚀刻絕緣體4及部份蚀刻絕 緣體3之步驟。其次,再—次藉例如光石印程序界定高導 電率金屬互連線條之圖樣,接著蝕刻絕緣體3之其餘部份 及絕緣體2,以形成壕溝12與孔洞13,以曝露出金屬線條 102。此等步驟爲此項技藝中被稱爲雙波紋方法之最初處 理步驟,且係描述於公告中,譬如頒予Dalai等人之美國專 利5,434,451 ’歸屬於本申請案之讓受人,其揭示内容保併 於本文供參考。 其次’根據本發明沈積所選擇之内襯材料與高導電率金 属’並藉化學-機械方法抛光以移除過量金屬,於是同時 形成通孔銷釘與互連金屬線條圖樣。本發明係在此方法中 ,將合併之通孔銷釘與互連線條圖樣在絕緣體層2、3及4 上蝕刻以曝露出局部互連體102之一部份時施行。 -15- 本紙張尺度通用中國國家標準(CNS )八4規格(210X297公釐) 經濟部中夬標準局員工消费合作社印裂 Α7 !_______ — Β7 五、發明説明(13) 本發明之互連體係以圖3開始説明,爲清楚起見其中僅 顯示圖2之一郅份。在原位濺射清理具有圖2結構之晶圓後 ,沈積點著與接觸金屬之薄層5,典型上爲1〇〇至3〇〇埃厚 ,其較佳爲鈦 '鉅、氮化鉅、鉻、鎢或此等層之任何組合 。接著沈積選用之熱捬―散隍辟層6 ’典型上爲2〇〇至4〇〇埃 厚,其材料譬如鉻-氧化鉻、鎢_矽、鎢_氮化物、鎢_氮化 物-矽、鈦·氮化物、鈀或釦-氮化物。層5與6係稱爲被採 用於本發明中之内襯冶舍材料。接觸金屬可爲例如鈦、鈕 或鈕-氮化物。障壁材料可爲鈦_氮化物、鈦_氧_氮化物、 鋰、鋰-氮化物、鉻、鉻/氧化鉻、鎢、鎢_氮化物.、鎢— 5夕或其任何組合。 ,内襯層可藉共同或個別沈耪技術沈積,譬如賤射、蒸發 。較佳係採用濺射技術,譬如反應性濺射、準直藏射、磁 控管藏射、低壓賤射' ECR ί賤射、離子朿;:賤射或其任何組 合。層5與6之此等前述沈積,更佳係使用準直濺射,在單 次抽氣降壓中進行,及使用沈積及獻性^屬之技術,其係 由Dalai與Lowney陳述於美國專利4,379,832中,歸屬於本發明 I讓受人’其揭示内容係併於本文供參考。較佳沈積溫度 係在約120°C與400。(:之間。 在此選用層6之後,於本發明之第一個具體實施例中, 係沈積ii層7,較佳爲約1〇〇至600埃厚,其爲一種能夠與 銅形成金屬間化合物之元素 此種元素可選自包括铪、鑭 、結' 锡及鈦。然後,沈積薄銅晶種層8,典型上爲6〇0至 2000埃厚。 ______ -16- 本紙承尺度適用中關家標準(CNS ) Μ規格(2丨G>< 297公潑) (請先閲绩背面之注意事項再填寫本買)
.1.—,----」裝------訂----------------I I - I I n In 437U 4 4 Α7 ______87_ 五、發明説明(14 ) . .V ’ 層5-S可藉共同或個別沈積技術沈積,譬如濺射、蒸發或 CVD。較佳係採用濺射技術,譬如反應性濺射、準直藏射 、磁控管濺射、低歷濺射、ECR濺射、離子束濺射或其任 何組合。層5、6及7與8之此等前述沈積,更佳係使用準 直濺射,在單次抽氣降壓中進行,及使用沈積反應性金屬 之技術,其係由Dalai與Lowney陳述於美國專利4,379,832中, 歸屬於本發明之讓受人,其揭示内容係併於本文供參考。 較佳沈積溫度係在約120°C -400°C之間、鋼晶種層亦可故意 在間隙位置含有碳,以加強電子遷移抗性,其將進一步討 論於下文。 在鋼晶種層8之後,接著電鍍銅之其餘層9 ,以充填壕溝 。或者,可藉CVD方法沈積層8或8與9。然後藉化學_ .機械 方法拋光基材晶圓,以自未經構圖區域移除所有過量金屬 ,於是造成圖3中所示之平面化結構。 經濟部中夬標準局員工消費合作社印製 ϋ I i - up I - - I - - - :·Y ----- I I c请先閱讀背面之注意事項再填寫本頁) 若使用可形成金屬間之金屬層7,則接著將基材晶圓在 %如氮之非反應性氣層中,加熱至溫度約25〇_45〇。(3,歷經 3〇分鐘至2小時《這會造成形成金屬間之層7與銅層反應, 而形成圖4中之銅金屬間化合物層10。此銅金屬間層,對 銅層8與9提供經改良之電子遷移抗性。可形成金屬間之金 屬之厚度,較佳係經選擇,以在金屬間化合物形成期間消 耗所有銅晶種層8 (圖3)。藉本發明在鋼層中形成之金屬間 化合物,可爲銅化铪(班2〇1)、銅化鑭(LaCu2)、” _青銅 (Cu6 Sn5)、銅化鈦(TiCu)及銅化锆(Zr2 Cu)。 金屬間層可爲完全金屬間,或金屬間與成份金屬層之組 _________ -17- •^紙關家料(GNS ) Λ4規格(21QX297公疫) ---- 經濟部中央標準局員工消费合作社印裝 ' 437〇 A7 s___________ B7___ 五·、發明説明(15) 合。可形成金屬間層之元素之選擇,可以兩種標準爲基礎 。首先’經選擇之元紊較佳係未具有或具有低於2原子百 分比在銅中之溶解度。低溶解度是很重要的,否則此元素 將會擴散進入銅中,並影嚮其導電率。其次,此元素較佳 係與銅形成士疋金屬間層。除了上述元素以外,符合此等 標準之任何其他元素,均可採用作爲可形成銅金屬間之元 素。 . 重複上述處理步驟,以在較高程度下界定與形成互連體 。應明暸的是,在互連體之最後階層被界定後,吾人可選 擇僅進行一次熱處理’以形成金屬間層;或在互連體之各 階層後,可選擇重複熱處理。 於本發明之另一項具體實施例中,金屬間層係在互連體 厚度之中間艰成,如圖5a中關於小尺寸通孔銷釘,及圖5b 中關於較寬廣通孔銷釘所示。在此項具體實施例中,金屬 間層7係在最初鋼層後沈積,以形成遠離鋼邊緣及朝向内 部區域之金屬間化合物區域。圖5a顯示熱處理後之金屬間 區域10 (其中係首先沈積金屬間元素層7),在銅層9之内部 Y-形。亦可採用超過一個金屬間區域,如圖5b中所示, 其中金屬間元素7之兩個區域,係在熱處理後,被沈積在 經顯示爲金屬間化合物區域1〇a與1〇b之位置處。 於本發明之又另一項具體實施例中,可形成金屬間之元 素係被沈積在銅線條之頂部,呈罩蓋形式。如圖6a中所示 ,在形成圖3之平面化結構後,銅之薄層,大約100至400 埃厚,係被移除以使其表面自周園絕緣體表面下凹。移除 ____ -18- 本紙張尺度適用中國國家禕準(CNS ) A4規格(2〖0父297公釐)
{請先閲讀背面之注意事項再填寫本KC -裝· -訂 經濟部中央擦準局員工消費合作社印製 4370 4 4 A7 B7 五、發明説明(16 ) 可藉由銅互連線條或通孔銷釘之輕微化學-機械拋光、機 械抛光或兩者,以提供經平面化之罩蓋表面。 如圖6b中所示,可形成金屬間元素之薄層,係接著藉前 述方法(PVD、電鍍、無電鍍覆、CVD,或藉其任何組合) 選擇性地沈積,較佳係在晶圓之原位漱射清理後進行。接 著藉化學-機械拋光或僅藉機械抛光,自互連壕溝外侧移 除過量金屬,留下可形成金屬間元素之罩蓋在銅線條頂上 ’與層4之表面相同階層,如圖6c中所示。下一個步驟是 按上述熱處理晶圓,以在銅層9頂部形成金屬間層7。於圖 中顯示此具體實施例,其中金屬間層或區域係在銅互連 層之底部與頂部形成。 此種形成金屬間罩蓋層之方法,具有沿著線條邊緣完全 覆盖銅線條之優點,這與使得铜之狹缝外露不同,後者例 如在其中罩蓋金屬伴隨著内襯與銅一起沈積之方法中之情 況。應明瞭的是,雖然此種形成罩箪之方法,係於此處針 對形成金屬間化合物罩蓋之目的加以描述,但此方法並不 限於此種金屬,而是任何所要之金屬、合金或金屬間化合 物均可使用,譬如鎢、鎢-矽、鎢-氮、铪、锆、钽、钽- 氮化初欽、錫、_、錯、碳、路、路-氧化鉻 '錫 '舶 或其任何組合。 因此,銅金屬間層係藉選擇性沈積形成,無論是在銅線 條横截面之底部、中央、頂部,或在此等位置之任何组合 處。本發明係提供一種在任何或所有此等區域中,於原位 形成銅金屬間層,以改良銅互連線條之電子遷移抗性之方 —J--------.'> 裂------訂 (碕先聞讀背面之注意事項再填寫本頁} k紙張尺度適用中國國家^J_CNS ) M規格 -19- 297公釐)
• ' 4 3 7 0 4 4 46號專利申請案 書修正頁(89年8月) 經濟部中央標準局員工消费合作社印裝 Α7 Β7 五、發明説明(17) 法。 為在經沈積之鋼晶格中摻入碳原子,如上文所討論者, 銅晶種層較佳係在真空工具中,伴隨著呈氣體形式之含碳 物質之故意流失進行沈積。基材較佳係保持在約1〇〇_4⑻。c 之溫度下。此含碳物質為一種未包含氧、氮或硫之烴’譬 如歸屬於CxHy或CXHX烴基之含礙物質。此含碳物質可以濃 縮形式’或使用惰性載氣以稀釋形式引進真空工具中。真 空工具較佳為濺射或蒸發工具,且含碳物質之分壓係為約 1CT4 至 10_7 托。 此種沈積:序之更佳參數為首先將基材抽氣降壓至1〇_ 8托 之壓力’使用自動壓力控制,流出1〇-5托壓力下之乙玦氣 體,及接著引進4毫托壓力下之氬氣,以及濺射沈積鋼至 基材之蟑溝中。本發明之此方面係提供一種銅之互連體, 其具有0.1 ppm至15 ppm經溶解碳在銅晶格中。 已發現此種碳之摻入銅中,會在電鍍銅中達到加強之電 子遷移抗性,而在CVD銅中則達較小程度。雖然不希望被 理論所束縛,但咸信加強之電子遷移抗性係由於碳原子摻 入間隙位置所致《此種間隙碳不會些許地影嚮銅之電性 質,但會大為影嚮其化學與機械性質。 顯而易見的是’在給予本文所提出之指引與說明下,可 對熟練技師提示本發明方法與結構之替代具體實施例。例 如’應明瞭的是’鋼晶種層8係為在下—處理步驟中電鍍 銅之目的而沈積。若選擇使用CVD銅層9,則不需要晶種 層8。而且,該對絕緣體可為有機/無機、有機/有機或 -20- 本纸張尺度適用中國國家標準(CNS ) Α4規格(2丨0Χ 297公疫) ~~ - {請先閲讀背面之注ί項再填寫本頁)
‘ 437 u 4 4 A7 --------- B7 五、發明説明(18 ) 典機/無機。 亦已發現在藉波紋方法形成鋼互連體上,使用化學蒸氣 $積以沈積銅晶種層’當與使用先前技#中所採用之物理 蒸氣沈積(例如濺射或蒸發)技術,在典型ιι〇〇_2〇〇〇埃厚度 下比較時,係提供迄今未知之優點。所沈積之銅晶種 f,可具有厚度範園約50-2000埃,較佳係在約1〇〇-7〇〇埃之 範圍内。或者,PVD銅晶種層,當在厚度低於約8〇〇埃,較
佳係低於約600埃下沈積時,係提供勝過較厚先前技藝pvD 銅晶種層之優點。此等優點包括較高電子遷移抗性。當使 用CVD銅叩種層或當使用PVD銅晶種層而低於埃厚度時 ,充%壕溝之銅層可直接沈積在銅晶種層上,無需根據本 發明之銅金屬間層。銅層應藉不同於用以沈積晶種層之方 法沈積。 經濟部中央標準局員工消費合作社印製 ——τ--.----^---裝------討 > - · · \ (帑先聞讀背面之注意事項再填寫本頁) 本發明此方面之互連體,係顯示於圖7與8中。如圖7中 所示(其顯示圖2之一部份),在原位濺射清理具有圖2結構 之晶圓後,内襯曆5與6係以如前文所述之相同方式沈積, 其中熱擴散層6仍然是選用的。但是,代替沈積銅合屬間 層7,可將晶種層8直接沈積在内襯層6上,或若層6不存 在,則直接沈積在内襯層5上。若採用CVD技術,則晶種 層厚度8更佳係在約300至600埃之範圍内。若採用pyj)技術 ’則銅晶種層較佳係低於約6〇〇埃厚,更佳爲約2〇〇至5〇〇埃 厚。在鋼晶種層8之後’其餘銅層9係經電鍍,以完全充填 壕溝。然後’將基材晶圓藉化學-機械方法拋光,以自未 經構圖區域移除所有過量金屬,於是造成圖8中所示之結 ____-21 - 本紙張尺度適用中國國標準(CNS ) A4規格(2Ϊ0Χ 297公瘦) """ 437ϋ 4 4 Α7 Β7 五、發明説明(19 ) 構。於疋’此種結構可提供具有經改良電子遷移抗性與蜮 低缺陷感度之次四分之—微米鋼互連體。 雖然本發明已搭配特定較佳具體實施例,特別地加以播 述,但2以明自,許多替代方式、修正與變異,對熟諳此 藝者而言’在明白前述説明之後將是顯而易見的。因此, 意欲涵蓋在内的是,隨文所附之中請專利範園係包含任 此種落在本發明眞實範園與精神内之替代方式、修正 異。 、又 ----------裝-- 5請先閱讀背耷之注意亊項再填寫本育) 、-ϊτ 經濟部中央揉準局β;工消費合作社印製 -22- 本紙張尺度適财國卿樣準( cns )峨2似297公疫

Claims (1)

  1. AS B8 —' 7Γ7Ϊ1 4 310 4 4 嘴8·月2 I鱗號專利申請案 译鼻#專利範圍修正jff1 2 3 4 5 6年 六、申請專利範圍 1. 一種形成舞線條之多階互漣體之方法,該銅線條係藉介 \}/ ^^1 n^l m^— ^^^1 I n^i I ^^^1 n^i ^^^1 ^^—^1 I ---eJ (請先閲讀背面之注意事項再填寫各頁) 電絕緣體互相隔離,以造成對基材中電特徵之接觸,該 方法包括以下步驟: ⑻製備具有介電絕綾層之基材,以接收呈界^定圖樣之 钢結條; (b)視情況在該圖樣中沈積金屬内襯; ⑹在破圖樣中沈積一層能夠與錮形成会晟間j匕全物之 元素; (d) 接著在該圖樣中沈積一個化犖蒸氣沈積之铜層; (e) 在該化學蒸氣沈積之銅層上方,藉不同程&在沈積一 铜層,以f督上填滿該圖樣;及 (f) 加熱.基材,以使該可形成合屬間層之元去溆钴音暫 上1^~該_樣·^銅展反應,以形成一層余屬間」^_合 Ml。 2. 如申請專利範圍第丨項之方法,其中化學蒸氣沈積之銅 層具有約50至2000埃之厚度。 3. 如申請專利範圍第丨項之方法,其中化學蒸氣沈積之銅 層具有約100至700埃之厚度。 經濟部中央標隼局負工消費合作社印裝 1 如申請專利範圍第1項之f ▲!,其中可形成金屬間層之 2 元素:ί系選自包括給、鑭、鈦、錫及錯。 3 飞5. —種形成鋼線條之多階互連體之方法,該鋼線條係藉介 電絕緣體互相隔離,以造成對基材中電特徵之接觸,該 4 方法包掊以下步驟: 5 --- - _______________. -1 - ____ 6 本紙張从逋用中國國家榇準(CNS ) Α4^ ( 210X297公缓 1~ --------- 修正 437044 A8 B8 C8 D8 、申請專利範圍 之铜層,其 物理蒸氣沈積係藉 (a) 製備具有介電絕緣層之颜’以接收呈界定圖樣之 銅線條; (b) 視情況在該圖樣中沈積金屬内襯; ⑹在該圖樣中沈積二層能夠與銅形成金屬間化合物之 毛素; — ⑷接著在該圖樣中沈積一個物理幺邀沈精 具有低於約800埃之厚度; ㈦在該物理蒸氣沈積之銅層上方,藉不间程崖沈積— -銅層,以實質上填滿該圖樣;及 ⑺加熱·基材,以使該可形成金屬間層之元素與該實質 上填滿該圖樣之銅層反應,以形成一層金屬間化合 物。 6,如申請專利㈣第5項之方法,其中物理蒸氣沈積係藉 錦激射。 7.如申請專利範圍第5項之方法,其中 鋼蒸發。 8_如申請專利範圍第5項之方法,其中物理蒸氣沈積之销 層具有低於約600埃之厚度。 9.如中請專利範圍第5項之方法,其中 T 形成金屬間層之 元素係選自包括銓、鑭、鈦、錫及鲒。 10 —種.形成銅線條之多階互連體之方法,該銅線條係萨公 電絕緣體互相隔離,以造成對基材中電特徵之接觸:二 方法包括以下步驟: ^ (a)製備具有介電螂欲層之基材,以接收 获狀王界足圖樣之 ^紙張尺度適用尹國國家標準(CNS ) A4規格(21〇X2S>i公着) - 1—1 - - I 1 H 11λ. - - I I H— n ^請先閲讀背兩之注意事項再填寫本頁j 經濟部中央榇準局員工消費合作社印製 89: Η修正 丨曰 補充 Α8 Β8 C8 D8 經濟部中央標準局貝4消費合作社印聚 六、申請專利範圍 錮绫條; (b) 視情況在該圖樣中沈積金屬内襯; (c) 在該圖樣中洗積一層能夠與j同形成金屬間化合物之 元素; (d) 接著藉選自包括化學蒸氣沈積與物理基氣龙積之程 序,在該圖樣中沈積鋼晶種層,其中該晶種層具有 低於約800 .埃之厚度; (e) 在該鋼晶種層上方’藉石齓程序沈積一邀層,以實 質上填滿該圖樣;及 ⑺和.熱基材,以使該可形成金屬間層之元素與該實質 上填滿該圖樣之銅層反應’以形成—層金屬間化合 物。 11·如申請專利範圍第10項之方法,其中鋼晶種層具有低於 約600埃之厚度。 12. 如申請專利範圍第1〇項之方法,其中可形成金屬間層之 元素係選自包括給、鑭、钦、錫及錐。 13. ^申請專利範圍第12項之方法,其中鋼晶種層係藉物理 蒸氣沈積法進行沈積。 14. 如中請專利範圍第12項之方法,其中銅晶種層係藉化學 蒸氣沈積法進行沈積。 本紙嫩適用中 (請先閲讀背面之注^^項再填寫本頁)
TW087108346A 1997-05-30 1998-05-28 Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity TW437044B (en)

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US08/866,777 US6130161A (en) 1997-05-30 1997-05-30 Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
US08/947,277 US6069068A (en) 1997-05-30 1997-10-08 Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity

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EP0881673A3 (en) 1998-12-09
EP0881673B1 (en) 2006-10-11
JP3057054B2 (ja) 2000-06-26
KR19980087540A (ko) 1998-12-05
KR100304395B1 (ko) 2001-11-02
US6258710B1 (en) 2001-07-10
EP0881673A2 (en) 1998-12-02
DE69836114T2 (de) 2007-04-19
JPH1145887A (ja) 1999-02-16
DE69836114D1 (de) 2006-11-23
US6069068A (en) 2000-05-30

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