JPS6373660A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6373660A
JPS6373660A JP61218302A JP21830286A JPS6373660A JP S6373660 A JPS6373660 A JP S6373660A JP 61218302 A JP61218302 A JP 61218302A JP 21830286 A JP21830286 A JP 21830286A JP S6373660 A JPS6373660 A JP S6373660A
Authority
JP
Japan
Prior art keywords
substrate
metal layer
film
layer
barrier metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61218302A
Other languages
English (en)
Inventor
Kazuhiro Hoshino
和弘 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61218302A priority Critical patent/JPS6373660A/ja
Priority to EP87308050A priority patent/EP0269211A3/en
Priority to KR8710203A priority patent/KR900007146B1/ko
Priority to US07/097,738 priority patent/US4985750A/en
Publication of JPS6373660A publication Critical patent/JPS6373660A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要〕 本発明の配線材料に銅（ＣＬＩ　）薄膜を使用した半導
体装ｔにおいて、 コンタクトホールでは基板の材料とＣｕとが直接接触す
るために熱処理工程の際に反応を起してＣｕが基板中に
拡散してしまう問題点を解決するため、 基板表面に金属層及びバリアメタル層をこの順で８ＩＷ
！Ｊすることにより、バリアメタル層にて基板とＣｕと
の反応を防止し得、又、金属層にて基板と良好なコ、ン
タクトをとり得るようにしたものである。
〔産業上の利用分野〕
本発明は半導体装置、特に、配線材料としてＣＵＮ膜を
用いた半導体装置に関する。Ｃｕは耐エレクトロマイグ
レーションが良好で、又、コンタクト抵抗が低いこと等
からＡ２に代る配線材料として使用することが考えられ
る。この場合、特に、コンタクトホールにおいてＣｕと
基板との反応を防止し１７、又、基板と良好なコンタク
トをとり得る半導体装置が必要である。
（技術の背景〕 第２図は配線材料にＣｕｌ膜を用いた半導体装δの断面
図を示す。同図中、１は３ｉＩｔ板、２は５ＩＯ２絶縁
層であり、コンタクトホール２ａが設けられている。３
はＣｕａ？ＩＱで、コンタク１〜ホ−ル２ａに埋込まれ
、かつ、絶縁層２の表面に配線材料として設けられてい
る。
このように、Ｃ（Ｉは耐エレクトロマイグレーションが
良好で、かつ、コンタクト抵抗が低いこと等からＡ２に
代る配線材料として使用することが考えられる。
〔発明が解決しようとする問題点〕
然るに、上記構成になる装置は、コンタクトホール２ａ
において、３ｉ基板１の３ｉと配線材料のＣｕｅ膜３と
が直接接触するために熱処理工程の際に反応が起き、Ｃ
ｕＲＩ膜３がＳｉｌ板１中に拡散してしまい、コンタク
ト抵抗が高くなる問題点がある。
〔問題点を解決するための手段〕
本発明になる半導体装置は、第１図に示す如く、基板１
表面に金属層４及びバリアメタル層５をこの順で積層し
て設け、更に、この表面に配線材料であるＣｕ１ｌ膜６
を設け、上記バリアメタル層５にて上記Ｃｕ薄膜６の上
記基板１への拡散を防止し、上記金属層４にて上記基板
１とのコンタクトをとる構成としてなる。
〔作用〕
Ｃｕｅ膜６とＳｉ基板１との間にバリアメタル層５が設
けられているため、Ｃｕ薄膜６の８１基板１への拡散を
防止でき、又、バリアメタル層５とＳｉ基板１との間に
金属層４が設けられているため、Ｓｉ基板１とのコンタ
クト抵抗を低りシ得る。
〔実施例〕
第１図は本発明装置の一実施例の断面図を示し、同図中
、第２図と同一構成部分には同一番号を付す。同図中、
４は例えばＡＩｌ又はＴｉ等の金属層で、コンタクトホ
ール２ａの表面に例えば５００人の厚さで設けられてい
る。この金属層４はＳｉ基板１とコンタクトをとるため
のものである。５は例えばＴｉＮ又はＷ又はＴｉＷ等の
バリアメタル層で、金属層４の更に表面に例えば１２０
０人の厚さで設けられている。このバリアメタル層５は
Ｃｕ薄膜３の３ｉ基板１への拡散を防止するためのもの
である。
Ｃｕ薄膜６はバリアメタル層５の表面に例えば７０００
人の厚さで設けられている。
このように、Ｃｕｌ膜６とＳｉ基板１との間にはバリア
メタル層５が設けられているため、Ｃｕ薄膜６のＳｉ基
板１への拡散を防止できる。又、このままではＣｕ１ｌ
１６．バリアメタル層５と３ｉ基板１とのコンタクト抵
抗が高くなってしまうが、バリアメタル層５とＳｉ基板
１との間に金属層４が設けられているため、Ｓｉ基板１
とのコンタクト抵抗を低クシ１７る。
なお、金属層４及びバリアメタル層５の上下関係を第１
図のものと逆にすると、バリアメタル層５がＳ　ｉ　Ｉ
ｔ板１と接触するためにコンタクト抵抗が高くなってし
まう。従って、金属層４及びバリアメタル層５の上下関
係は第１図のものに限られる。
又、金属層４及びバリアメタル層５の夫々の材料は必ず
しも前述のものに限定されるものではない。
又、基板は必ずしもＳｉ基板に限定されるものではなく
、ＣａＯ膜と反応を起してＣＬＩが基板中に拡散する可
能性のある基板全てに適用される。
〔発明の効果〕
本発明によれば、バリアメタル層にてＣｕ１ｌ膜の基板
への拡散を防止し得、金属層にて基板とのコンタクトを
良好にとり得る等の特長を有する。
【図面の簡単な説明】
第１図は本発明装置の一実施例の断面図、第２図は配線
材料にＣＬＩを用いた半導体装置の断面図である。 図において、 １はＳｉ基板、 ２はＳ！０２絶縁膜、 ２ａはコンタクトホール、 ４は金属層、 ５はバリアメタル層、 ６はＣｕ薄膜である。 、Ｉヰ、′＼ ５「：（イ、。 代理人　弁理士　井　桁　負　、−、）、ｊ−、：、Ｔ
ユ１．１−ツノ （ｌニー′ 不発８月装置の逝面関 第１図 装置の断面図 第２図

Claims (1)

    【特許請求の範囲】
  1. 基板（１）表面に金属層（４）及びバリアメタル層（５
    ）をこの順で積層して設け、更に、この表面に配線材料
    である銅薄膜（６）を設けてなり、上記バリアメタル層
    （５）にて上記銅薄膜（６）の上記基板（１）への拡散
    を防止し、上記金属層（４）にて上記基板（１）とのコ
    ンタクトをとる構成としたことを特徴とする半導体装置
    。
JP61218302A 1986-09-17 1986-09-17 半導体装置 Pending JPS6373660A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP61218302A JPS6373660A (ja) 1986-09-17 1986-09-17 半導体装置
EP87308050A EP0269211A3 (en) 1986-09-17 1987-09-11 Semiconductor device having a metallic layer
KR8710203A KR900007146B1 (en) 1986-09-17 1987-09-15 Manufacture of semiconductor device
US07/097,738 US4985750A (en) 1986-09-17 1987-09-17 Semiconductor device using copper metallization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61218302A JPS6373660A (ja) 1986-09-17 1986-09-17 半導体装置

Publications (1)

Publication Number Publication Date
JPS6373660A true JPS6373660A (ja) 1988-04-04

Family

ID=16717709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61218302A Pending JPS6373660A (ja) 1986-09-17 1986-09-17 半導体装置

Country Status (4)

Country Link
US (1) US4985750A (ja)
EP (1) EP0269211A3 (ja)
JP (1) JPS6373660A (ja)
KR (1) KR900007146B1 (ja)

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JP2010135603A (ja) * 2008-12-05 2010-06-17 Panasonic Electric Works Co Ltd 配線構造

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US4985750A (en) 1991-01-15
KR880004551A (ko) 1988-06-04
KR900007146B1 (en) 1990-09-29

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