KR960012327A - 반도체 디바이스 및 그 제조 방법 - Google Patents

반도체 디바이스 및 그 제조 방법 Download PDF

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KR960012327A
KR960012327A KR1019950028065A KR19950028065A KR960012327A KR 960012327 A KR960012327 A KR 960012327A KR 1019950028065 A KR1019950028065 A KR 1019950028065A KR 19950028065 A KR19950028065 A KR 19950028065A KR 960012327 A KR960012327 A KR 960012327A
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insulating film
concentration
titanium
semiconductor device
fluorine
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KR1019950028065A
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KR0172205B1 (ko
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다다시 마쯔노
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사또 후미오
가부시끼가이샤 도시바
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Abstract

반도체 디바이스는 기판, 기판 상에 형성되고 실리콘-플로오르 결합을 포함하는 절연막; 및 절연막 상에 형성되고 절연막으로부터 확산되고 1 × 1020atoms/ cm3이하의 플루오르 농도를 갖고 있는 플루오르를 포함하는 티타늄계 금속 배선층을 포함한다.

Description

반도체 디바이스 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 제1실시예에 따른 반도체 디바이스의 주요 부분을 도시하는 단면도.

Claims (20)

  1. 기판; 상기 기판 상에 형성되고 실리콘-플루오르 결합(silicon-fluorine bonds)을 포함하는 절연막; 및 상기 절연막 상에 형성되고, 상기 절연막으로부터 확산되며 1 × 1020atoms/cm3이하의 플루오르 농도를 갖고 있는 플루오르를 포함하는 티타늄계 금속 배선층을 포함하는 것을 특징으로 하는 반도체 디바이스.
  2. 제1항에 있어서, 상기 절연막의 플루오르 농도는 막 두께 방향으로 거의 균일한 것을 특징으로 하는 반도체 디바이스.
  3. 제1항에 있어서, 상기 절연막의 플루오르 농도는 막 두께 방향으로 상기 티타늄계 금속 배선층으로부터 멀리 떨어진 거리에 따라 더 높게 되는 것을 특징으로 하는 반도체 디바이스.
  4. 제1항에 있어서, 상기 절연막은 상기 절연막의 플루오르 농도가 1 × 1021atoms/cm3이상인 영역을 갖고 있는 것을 특징으로 하는 반도체 디바이스.
  5. 제1항에 있어서, 상기 절연막은 단일층막으로 이루어지는 것을 특징으로 하는 반도체 디바이스.
  6. 제1항에 있어서, 상기 절연막은 적층막으로 이루어지는 것을 특징으로 하는 반도체 디바이스.
  7. 제1항에 있어서, 상기 티타늄계 금속 배선층은 티타늄 질화물을 포함하는 것을 특징으로 하는 반도체 디바이스.
  8. 기판; 상기 기판 상에 형성되고 실리콘-플루오르 결합을 포함하는 절연막; 상기 절연막 상에 형성된 티타늄계 금속 배선층; 및 상기 절연막과 상기 티타늄계 금속 배선층 사이에 형성되고 적어도 티타늄, 실리콘 및 산소를 포함하는 반응층을 포함하고, 상기 반응층은 막 두께 방향으로 적어도 상기 반응층의 중심 부분에 실리콘 농도 및 산소 농도에 대한 티타늄 농도의 비율이 각각 1 이하인 영역을 갖고 있는 것을 특징으로 하는 반도체 디바이스.
  9. 제8항에 있어서, 상기 금속 배선층 상에 형성된 본딩 패드를 더 포함하고, 실리콘 농도 및 산소 농도에 대한 티타늄 농도의 비율이 1 이하인 상기 반응층의 상기 영역이 상기 본딩 패드 아래에 형성되는 것을 특징으로 하는 반도체 디바이스.
  10. 제8항에 있어서, 실리콘 농도 및 산소 농도에 대한 티타늄 농도의 비율이 1 이하인 상기 반응층의 상기 영역에서의 플루오르 농도, 및 티타늄계 금속 배선층의 플루오르 농도는 1 × 1020atoms/cm3이하인 것을 특징으로 하는 반도체 디바이스.
  11. 제8항에 있어서, 실리콘 농도 및 산소 농도에 대한 티타늄 농도의 비율이 1 이하인 상기 반응층의 상기 영역의 평균 막 두께는 3.5 nm 이하인 것을 특징으로 하는 반도체 디바이스.
  12. 제8항에 있어서, 실리콘 농도 및 산소 농도에 대한 티타늄 농도의 비율이 1 이하인 상기 반응층의 상기 영역의 바로 아래에 형성된 플루오르 확산 억제막을 더 포함하는 것을 특징으로 하는 반도체 디바이스.
  13. 제12항에 있어서, 상기 플루오르 확산 억제막은 실리콘, 실리콘 질화물, 실리콘 산화물, 금속 및 이들 물질의 적층 부재로 이루어진 그룹으로부터 선택된 임의의 한 물질로 구성되는 것을 특징으로 하는 반도체 디바이스.
  14. 제8항에 있어서, 실리콘 농도 및 산소 농도에 대한 티타늄 농도의 비율이 1 이하인 상기 반응층의 상기 영역 바로 아래에 형성된 상기 절연막의 막 두께는 상기 영역이외의 상기 반응층 바로 아래에 형성된 상기 절연막의 막 두께보다 더 작은 것을 특징으로 하는 반도체 디바이스.
  15. 제1 및 제2영역을 갖고 있는 기판; 상기 기판 상에 형성되고 실리콘-플루오르 결합을 포함하며, 상기 제1영역 상에 제1두께를 갖고 있고 상기 제2영역 상에 상기 제1두께보다 더 큰 제2께를 갖고 있는 제1절연막; 상기 제1절연막 상에 형성된 티타늄계 금속 배선층; 및 적어도 상기 배선층 상에 형성되고, 상기 배선층 상의 배선 결합을 위해 상기 제1영역 상에 개구를 갖고 있는 제2절연막을 포함하는 것을 특징으로 하는 반도체 디바이스.
  16. 기판 상이 실리콘-플루오르 결합을 포함하는 절연막을 형성하는 단계; 프리 플루오르 및 플루오르 화합물을 상기 절연막 외부로 확산시키기 위해 상기 절연막의 어닐링을 행하는 단계; 및 상기 절연막 상에 티타늄계 금속 배선층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.
  17. 제16항에 있어서, 상기 어닐링 단계는 400℃ 이상의 비활성 가스 분위기에서 행해지는 것을 특징으로 하는 반도체 디바이스의 제조 방법.
  18. 제16항에 있어서, 상기 어닐링 단계는 적외선 램프를 사용하여 가열시킴으로써 행해지는 것을 특징으로 하는 반도체 디바이스의 제조 방법.
  19. 제16항에 있어서, 상기 어닐링 단계는 저압 프라즈마 방전으로 행해지는 것을 특징으로 하는 반도체 디바이스의 제조 방법.
  20. 제16항에 있어서, 실리콘-플루오르 결합을 포함하는 상기 절연막을 형성하는 단계 후 실리콘-플루오르 결합이 없는 절연막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950028065A 1994-09-01 1995-08-31 반도체 디바이스 및 그 제조 방법 KR0172205B1 (ko)

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