KR970053523A - 반도체 소자의 금속배선 형성방법 - Google Patents

반도체 소자의 금속배선 형성방법 Download PDF

Info

Publication number
KR970053523A
KR970053523A KR1019950048753A KR19950048753A KR970053523A KR 970053523 A KR970053523 A KR 970053523A KR 1019950048753 A KR1019950048753 A KR 1019950048753A KR 19950048753 A KR19950048753 A KR 19950048753A KR 970053523 A KR970053523 A KR 970053523A
Authority
KR
South Korea
Prior art keywords
layer
forming
metal wiring
semiconductor device
barrier metal
Prior art date
Application number
KR1019950048753A
Other languages
English (en)
Other versions
KR0172283B1 (ko
Inventor
김춘환
곽노정
김정태
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950048753A priority Critical patent/KR0172283B1/ko
Publication of KR970053523A publication Critical patent/KR970053523A/ko
Application granted granted Critical
Publication of KR0172283B1 publication Critical patent/KR0172283B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법이 개시된다.
본 발명은 장벽 금속층(Ti/TiN)과 젖음층(Ti)사이에 확산 방지층(TiN)을 형성하여 장벽 금속층과 젖음층사이의 계면에 티타늄 옥사이드(TiOx)층의 생성을 방지한다.
따라서, 본 발명은 확산 방지층에 의해 알루미늄 콘택 매립에 필요한 일정한 젖음층의 두께를 확보해 주므로써 콘택 매립의 균일성 및 금속배선의 신뢰성을 향상시킬 수 있다.

Description

반도체 소자의 금속배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a 내지 제2c도는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위해 도시한 소자의 단면도.

Claims (5)

  1. 반도체 소자의 금속배선 형성방법에 있어서, 접합부가 형성된 실리콘 기판상에 층간 절연막을 형성한 후, 상기 층간 절연막의 일부분을 식각하여 상기 접합부를 노출시킴에 의해 콘택홀이 형성되는 단계; 상기 콘택홀을 포함한 상기 층간 절연막상에 장벽 금속층을 형성한 후, 어닐링공정이 실시되는 단계; 상기 장벽 금속층상에 확산 방지층이 형성되는 단계; 상기 확산 방지층상에 젖음층이 형성되는 단계; 및 상기 젖음층상에 알루미늄층이 형성되는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  2. 제1항에 있어서, 상기 장벽 금속층은 티타늄과 티타늄 나이트라이드가 적층되어 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  3. 제1항에 있어서, 상기 장벽 금속층의 어닐링공정은 질소(N2)와 산소(O2)가스 분위기로 실시되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  4. 제1항에 있어서, 상기 확산 방지층은 티타늄 나이트라이드를 50 내지 100Å의 두께로 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  5. 제1항에 있어서, 상기 젖음층은 티타늄을 500 내지 700Å의 두께로 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950048753A 1995-12-12 1995-12-12 반도체 소자의 금속배선 형성방법 KR0172283B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950048753A KR0172283B1 (ko) 1995-12-12 1995-12-12 반도체 소자의 금속배선 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950048753A KR0172283B1 (ko) 1995-12-12 1995-12-12 반도체 소자의 금속배선 형성방법

Publications (2)

Publication Number Publication Date
KR970053523A true KR970053523A (ko) 1997-07-31
KR0172283B1 KR0172283B1 (ko) 1999-03-30

Family

ID=19439288

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950048753A KR0172283B1 (ko) 1995-12-12 1995-12-12 반도체 소자의 금속배선 형성방법

Country Status (1)

Country Link
KR (1) KR0172283B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100702780B1 (ko) * 2000-01-31 2007-04-03 주식회사 하이닉스반도체 반도체 장치의 배선 형성방법

Also Published As

Publication number Publication date
KR0172283B1 (ko) 1999-03-30

Similar Documents

Publication Publication Date Title
KR950034682A (ko) 반도체 소자의 금속배선 제조방법
KR970052347A (ko) 금속배선구조 및 형성방법
KR950009926A (ko) 반도체 소자의 금속배선 형성방법
KR970053523A (ko) 반도체 소자의 금속배선 형성방법
KR100208444B1 (ko) 반도체 소자의 금속배선 형성방법
KR0156126B1 (ko) 반도체장치의 콘택형성방법
KR100187685B1 (ko) 반도체 소자의 금속층 형성 방법
KR100399978B1 (ko) 반도체소자의베리어금속층형성방법
KR100380980B1 (ko) 텅스텐 게이트 형성 방법
KR100443363B1 (ko) 반도체 소자의 금속배선 형성방법
JP3189399B2 (ja) 半導体装置の製造方法
KR100219509B1 (ko) 반도체장치의 금속층 형성방법
KR100203305B1 (ko) 반도체 소자의 패시베이션 방법
KR950021108A (ko) 반도체 소자의 금속배선 형성방법
KR960042957A (ko) 반도체 소자의 확산방지층 형성방법
KR0144021B1 (ko) 텅스텐 접합층을 이용한 콘택홀 매립 방법
KR970052921A (ko) 반도체 소자의 금속층 형성 방법
KR970003475A (ko) 반도체 소자의 금속 배선 방법
KR970008347A (ko) 반도체 소자의 금속층 형성방법
JPH0311732A (ja) 半導体装置の配線形成方法
KR980005519A (ko) 반도체 소자의 금속배선 형성방법
JP2000323476A (ja) 配線構造およびその製造方法
KR970052297A (ko) 반도체소자의 금속배선 형성방법
KR980005528A (ko) 반도체 소자의 금속 배선 형성방법
KR970052537A (ko) 반도체장치의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060920

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee