KR970052347A - 금속배선구조 및 형성방법 - Google Patents

금속배선구조 및 형성방법 Download PDF

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KR970052347A
KR970052347A KR1019950056308A KR19950056308A KR970052347A KR 970052347 A KR970052347 A KR 970052347A KR 1019950056308 A KR1019950056308 A KR 1019950056308A KR 19950056308 A KR19950056308 A KR 19950056308A KR 970052347 A KR970052347 A KR 970052347A
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metal
nitride film
insulating film
semiconductor substrate
wiring structure
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김도형
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문정환
Lg 반도체주식회사
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Priority to US08/634,531 priority patent/US5795796A/en
Priority to JP8353344A priority patent/JP2789332B2/ja
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    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
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Abstract

본 발명은 금속배선구조 및 형성방법에 관한 것으로, 얇은 두께의 금속질화막을 포함한 금속절연막을 확산방지막으로 이용하여 장벽효과를 증대시키고, 고집적소자제조에 적합하도록 한 것이다. 본 발명에 따른 금속배선구조는 반도체기판상에 형성되고 금속배선용 금속이온들이 상기 반도체기판으로의 확산을 방지해 주는 금속질화막을 갖는 금속배선구조에 있어서, 상기 금속질화막위에 금속절연막이 형성된 구조를 포함한다. 본 발명에 따른 금속배선 형성방법은 반도체기판을 준비하는 단계; 상기 반도체기판상에 제1금속을 증착하는 단계; 상기 제1금속을 1차 열처리하여 제1금속질화막을 형성하는 단계; 상기 제1금속질화막상에 제2금속을 증착하여 2차 열처리하는 단계; 상기 제2금속위에 제3금속을 증착하는 단계; 상기 제2금속을 포함한 제3금속을 3차 열처리하여 상기 제2 및 제3금속이 혼합된 금속절연막을 형성하는 단계를 포함하여 이루어진다.

Description

금속배선구조 및 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 금속배선의 적층구조.

Claims (21)

  1. 반도체기판상에 형성되고 금속배선용 금속이온들이 상기 반도체기판으로의 확산을 방지해 주는 금속질화막을 갖는 금속배선구조에 있어서, 상기 금속질화막위에 금속절연막이 형성된 것을 특징으로 하는 금속배선구조.
  2. 제1항에 있어서, 상기 금속절연막은 CuMxOy, CuMxOyNz(0〈x〈1, 0〈y〈1, 0≤z〈1)중 1종인 것을 특징으로 하는 금속배선구조.
  3. 제2항에 있어서, 상기 M금속은 Al, Ti, Ta, Mg, Zr중 어느 하나인 것을 특징으로 하는 금속배선구조.
  4. 제1항에 있어서, 상기 금속절연막의 두께는 약 10~500Å인 것을 특징으로 하는 금속배선구조.
  5. 제1항에 있어서, 상기 금속절연막은 전도성을 띄는 것을 특징으로 하는 금속배선구조.
  6. 반도체기판을 준비하는 단계; 상기 반도체기판상에 제1금속을 증착하는 단계; 상기 제1금속을 1차 열처리하여 제1금속질화막을 형성하는 단계; 상기 제1금속질화막상에 제2금속을 증착하여 2차 열처리하는 단계; 상기 제2금속위에 제3금속을 증착하는 단계; 상기 제2금속을 포함한 제3금속을 3차 열처리하여 상기 제2 및 제3금속이 혼합된 금속절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 금속배선 형성방법.
  7. 제6항에 있어서, 상기 제1금속은 화학기상증착법(CVD)에 의해 증착하는 것을 특징으로 하는 금속배선 형성방법.
  8. 제6항에 있어서, 상기 제1금속은 Ti, W, Ta, TiSi, TaSi 중 어느 하나를 포함하는 것을 특징으로 하는 금속배선 형성방법.
  9. 제6항에 있어서, 상기 1차 열처리는 질소분위기하에서 이루어지는 것을 특징으로 하는 금속배선 형성방법.
  10. 제6항에 있어서, 상기 제1금속질화막은 TiNx, TaNx, WNx, TiSiNx, TaSiNx(0.25〈X〈0.75) 중 어느 하나를 포함하는 것을 특징으로 하는 금속배선 형성방법.
  11. 제6항에 있어서, 상기 제1금속질화막은 약 10~500Å 두께로 형성하는 것을 특징으로 하는 금속배선 형성방법.
  12. 제6항에 있어서, 상기 제2금속은 CVD법으로 증착하는 것을 특징으로 하는 금속배선 형성방법.
  13. 제6항에 있어서, 상기 2차 열처리는 산소 또는 대기분위기 중 어느 한 분위기하에서 이루어지는 것을 특징으로 하는 금속배선 형성방법.
  14. 제6항에 있어서, 상기 제3금속은 CVD법에 의해 증착하는 것을 특징으로 하는 금속배선 형성방법.
  15. 제6항에 있어서, 상기 제3금속은 Al, Ti, Zr, Ta, Pd중 1종을 포함하는 것을 특징으로 하는 금속배선 형성방법.
  16. 제6항에 있어서, 상기 3차 열처리는 O2, N2, O2/N2, 대기분위기중 어느 한 분위기하에서 이루어지는 것을 특징으로 하는 금속배선 형성방법.
  17. 제6항에 있어서, 상기 제2 및 제3금속이 혼합된 금속절연막은 CuMxOy, CuMxOyNz(0〈x〈1, 0〈y〈1, 0≤z〈1)중 1종을 포함하는 것을 특징으로 하는 금속배선 구조.
  18. 제17항에 있어서, 상기 M금속은 Al, Ti, Zr, Ta, Pd중 1종을 포함하는 것을 특징으로 하는 금속배선 형성방법.
  19. 제6항에 있어서, 상기 제2 및 제3금속이 혼합된 금속절연막은 약 10~500Å 두께로 형성하는 것을 특징으로 하는 금속배선 형성방법.
  20. 제6항에 있어서, 상기 금속절연막은 전도성을 띄도록 형성하는 것을 특징으로 하는 금속배선 형성방법.
  21. 제6항에 있어서, 상기 금속질화막과 금속절연막은 장벽층으로 사용하는 것을 특징으로 하는 금속배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950056308A 1995-12-26 1995-12-26 금속배선구조 및 형성방법 KR100205301B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019950056308A KR100205301B1 (ko) 1995-12-26 1995-12-26 금속배선구조 및 형성방법
US08/634,531 US5795796A (en) 1995-12-26 1996-04-18 Method of fabricating metal line structure
JP8353344A JP2789332B2 (ja) 1995-12-26 1996-12-17 金属配線の構造及びその形成方法

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KR1019950056308A KR100205301B1 (ko) 1995-12-26 1995-12-26 금속배선구조 및 형성방법

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JP2861129B2 (ja) * 1989-10-23 1999-02-24 日本電気株式会社 半導体装置
US5310602A (en) * 1991-11-12 1994-05-10 Cornell Research Foundation Self-aligned process for capping copper lines
JP2905032B2 (ja) * 1992-05-12 1999-06-14 シャープ株式会社 金属配線の製造方法
JPH06120355A (ja) * 1992-09-30 1994-04-28 Toshiba Corp 半導体装置の製造方法
DE4400200C2 (de) * 1993-01-05 1997-09-04 Toshiba Kawasaki Kk Halbleitervorrichtung mit verbesserter Verdrahtungsstruktur und Verfahren zu ihrer Herstellung
JP3283965B2 (ja) * 1993-05-13 2002-05-20 株式会社東芝 半導体装置およびその製造方法
JP3326698B2 (ja) * 1993-03-19 2002-09-24 富士通株式会社 集積回路装置の製造方法
KR0147682B1 (ko) * 1994-05-24 1998-11-02 구본준 반도체 소자의 금속배선 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396693B1 (ko) * 2000-03-30 2003-09-02 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법

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JP2789332B2 (ja) 1998-08-20
US5795796A (en) 1998-08-18
JPH09186103A (ja) 1997-07-15
KR100205301B1 (ko) 1999-07-01

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