KR950021406A - 멀티 레벨 상호 접속 구조를 가진 반도체 장치 - Google Patents

멀티 레벨 상호 접속 구조를 가진 반도체 장치 Download PDF

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KR950021406A
KR950021406A KR1019940037110A KR19940037110A KR950021406A KR 950021406 A KR950021406 A KR 950021406A KR 1019940037110 A KR1019940037110 A KR 1019940037110A KR 19940037110 A KR19940037110 A KR 19940037110A KR 950021406 A KR950021406 A KR 950021406A
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South Korea
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hole
semiconductor device
metal silicide
silicon
substrate
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KR1019940037110A
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KR0164441B1 (ko
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군니아끼 고야마
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가네꼬 히사시
니뽄 덴끼 가부시끼 가이샤
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53276Conductive materials containing carbon, e.g. fullerenes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

반도체 장치는 관통홀의 내벽과 직접 접촉한 상태로 미세 관통홀 내의 실리콘 관통 플러그를 포함한다. 금속규화물층은 상호 접속층과 실리콘 플러그 사이와 뿐만아니라 기판내에 형성된 확산층과 실리콘 플러그 사이에 형성된다. 미세 관통홀내에 형성된 형상 결함과 초과 응력을 대부분 측벽상에 금속막 또는 금속 규화물막 없이 실리콘 플러그내에 충전된다. 금속 규화물막은 규화 반응을 통한 열처리에 의해 형성된다.

Description

멀티 레벨 상호 접속 구조를 가진 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 실시예에 따른 반도체 장치내의 규화물 콘택트 전극과 상호 접속구조의 단면도이다.

Claims (7)

  1. 실리콘 기판과, 상기 실리콘 기판내에 형성된 확산 영역과, 상기 기판상에 형성되고 상기 확산 영역상에 관통홀을 가지는 절연막과, 상기 실리콘 플로그와 직접 접촉한 상태로 상기 금속 규화물로 만들어진 제2도전성 부분을 포함하는, 상기 절연막상에 형성된 상호접속층과, 상기 관통홀의 내벽과 직접 접촉한 상태로 상기 관통홀내에 형성된 실리콘 플러그와, 상기 확산영역과 상기 실리콘 플러그 사이에 금속 규화물로 형성된 제1도전성 부분을 포함하는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 금속 규화물은 Ti, Zr, Hf, V, Mo, Co와 Pt를 구성하는 그룹으로부터 선택된 금속을 포함하는 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 상호 접속층의 대부분은 상기 금속규화물로 만들어진 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 제1도전성부분은 상기 실리콘 플러그 아래의 상기 관통홀내에 형성된 것을 특징으로 하는 반도체 장치.
  5. 기판과, 상기 기판을 덮도록 형성된 제1상호 접속층과, 상기 상호 접속층 상에 형성되고 상기 상호 접속층의 제1부분을 노출하는 관통홀을 가지는 층간 절연막과, 상기 층간 절연막상에 형성되고 상기 관통홀상의 금속 규화물로 만든 제2부분을 가지는 제2상호 접속층과, 상기 관통홀의 내벽과 직접 접촉한 상태로 상기 관통홀내에 형성된 실리콘 플러그를 포함하는 것을 특징으로 하는 반도체 장치.
  6. 제5항에 있어서, 상기 금속 규화물은 Ti, Zr, Hf, V, Mo, Co와 Pt를 구성하는 그룹으로부터 선택된 금속을 포함하는 것을 특징으로 하는 반도체 장치.
  7. 제5항에 있어서, 상기 제1, 2 상호 접속층 중 적어도 하나는 상기 금속 규화물로 만든 것을 특징으로 하는 반도체 장치.
    ※참고사항:최초출원 내용에 의하여 공개하는 것임.
KR1019940037110A 1993-12-27 1994-12-27 멀티 레벨 상호 접속 구조를 가진 반도체 장치 KR0164441B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-330688 1993-12-27
JP5330688A JPH07193024A (ja) 1993-12-27 1993-12-27 半導体装置およびその製造方法

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KR950021406A true KR950021406A (ko) 1995-07-26
KR0164441B1 KR0164441B1 (ko) 1999-02-01

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US5514910A (en) 1996-05-07
KR0164441B1 (ko) 1999-02-01

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