KR950021406A - 멀티 레벨 상호 접속 구조를 가진 반도체 장치 - Google Patents
멀티 레벨 상호 접속 구조를 가진 반도체 장치 Download PDFInfo
- Publication number
- KR950021406A KR950021406A KR1019940037110A KR19940037110A KR950021406A KR 950021406 A KR950021406 A KR 950021406A KR 1019940037110 A KR1019940037110 A KR 1019940037110A KR 19940037110 A KR19940037110 A KR 19940037110A KR 950021406 A KR950021406 A KR 950021406A
- Authority
- KR
- South Korea
- Prior art keywords
- hole
- semiconductor device
- metal silicide
- silicon
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
반도체 장치는 관통홀의 내벽과 직접 접촉한 상태로 미세 관통홀 내의 실리콘 관통 플러그를 포함한다. 금속규화물층은 상호 접속층과 실리콘 플러그 사이와 뿐만아니라 기판내에 형성된 확산층과 실리콘 플러그 사이에 형성된다. 미세 관통홀내에 형성된 형상 결함과 초과 응력을 대부분 측벽상에 금속막 또는 금속 규화물막 없이 실리콘 플러그내에 충전된다. 금속 규화물막은 규화 반응을 통한 열처리에 의해 형성된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 실시예에 따른 반도체 장치내의 규화물 콘택트 전극과 상호 접속구조의 단면도이다.
Claims (7)
- 실리콘 기판과, 상기 실리콘 기판내에 형성된 확산 영역과, 상기 기판상에 형성되고 상기 확산 영역상에 관통홀을 가지는 절연막과, 상기 실리콘 플로그와 직접 접촉한 상태로 상기 금속 규화물로 만들어진 제2도전성 부분을 포함하는, 상기 절연막상에 형성된 상호접속층과, 상기 관통홀의 내벽과 직접 접촉한 상태로 상기 관통홀내에 형성된 실리콘 플러그와, 상기 확산영역과 상기 실리콘 플러그 사이에 금속 규화물로 형성된 제1도전성 부분을 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 금속 규화물은 Ti, Zr, Hf, V, Mo, Co와 Pt를 구성하는 그룹으로부터 선택된 금속을 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 상호 접속층의 대부분은 상기 금속규화물로 만들어진 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 제1도전성부분은 상기 실리콘 플러그 아래의 상기 관통홀내에 형성된 것을 특징으로 하는 반도체 장치.
- 기판과, 상기 기판을 덮도록 형성된 제1상호 접속층과, 상기 상호 접속층 상에 형성되고 상기 상호 접속층의 제1부분을 노출하는 관통홀을 가지는 층간 절연막과, 상기 층간 절연막상에 형성되고 상기 관통홀상의 금속 규화물로 만든 제2부분을 가지는 제2상호 접속층과, 상기 관통홀의 내벽과 직접 접촉한 상태로 상기 관통홀내에 형성된 실리콘 플러그를 포함하는 것을 특징으로 하는 반도체 장치.
- 제5항에 있어서, 상기 금속 규화물은 Ti, Zr, Hf, V, Mo, Co와 Pt를 구성하는 그룹으로부터 선택된 금속을 포함하는 것을 특징으로 하는 반도체 장치.
- 제5항에 있어서, 상기 제1, 2 상호 접속층 중 적어도 하나는 상기 금속 규화물로 만든 것을 특징으로 하는 반도체 장치.※참고사항:최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-330688 | 1993-12-27 | ||
JP5330688A JPH07193024A (ja) | 1993-12-27 | 1993-12-27 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950021406A true KR950021406A (ko) | 1995-07-26 |
KR0164441B1 KR0164441B1 (ko) | 1999-02-01 |
Family
ID=18235469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940037110A KR0164441B1 (ko) | 1993-12-27 | 1994-12-27 | 멀티 레벨 상호 접속 구조를 가진 반도체 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5514910A (ko) |
JP (1) | JPH07193024A (ko) |
KR (1) | KR0164441B1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5650654A (en) * | 1994-12-30 | 1997-07-22 | International Business Machines Corporation | MOSFET device having controlled parasitic isolation threshold voltage |
US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
KR100383498B1 (ko) | 1996-08-30 | 2003-08-19 | 산요 덴키 가부시키가이샤 | 반도체 장치 제조방법 |
US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
JP3015767B2 (ja) * | 1996-12-25 | 2000-03-06 | 三洋電機株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2975934B2 (ja) | 1997-09-26 | 1999-11-10 | 三洋電機株式会社 | 半導体装置の製造方法及び半導体装置 |
US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6081032A (en) * | 1998-02-13 | 2000-06-27 | Texas Instruments - Acer Incorporated | Dual damascene multi-level metallization and interconnection structure |
US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
US6917110B2 (en) * | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
US9553050B2 (en) | 2014-08-26 | 2017-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP7304721B2 (ja) * | 2019-03-18 | 2023-07-07 | 東京エレクトロン株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60236257A (ja) * | 1984-05-09 | 1985-11-25 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
DE3428741A1 (de) * | 1984-08-03 | 1986-02-13 | Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn | Messvorrichtung zur lagebestimmung fuer einen satelliten |
US4984039A (en) * | 1985-05-03 | 1991-01-08 | Texas Instruments Incorporated | Tapered trench structure and process |
FR2582446B1 (fr) * | 1985-05-24 | 1987-07-17 | Thomson Csf | Dispositif semi-conducteur photosensible et procede de fabrication d'un tel procede |
US4674173A (en) * | 1985-06-28 | 1987-06-23 | Texas Instruments Incorporated | Method for fabricating bipolar transistor |
JPS6334954A (ja) * | 1986-07-29 | 1988-02-15 | Nec Corp | 半導体装置およびその製造方法 |
JPH0290688A (ja) * | 1988-09-28 | 1990-03-30 | Nec Corp | 分布帰還型半導体レーザ |
JPH0671073B2 (ja) * | 1989-08-29 | 1994-09-07 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH0513714A (ja) * | 1990-01-25 | 1993-01-22 | Texas Instr Inc <Ti> | 溝型トランジスタ使用の双安定論理デバイス |
JPH03234062A (ja) * | 1990-02-09 | 1991-10-18 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
JPH0430422A (ja) * | 1990-05-25 | 1992-02-03 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JPH04167522A (ja) * | 1990-10-31 | 1992-06-15 | Nec Corp | 半導体デバイスおよびその製造方法 |
JP2550248B2 (ja) * | 1991-10-14 | 1996-11-06 | 株式会社東芝 | 半導体集積回路装置およびその製造方法 |
US5382817A (en) * | 1992-02-20 | 1995-01-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a ferroelectric capacitor with a planarized lower electrode |
-
1993
- 1993-12-27 JP JP5330688A patent/JPH07193024A/ja active Pending
-
1994
- 1994-12-27 KR KR1019940037110A patent/KR0164441B1/ko not_active IP Right Cessation
- 1994-12-27 US US08/364,226 patent/US5514910A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH07193024A (ja) | 1995-07-28 |
US5514910A (en) | 1996-05-07 |
KR0164441B1 (ko) | 1999-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970030370A (ko) | 티탄실리사이드층을 거쳐서 반도체영역과 전기배선용 금속을 접속하는 반도체집적회로 장치 및 그 제조방법 | |
KR940010352A (ko) | 반도체기억장치 | |
KR950034678A (ko) | 집적 회로내에 전도성 접속부 형성 방법 및, 그 회로내의 전도성 부재 | |
KR960039281A (ko) | 반도체 장치의 배선 구조 및 그 제조 방법 | |
KR970023863A (ko) | 반도체장치 및 그 제조방법 | |
KR950021406A (ko) | 멀티 레벨 상호 접속 구조를 가진 반도체 장치 | |
KR970008573A (ko) | 반도체 장치의 접속구조 및 그 제조방법 | |
KR900013585A (ko) | 반도체 소자의 제조방법 | |
KR910001914A (ko) | 반도체 집적 회로와 반도체 회로 내의 다결정 실리콘 접촉 형성방법 | |
KR950021526A (ko) | 반도체 장치 및 그의 제조방법 | |
KR960012554A (ko) | 바이폴러 트랜지스터 및 그의 제조방법 | |
KR960026953A (ko) | 반도체장치의 게이트전극 및 그 형성방법 | |
KR900007107A (ko) | 반도체 소자 | |
KR890008966A (ko) | 반도체장치의 배선접속부 | |
KR910016103A (ko) | 반도체장치 | |
KR960032601A (ko) | 폴리사이드와 폴리사이드간의 접촉방법 | |
KR970003968A (ko) | TiSi2 접점을 사용하여 DRAM 회로 내의 주변 영역으로 비트 라인을 병합시키는 방법 | |
KR970003537A (ko) | 타타늄 폴리-계의 cmos 회로 접촉부의 제조 방법 | |
KR970063500A (ko) | 반도체소자의 금속배선 형성방법 | |
KR930003424A (ko) | 반도체 장치의 제조방법 | |
KR950024265A (ko) | 반도체 장치의 금속 콘택부 구조 및 형성방법 | |
KR970003479A (ko) | 반도체 장치의 매복접촉 형성방법 | |
KR950024267A (ko) | 반도체장치의 금속배선시 콘택부 형성방법 및 구조 | |
KR970072090A (ko) | 반도체 소자의 배선층 형성 방법 | |
KR980005596A (ko) | 반도체 장치의 금속콘택 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030908 Year of fee payment: 6 |
|
LAPS | Lapse due to unpaid annual fee |