KR960026953A - 반도체장치의 게이트전극 및 그 형성방법 - Google Patents

반도체장치의 게이트전극 및 그 형성방법 Download PDF

Info

Publication number
KR960026953A
KR960026953A KR1019940038281A KR19940038281A KR960026953A KR 960026953 A KR960026953 A KR 960026953A KR 1019940038281 A KR1019940038281 A KR 1019940038281A KR 19940038281 A KR19940038281 A KR 19940038281A KR 960026953 A KR960026953 A KR 960026953A
Authority
KR
South Korea
Prior art keywords
forming
metal layer
gate electrode
polycrystalline silicon
barrier metal
Prior art date
Application number
KR1019940038281A
Other languages
English (en)
Other versions
KR0161380B1 (ko
Inventor
김영선
이내인
고대홍
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940038281A priority Critical patent/KR0161380B1/ko
Priority to JP7339693A priority patent/JPH08236769A/ja
Publication of KR960026953A publication Critical patent/KR960026953A/ko
Priority to US08/953,644 priority patent/US5852319A/en
Application granted granted Critical
Publication of KR0161380B1 publication Critical patent/KR0161380B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

3층구조의 게이트전극 및 그 형성방법에 관하여 기쟈되고 있다.
이는 반도체기판 상에 형성된 게이트산화막, 상기 게이트산화막 상에 형성된 다결정실리콘막, 상기 다결정실리콘막 상에 형성된 장벽급속층, 및 상기 장벽금속층 상에 형성된 저저항금속층을 포함하는 것을 특징으로 한다. 따라서 게이트전극의 전기적 특성 및 신뢰도를 향상시킬 수 있다.

Description

반도체장치의 게이트전극 및 그 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 일 방법에 의해 형성된 게이트전극을 도시한 단면도, 제3A도 내지 3D도는 본 발명의 제1실시예에 의한 게이트전극 형성방법을 설명하기 위해 도시한 단면도들이다. 제4A도 내지 4D도는 본 발명의 제2실시예에 의한 게이트전극 형성방법을 설명하기 위해 거시한 단면도들이다.

Claims (9)

  1. 반도체기판 상에 형성된 게이트산화막; 상기 게이트산화막 상에 형성된 다결정실리콘막; 상기 다결정실리콘막 상에 형성된 장벽금속층; 및 상기 장벽급속층 상에 형성된 저저항금속층을 포함하는 것을 특징으로 하는 반도체장치의 게이트전극.
  2. 제1항에 있어서, 상기 장벽금속층은 WSi2,TaSi2및 MoSi2등의 고융점 실리사이드와 WN, TiN, TaN,MoN등의 고융점 나이트라인으로 이루어진 군에서 선택된 하나로 형성되어 있는 것을 특징으로 하는 반도체장치의 게이트전극.
  3. 제1항에 있어서, 상기 장벽금속층은 TiTs2, TaSi2, CoSi2및 MoSi2등의로 이루어진 군에서 선택된 하나로 형성되어 있는 것을 특징으로 하는 반도체장치의 게이트전극.
  4. 반도체기판 상에 게이트산화막을 형성하는 제1공정; 상기 게이트산화막 상에 제1다결정실리콘막을 형성하는 제2공정; 상기 제1다결정실리콘막 상에 장벽금속층을 형성하는 제3공정; 상기 장벽금속층 상에 제2다결정실리콘막을 형성하는 제4공정; 상기 제3다결정실리콘막층 상에 실리사이드화 물질을 형성하는 제5공정; 결과물을 열처리하여 상기 실리사이드화 물질과 제2다결정실리콘막을 반응시킴으로서 저저항금속층을 형성하는 제6공정; 및 후속 열처리하는 제7공정을 포함하는 것을 특징으로 하는 반도체장치의 게이트전극 형성방법.
  5. 제4항에 있어서, 상기 장벽금속층은 상기 저저항금속층을 구성하는 입자가 제1다결정실리톰막으로 확산되지 않도록하는 물질을 사용하여 형성되는 것을 특징으로 하는 반도체장치의 게이트전극 형성방법.
  6. 제5항에 있어서, 상기 물질은 Wsix,TaSi2및 MoSi2등의 고융점 실리사리드와, WN, TiN, TaN,MoN등의 고융점 나이트라인으로 이루어진 군에서 선택된 하나로 형성되어 있는 것을 특징으로 하는 반도체장치의 게이트전극 형성방법.
  7. 제6항에 있어서, 상기 WSix는 WF6을 SiH나 SiHCI2등과 반응시켜 형성하는것을 특징으로 하는 반도체장치의 게이트전극 형성방법.
  8. 제4항에 있어서, 상기 실리사이드화 물질은 TI, Co, Ta 및 Mo등으로 이루어진 군에서 선택된 하나인 것을 특징으로 하는 반도체장치의 게이트전극 형성방법.
  9. 제4항에 있어서, 상기 제4공정 이후에, 적층된 물질들을 패터닝하여 게이트전극의패턴을 형성하는 공정 및 상기 패턴 측벽에 절연물질로 된 측벽스페이서를 형성하는 공정을 더 포함하는 는 것을 특징으로 하는 반도체장치의 게이트전극 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940038281A 1994-12-28 1994-12-28 반도체장치의 트랜지스터 및 그 제조방법 KR0161380B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940038281A KR0161380B1 (ko) 1994-12-28 1994-12-28 반도체장치의 트랜지스터 및 그 제조방법
JP7339693A JPH08236769A (ja) 1994-12-28 1995-12-26 半導体素子のゲ−ト電極及びその製造方法
US08/953,644 US5852319A (en) 1994-12-28 1997-10-17 Gate electrode for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038281A KR0161380B1 (ko) 1994-12-28 1994-12-28 반도체장치의 트랜지스터 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR960026953A true KR960026953A (ko) 1996-07-22
KR0161380B1 KR0161380B1 (ko) 1998-12-01

Family

ID=19404548

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038281A KR0161380B1 (ko) 1994-12-28 1994-12-28 반도체장치의 트랜지스터 및 그 제조방법

Country Status (3)

Country Link
US (1) US5852319A (ko)
JP (1) JPH08236769A (ko)
KR (1) KR0161380B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443352B1 (ko) * 1996-12-30 2004-10-14 주식회사 하이닉스반도체 반도체장치의실리사이드막형성방법

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100234378B1 (ko) * 1997-05-20 1999-12-15 윤종용 실리사이드를 이용한 스위칭 소자 및 그 제조방법
US5854115A (en) * 1997-11-26 1998-12-29 Advanced Micro Devices, Inc. Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length
JPH11220112A (ja) * 1998-01-30 1999-08-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6291868B1 (en) 1998-02-26 2001-09-18 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US5998847A (en) * 1998-08-11 1999-12-07 International Business Machines Corporation Low voltage active body semiconductor device
US7282443B2 (en) * 2003-06-26 2007-10-16 Micron Technology, Inc. Methods of forming metal silicide
US7348265B2 (en) * 2004-03-01 2008-03-25 Texas Instruments Incorporated Semiconductor device having a silicided gate electrode and method of manufacture therefor
KR100553714B1 (ko) * 2004-07-14 2006-02-24 삼성전자주식회사 자기정렬 실리사이드층을 가지는 반도체 소자 및 그제조방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3230077A1 (de) * 1982-08-12 1984-02-16 Siemens AG, 1000 Berlin und 8000 München Integrierte bipolar- und mos-transistoren enthaltende halbleiterschaltung auf einem chip und verfahren zu ihrer herstellung
JPS61166075A (ja) * 1985-01-17 1986-07-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPS63284857A (ja) * 1987-05-18 1988-11-22 Toshiba Corp 半導体装置及びその製造方法
JP2753301B2 (ja) * 1989-01-20 1998-05-20 株式会社日立製作所 半導体集積回路装置
JP2695014B2 (ja) * 1989-09-06 1997-12-24 株式会社東芝 Mos型半導体装置
US5341016A (en) * 1993-06-16 1994-08-23 Micron Semiconductor, Inc. Low resistance device element and interconnection structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443352B1 (ko) * 1996-12-30 2004-10-14 주식회사 하이닉스반도체 반도체장치의실리사이드막형성방법

Also Published As

Publication number Publication date
US5852319A (en) 1998-12-22
KR0161380B1 (ko) 1998-12-01
JPH08236769A (ja) 1996-09-13

Similar Documents

Publication Publication Date Title
KR970003718A (ko) 모스 전계 효과 트랜지스터 형성 방법
JP2002118241A5 (ko)
KR970052544A (ko) 반도체 소자의 폴리레지스터 구조 및 그 제조방법
KR960026953A (ko) 반도체장치의 게이트전극 및 그 형성방법
TWI309890B (en) Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method
KR950021406A (ko) 멀티 레벨 상호 접속 구조를 가진 반도체 장치
KR100673902B1 (ko) 텅스텐폴리메탈게이트 및 그의 제조 방법
KR920015622A (ko) 집적 회로의 제조방법
KR970077210A (ko) 텅스텐 실리사이드를 갖는 반도체소자 제조방법
JP2842842B2 (ja) Mos型半導体装置およびその製造方法
KR100607305B1 (ko) 반도체 소자의 금속 배선 형성 방법
KR20040001861A (ko) 금속게이트전극 및 그 제조 방법
KR960042948A (ko) 반도체장치의 폴리사이드 콘택 및 그 형성방법
JPH10214833A (ja) 半導体装置用配線構造及びその製造方法
KR960030446A (ko) 피모스 트랜지스터 및 그 제조방법
KR920018929A (ko) 반도체장치의 폴리사이드 게이트전극구조 및 그 제조방법
KR950021086A (ko) 반도체장치 및 그 제조방법
KR960032601A (ko) 폴리사이드와 폴리사이드간의 접촉방법
KR970018086A (ko) 반도체장치의 게이트전극 형성방법
KR970077070A (ko) 텅스텐 실리사이드를 갖는 반도체소자 제조방법
KR930006885A (ko) 반도체 소자의 금속배선 방법
KR970018658A (ko) 확산방지층을 함유하는 게이트 구조 및 그 제조방법
KR970018406A (ko) 고내열 금속배선 형성방법
KR970013421A (ko) 박막트랜지스터 제조방법
KR960043123A (ko) 반도체 장치의 폴리사이드 간의 층간접속방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110729

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee