KR970003718A - 모스 전계 효과 트랜지스터 형성 방법 - Google Patents
모스 전계 효과 트랜지스터 형성 방법 Download PDFInfo
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- KR970003718A KR970003718A KR1019950018862A KR19950018862A KR970003718A KR 970003718 A KR970003718 A KR 970003718A KR 1019950018862 A KR1019950018862 A KR 1019950018862A KR 19950018862 A KR19950018862 A KR 19950018862A KR 970003718 A KR970003718 A KR 970003718A
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- 230000005669 field effect Effects 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 36
- 239000002184 metal Substances 0.000 claims abstract 27
- 229910052751 metal Inorganic materials 0.000 claims abstract 27
- 238000000034 method Methods 0.000 claims abstract 24
- 229920005591 polysilicon Polymers 0.000 claims abstract 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract 8
- 239000000758 substrate Substances 0.000 claims abstract 7
- 239000004065 semiconductor Substances 0.000 claims abstract 6
- 238000000151 deposition Methods 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims 9
- 230000004888 barrier function Effects 0.000 claims 3
- 229910052759 nickel Inorganic materials 0.000 claims 3
- 229910052715 tantalum Inorganic materials 0.000 claims 3
- 229910052719 titanium Inorganic materials 0.000 claims 3
- 229910052721 tungsten Inorganic materials 0.000 claims 3
- 238000000059 patterning Methods 0.000 claims 2
- 238000000137 annealing Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
본 발명은 모스 전계 효과 트랜지스터 형성 방법에 관한 것으로, 금속막 또는 금속 실리사이드막을 이용한 게이트 전극의 형성에 있어서, 게이트와 실리콘이 단락되는 현상을 방지하기 위하여 게이트 산화막의 상부에 다결정실리콘층을 증착하므로써, 다결정실리콘 패턴의 형성시에 게이트 산화막이 식각되어 게이트와 반도체 기판이 단락되는 현상을 방지한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도 내지 제8도은 본 발명의 제1실시예에 따라 모스 전계 효과 트랜지스터를 형성하는 단계를 도시한 단면도.
Claims (19)
- 반도체 기판의 상부에 게이트 산화막, 제1다결정실리콘층, 절연막 및 제2다결정실리콘층을 적층하고, 게이트 패턴 공정으로 제1다결정실리콘층을 절연막이 노출될 때까지 식각하여 제1다결정실리콘 패턴을 형성하는 단계와, 상기 제2다결정실리콘 패턴을 마스크로하여 절연막을 식각하여 절연막 패턴을 형성하는 단계와, 전체 구조의 상부에 금속막을 증착하는 단계와, 상기 금속막을 이방성식각하여 제2다결정실리콘의 측면에 금속막 사이드월을 형성하는 단계와, 상기 제2다결정실리콘 패턴과 금속막 사이드월을 마스크로 하여 상기 제1다결정실리콘층과 게이트 산화막을 식각하므로써, 반도체 기판의 상부에 제2다결정실리콘 패턴, 금속막 사이드월, 제1다결정실리콘 패턴 및 절연막 패턴으로 메탈사이드 구조의 게이트를 형성하는 단계를 포함하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제1항에 있어서, 상기 게이트 산화막의 식각시 제1다결정실리콘층이 식각 장벽막 역활을 하므로 두께가 얇은 경우에도 게이트 하부의 게이트 산화막은 식각되지 않는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제1항에 있어서, 상기 금속막은 W, Ta, Ti, Mo, Pt, Ni, Co 중에 하나를 선택하여 사용하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제1항에 있어서, 상기 금속막의 두께가 100A 내지 1000A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제1항에 있어서, 제1다결정실리콘층의 두께가 100A 내지 500A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제1항에 있어서, 절연막의 두께가 50A 내지 500A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 반도체 기판의 상부에 게이트 산화막, 제1다결정실리콘층, 절연막 및 제2다결정실리콘층을 적층하고, 게이트 패턴 공정으로 제1다결정실리콘 패턴과, 절연막 패턴을 형성하고, 전체 구조의 상부에 금속막을 형성하는 단계와, 상기 금속막을 이방성식각하여 제2다결정실리콘의 측면에 금속막 사이드월을 형성하는 단계와, 열처리 공정을 통하여 상기 제2다결정실리콘 패턴과 제1다결정실리콘층이 접합 부분의 금속막을 반응시켜 금속 실리사이드막으로 형성하는 단계와, 상기 제2다결정실리콘 패턴과 금속 실리사이드막을 마스크로 하여 상기 제1다결정실리콘층과 게이트 산화막을 식각하므로써, 반도체 기판의 상부에 제2다결정실리콘 패턴, 금속 실리사이드, 제1다결정실리콘 패턴 및 절연막 패턴으로 폴리사이드 구조의 게이트를 형성하는 단계를 포함하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 제조 방법.
- 제7항에 있어서, 게이트 산화막의 식각시 제1다결정실리콘층이 식각 장벽막 역활을 하여 두께가 얇은 경우에도 게이트 하부의 게이트 산화막은 식각되지 않는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제7항에 있어서, 상기 금속막은 W, Ta, Ti, Mo, Pt, Ni, Co 중에 하나를 사용하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제7항에 있어서, 상기 금속막의 두께가 100A 내지 1000A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제7항에 있어서, 제1다결정실리콘층의 두께가 100A 내지 500A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제7항에 있어서, 절연막의 두께가 50A 내지 500A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 반도체 기판의 상부에 게이트 산화막, 제1다결정실리콘층, 절연막 및 제2다결정실리콘층을 적층하고, 게이트 패턴 공정으로 제1다결정실리콘 패턴과, 절연막 패턴을 형성하고, 전체 구조의 상부에 금속막을 형성하는 단계와, 열처리 공정을 통하여 제2다결정실리콘 패턴 및 제1다결정실리콘층과 접합 부분의 금속막을 반응시켜 금속 실리사이드막을 형성하는 단계와, 상기 금속 실리사이드막을 이방성식각하여 제2다결정실리콘 패턴의 측면에 금속실리사이드 사이드월을 형성하고, 반도체 기판의 상부에 제2다결정실리콘 패턴, 금속 실리사이드 사이드월, 제2다결정실리콘 패턴 및 절연막 패턴으로 폴리사이드 구조의 게이트를 형성하는 단계를 포함하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제13항에 있어서, 폴리 사이드 구조의 게이트를 형성한 후에 게이트 산화막을 식각하는 단계를 추가로 구비하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제13항에 있어서, 게이트 산화막의 식각시 제2다결정실리콘층이 식각 장벽막 역활을 하여 두께가 얇은 경우에도 게이트 하부의 게이트 산화막은 식각되지 않는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제13항에 있어서, 상기 금속막은 W, Ta, Ti, Mo, Pt, Ni, Co 중에 하나를 사용하는 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제13항에 있어서, 상기 금속막의 두께가 100A 내지 1000A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제13항에 있어서, 제1다결정실리콘층의 두께가 100A 내지 500A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.
- 제13항에 있어서, 절연막의 두께가 50A 내지 500A인 것을 특징으로 하는 모스 전계 효과 트랜지스터 형성 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018862A KR100190757B1 (ko) | 1995-06-30 | 1995-06-30 | 모스 전계 효과 트랜지스터 형성방법 |
US08/666,214 US5753546A (en) | 1995-06-30 | 1996-06-20 | Method for fabricating metal oxide field effect transistors |
CN96106872A CN1076870C (zh) | 1995-06-30 | 1996-06-27 | 制造金属氧化物场效应晶体管的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950018862A KR100190757B1 (ko) | 1995-06-30 | 1995-06-30 | 모스 전계 효과 트랜지스터 형성방법 |
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Publication Number | Publication Date |
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KR970003718A true KR970003718A (ko) | 1997-01-28 |
KR100190757B1 KR100190757B1 (ko) | 1999-06-01 |
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KR1019950018862A KR100190757B1 (ko) | 1995-06-30 | 1995-06-30 | 모스 전계 효과 트랜지스터 형성방법 |
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US (1) | US5753546A (ko) |
KR (1) | KR100190757B1 (ko) |
CN (1) | CN1076870C (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010001737A (ko) * | 1999-06-08 | 2001-01-05 | 김선수 | 스크린 프린터의 캡처장치 및 그 방법 |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5981367A (en) * | 1996-10-17 | 1999-11-09 | Micron Technology, Inc. | Method for making an access transistor |
US5937319A (en) * | 1997-10-31 | 1999-08-10 | Advanced Micro Devices, Inc. | Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching |
US6501098B2 (en) | 1998-11-25 | 2002-12-31 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device |
KR100328830B1 (ko) * | 1999-08-02 | 2002-03-14 | 박종섭 | 모스페트 소자의 제조 방법 |
US20040038489A1 (en) * | 2002-08-21 | 2004-02-26 | Clevenger Lawrence A. | Method to improve performance of microelectronic circuits |
US6909145B2 (en) * | 2002-09-23 | 2005-06-21 | International Business Machines Corporation | Metal spacer gate for CMOS FET |
US6849487B2 (en) * | 2003-05-27 | 2005-02-01 | Motorola, Inc. | Method for forming an electronic structure using etch |
KR100541152B1 (ko) * | 2003-07-18 | 2006-01-11 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속 배선층 형성 방법 |
US6943097B2 (en) * | 2003-08-19 | 2005-09-13 | International Business Machines Corporation | Atomic layer deposition of metallic contacts, gates and diffusion barriers |
EP1677359A4 (en) * | 2003-10-23 | 2008-06-25 | Fujitsu Ltd | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME |
CN100385625C (zh) * | 2004-03-15 | 2008-04-30 | 华邦电子股份有限公司 | 多晶硅化金属栅极结构及其制造方法 |
US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7413981B2 (en) * | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
US8123968B2 (en) * | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US7816262B2 (en) * | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7687342B2 (en) * | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7759197B2 (en) | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7557032B2 (en) * | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) * | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US7723009B2 (en) | 2006-06-02 | 2010-05-25 | Micron Technology, Inc. | Topography based patterning |
US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US8129289B2 (en) | 2006-10-05 | 2012-03-06 | Micron Technology, Inc. | Method to deposit conformal low temperature SiO2 |
US8227342B2 (en) * | 2007-01-11 | 2012-07-24 | Stmicroelectronics (Crolles 2) Sas | Method of fabricating a transistor with semiconductor gate combined locally with a metal |
US7923373B2 (en) * | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0638496B2 (ja) * | 1983-06-27 | 1994-05-18 | 日本電気株式会社 | 半導体装置 |
US4716131A (en) * | 1983-11-28 | 1987-12-29 | Nec Corporation | Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film |
US4660276A (en) * | 1985-08-12 | 1987-04-28 | Rca Corporation | Method of making a MOS field effect transistor in an integrated circuit |
US5247198A (en) * | 1988-09-20 | 1993-09-21 | Hitachi, Ltd. | Semiconductor integrated circuit device with multiplayered wiring |
US5221853A (en) * | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
KR920010062B1 (ko) * | 1989-04-03 | 1992-11-13 | 현대전자산업 주식회사 | 반도체 장치의 실리사이드 형성방법 |
KR940001402B1 (ko) * | 1991-04-10 | 1994-02-21 | 삼성전자 주식회사 | 골드구조를 가지는 반도체소자의 제조방법 |
EP0575280A3 (en) * | 1992-06-18 | 1995-10-04 | Ibm | Cmos transistor with two-layer inverse-t tungsten gate structure |
KR0141195B1 (ko) * | 1994-06-08 | 1998-07-15 | 김광호 | 저저항 게이트전극을 갖는 반도체소자의 제조방법 |
US5472896A (en) * | 1994-11-14 | 1995-12-05 | United Microelectronics Corp. | Method for fabricating polycide gate MOSFET devices |
-
1995
- 1995-06-30 KR KR1019950018862A patent/KR100190757B1/ko not_active IP Right Cessation
-
1996
- 1996-06-20 US US08/666,214 patent/US5753546A/en not_active Expired - Lifetime
- 1996-06-27 CN CN96106872A patent/CN1076870C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010001737A (ko) * | 1999-06-08 | 2001-01-05 | 김선수 | 스크린 프린터의 캡처장치 및 그 방법 |
Also Published As
Publication number | Publication date |
---|---|
US5753546A (en) | 1998-05-19 |
CN1142684A (zh) | 1997-02-12 |
CN1076870C (zh) | 2001-12-26 |
KR100190757B1 (ko) | 1999-06-01 |
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