KR960032601A - 폴리사이드와 폴리사이드간의 접촉방법 - Google Patents

폴리사이드와 폴리사이드간의 접촉방법 Download PDF

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Publication number
KR960032601A
KR960032601A KR1019950002138A KR19950002138A KR960032601A KR 960032601 A KR960032601 A KR 960032601A KR 1019950002138 A KR1019950002138 A KR 1019950002138A KR 19950002138 A KR19950002138 A KR 19950002138A KR 960032601 A KR960032601 A KR 960032601A
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South Korea
Prior art keywords
polyside
layer
metal
contact hole
forming
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KR1019950002138A
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English (en)
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KR100355220B1 (ko
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김의송
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김광호
삼성전자 주식회사
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Priority to KR1019950002138A priority Critical patent/KR100355220B1/ko
Publication of KR960032601A publication Critical patent/KR960032601A/ko
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Publication of KR100355220B1 publication Critical patent/KR100355220B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

2개이상의 폴리사이드를 가지는 반도체 장치의 폴리사이드 간의 저저항의 접촉방법을 개시한다.
이를 위해서, 제1폴리사이드 형성 후 TiN의 금속층을 형성하고 이를 급속순간어닐링하여 제1 및 제2폴리사이드 접촉부분에 TiSix의 금속실리콘층을 형성하는 단계를 거친후 제2폴리사이드를 형성한다.
이로써, 제1및 제2폴리사이드간의 접촉저항을 낮출 수 있어 반도체소자특성저하를 억제할 수 있다.

Description

폴리사이드와 폴리사이드간의 접촉방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2C도는 본 발명에 따른 폴리사이드와 폴리사이드간의 접촉방법을 나타내는 단면도이다.

Claims (3)

  1. 필드산화막에 의해 한정되는 반도체 기판의 활성영역에 형성된 소오스와 드레인을 가지며 2개 이상의 폴리사이드를 가지는 반도체 장치에 있어서, 상기 소오스와 드레인 사이에 해당하는 상기 반도체 기판 상에 제1폴리실리콘층과 제1금속실리사이드층을 형성하여 제1폴리사이드를 형성하는 단계; 결과물 전면에 층간졀연막을 도포하고 패턴화하여 상기 제1폴리사이드의 소정부분이 노출되게 하는 접촉구를 형성하는 단계; 상기 층간절연막의 상면, 상기 접촉구의 내측벽 및 상기 제1폴리사이드의 상면에 금속층을 형성하는 단계; 상기 금속층을 급속순간어닐링하여 상기 접촉구의 상면에 형성된 금속층을 금속실리콘층으로 변환시키는 단계; 및 상기 금속층과 금속실리콘층 위에 제2폴리실리콘층과 제2실리사이드층을 순차적으로 형성하고 패턴화하여 제2폴리사이드를 형성하는 단계를 구비함을 특징으로 하는 폴리사이드 간의 접촉방법.
  2. 제1항에 있어서, 상기 금속실리콘층이 WSix, TiSix, TaSix중의 어느 하나임을 특징으로 하는 폴리사이드 간의 접촉방법.
  3. 제1항에 있어서, 상기 제1 및 제2금속실리사이드층이 제1 및 제2텅스텐폴리사이드층임을 특징으로 하는 폴리사이드 간의 접촉방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950002138A 1995-02-07 1995-02-07 폴리사이드와폴리사이드간의접촉방법 KR100355220B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950002138A KR100355220B1 (ko) 1995-02-07 1995-02-07 폴리사이드와폴리사이드간의접촉방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950002138A KR100355220B1 (ko) 1995-02-07 1995-02-07 폴리사이드와폴리사이드간의접촉방법

Publications (2)

Publication Number Publication Date
KR960032601A true KR960032601A (ko) 1996-09-17
KR100355220B1 KR100355220B1 (ko) 2002-12-28

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KR1019950002138A KR100355220B1 (ko) 1995-02-07 1995-02-07 폴리사이드와폴리사이드간의접촉방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430687B1 (ko) * 1996-12-31 2004-08-02 주식회사 하이닉스반도체 반도체소자의금속배선형성방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430687B1 (ko) * 1996-12-31 2004-08-02 주식회사 하이닉스반도체 반도체소자의금속배선형성방법

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KR100355220B1 (ko) 2002-12-28

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