KR910016103A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
- Publication number
- KR910016103A KR910016103A KR1019910002123A KR910002123A KR910016103A KR 910016103 A KR910016103 A KR 910016103A KR 1019910002123 A KR1019910002123 A KR 1019910002123A KR 910002123 A KR910002123 A KR 910002123A KR 910016103 A KR910016103 A KR 910016103A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- silicon nitride
- nitride film
- insulating film
- interlayer insulating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 12
- 239000011229 interlayer Substances 0.000 claims 7
- 239000010410 layer Substances 0.000 claims 5
- 230000001681 protective effect Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 제 1 실시예에 따른 반도체장치의 구성을 나타낸 단면도.
Claims (12)
- 적어도 1층의 실리콘질화막(16,37)으로 이루어진 층간절연막을 전극인출용 접촉개구부(18,39)를 제외한 전체면에 형성하여 이루어진 것을 특징으로 하는 반도체장치.
- 제 1 항에 있어서, 상기 실리콘질화막(16,37)이 상기 층간절연막의 최하층에 위치하고 있는 것을 특징으로 하는 반도체장치.
- 제 1 항에 있어서, 상기 실리콘질화막(16,37)의 막두께가 100nm이하인 것을 특징으로 하는 반도체장치.
- 사이드웰구조를 갖춘 트랜지스터를 적어도 한개 이상 포함하고, 적어도 1층의 실리콘질화막(16,37)으로 이루어진 층간절연막을 전극인출용 접촉개구부(18,39)를 제외한 전체면에 형성하여 이루어진 것을 특징으로 하는 반도체장치.
- 제 4 항에 있어서, 상기 실리콘질화막(16,37)이 상기 충절연막의 최하층에 위치하고 있는 것을 특징으로 하는 반도체장치.
- 제 4 항에 있어서, 상기 실리콘질화막(16,37)의 막두께가 100nm이하인 것을 특징으로 하는 반도체장치.
- 자외선소거형 MOS트랜지스터를 메모리셀로서 갖추고, 적어도 1층의 실리콘질화막(16)으로 이루어진 층간절연막을 전극인출용 접촉개구부(18)를 제외한 전체면에 형성하여 이루어진 것을 특징으로 하는 반도체장치.
- 제 7 항에 있어서, 상기 실리콘질화막(16)이 층간절연막의 최하층에 위치하고 있는 것을 특징으로 하는 반도체장치.
- 제 7 항에 있어서, 상기 실리콘질화막(16)의 막두께가 100nm이하인 것을 특징으로 하는 반도체장치.
- 최종보호막으로서 플라즈마 CVD절연막(42)이 설치되고, 적어도 1층의 실리콘질화막(37)으로 이루어진 층간절연막을 전극인출용 접촉개구부(39)를 제외한 전체면에 형성되어 이루어진 것을 특징으로 하는 반도체장치.
- 제 10 항에 있어서, 상기 실리콘질화막(37)이 상기 층간절연막의 최하층에 위치하고 있는 것을 특징으로 하는 반도체장치.
- 제 10 항에 있어서, 상기 실리콘질화막(37)의 막두께가 100nm이하인 것을 특징으로 하는 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2027092A JPH03232231A (ja) | 1990-02-08 | 1990-02-08 | 半導体装置 |
JP02-027092 | 1990-02-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR910016103A true KR910016103A (ko) | 1991-09-30 |
Family
ID=12211435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910002123A KR910016103A (ko) | 1990-02-08 | 1991-02-08 | 반도체장치 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0441392A3 (ko) |
JP (1) | JPH03232231A (ko) |
KR (1) | KR910016103A (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04186675A (ja) * | 1990-11-16 | 1992-07-03 | Matsushita Electron Corp | 半導体装置 |
JP3886209B2 (ja) * | 1997-06-02 | 2007-02-28 | 貞夫 門倉 | 対向ターゲット式スパッタ装置 |
JP4340040B2 (ja) * | 2002-03-28 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5649570A (en) * | 1979-09-28 | 1981-05-06 | Hitachi Ltd | Semiconductor memory and its manufacturing process |
JPS61133656A (ja) * | 1984-12-03 | 1986-06-20 | Hitachi Ltd | 半導体装置およびその製造方法 |
ATE194882T1 (de) * | 1987-03-04 | 2000-08-15 | Advanced Micro Devices Inc | Passivationsschicht für integrierte schaltungsstruktur |
JPH0687483B2 (ja) * | 1988-02-13 | 1994-11-02 | 株式会社東芝 | 半導体装置 |
US4982250A (en) * | 1989-01-04 | 1991-01-01 | Motorola, Inc. | Mosture barrier for floating gate transistors |
-
1990
- 1990-02-08 JP JP2027092A patent/JPH03232231A/ja active Pending
-
1991
- 1991-02-08 KR KR1019910002123A patent/KR910016103A/ko not_active IP Right Cessation
- 1991-02-08 EP EP19910101762 patent/EP0441392A3/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0441392A2 (en) | 1991-08-14 |
EP0441392A3 (en) | 1991-10-16 |
JPH03232231A (ja) | 1991-10-16 |
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Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
SUBM | Submission of document of abandonment before or after decision of registration |