TW201740526A - 用於封裝上元件之電路之機械相容的以及導電及導熱的引線架 - Google Patents

用於封裝上元件之電路之機械相容的以及導電及導熱的引線架 Download PDF

Info

Publication number
TW201740526A
TW201740526A TW106113400A TW106113400A TW201740526A TW 201740526 A TW201740526 A TW 201740526A TW 106113400 A TW106113400 A TW 106113400A TW 106113400 A TW106113400 A TW 106113400A TW 201740526 A TW201740526 A TW 201740526A
Authority
TW
Taiwan
Prior art keywords
component
circuit
lead frame
package
module
Prior art date
Application number
TW106113400A
Other languages
English (en)
Other versions
TWI681523B (zh
Inventor
約翰大衛 布萊佐
佛雷德瑞克Ｅ 畢維爾
大衛Ａ 普魯特
Original Assignee
線性科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 線性科技股份有限公司 filed Critical 線性科技股份有限公司
Publication of TW201740526A publication Critical patent/TW201740526A/zh
Application granted granted Critical
Publication of TWI681523B publication Critical patent/TWI681523B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/1003—Non-printed inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10553—Component over metal, i.e. metal plate in between bottom of component and surface of PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/10757—Bent leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種封裝上元件電路可包括：用於電路的元件；及電路模組，附接至該元件。該電路模組可具有電路系統及至少一個引線架，該至少一個引線架將該電路系統皆電及熱地連接至該元件。該引線架可具有高度的導電性及導熱性兩者及非平坦的形狀，該非平坦形狀提供了以該電路模組之方向施加至該元件之力的彈簧狀緩衝。 一種製作封裝上元件電路的方法可包括以下步驟：將用於電路的元件附接至電路模組。該電路模組可具有電路系統及至少一個引線架，該至少一個引線架在該附接步驟之後將該電路系統皆電及熱地連接至該元件。該引線架可具有高度的導電性及導熱性兩者及非平坦的形狀，該非平坦形狀提供了以該電路模組之方向施加至該元件之力的彈簧狀緩衝。可在該電路模組已附接至該元件之後將該電路模組密封在模製材料中，同時不密封該元件。

Description

用於封裝上元件之電路之機械相容的以及導電及導熱的引線架
此揭示案關於高功率密度的封裝中系統（systems-in-package, SIP）或模組、需要低阻抗的封裝及具有高熱效能需求的封裝。此揭示案亦關於具有高功率/高電流應用的模組封裝，該等應用需要大的外部安裝的元件及/或改良的散熱。
使SIP具有增加的功率及電流效能且同時最小化它們在系統電路板設計內的覆蓋區的需要可能對於設計師及模組封裝工程師呈現了大量的設計約束及限制。
較高功率的元件可能需要大量的電路板空間且可能具有大的熱質量。例如，大的電感器可被整合進SIP，但模製的封裝的尺寸限制可能防止使用更大及更具功率能力的元件。由於它們的尺寸，該等大的元件可能不能被封進SIP內。它們亦可能需要盡量靠近SIP地附接在系統電路板上以最小化電路中的損失或雜訊。基於此理由，封裝設計及組裝方法學可能需要將更大的高功率的外部的有源及無源元件與模製的SIP整合，同時維持對於電路板上之佈局實體（real estate）的最小衝擊。
此外，較高功率的封裝及元件可能將較大量的熱散進它們的周圍事物（主要是散進系統電路板），將熱分散進相鄰的封裝及元件。此可能影響整體的系統效率及可靠度。該等高功率的封裝可能需要高電流路徑，該等路徑在不使用額外的金屬層、固態金屬的層間通孔（via）及昂貴的散熱裝置的情況下可能超過封裝基板及系統電路板的熱及電流承載容量。基於高功率模組封裝上的此額外需求，可能需要在SIP封裝主體內提供高度傳導性的熱及電路徑的技術，該路徑不取決於基板及系統電路板架構的限制。
一種封裝上元件電路可包括：用於電路的元件；及電路模組，附接至該元件。該電路模組可具有電路系統及至少一個引線架，該至少一個引線架將該電路系統皆電及熱地連接至該元件。該引線架可具有高度的導電性及導熱性兩者及非平坦的形狀，該非平坦形狀提供了以該電路模組之方向施加至該元件之力的彈簧狀緩衝。
一種製作封裝上元件電路的方法可包括以下步驟：將用於電路的元件附接至電路模組。該電路模組可具有電路系統及至少一個引線架，該至少一個引線架在該附接步驟之後將該電路系統皆電及熱地連接至該元件。該引線架可具有高度的導電性及導熱性兩者及非平坦的形狀，該非平坦形狀提供了以該電路模組之方向施加至該元件之力的彈簧狀緩衝。可在該電路模組已附接至該元件之後將該電路模組密封在模製材料中，同時不密封該元件。
藉由檢閱以下說明性實施例的詳細說明、隨附繪圖及申請專利範圍，該等以及其他元件、步驟、特徵、目的、益處及優點將變得清楚。
現描述說明性實施例。可補充性地或替代性地使用其他實施例。可能是清楚的或不必要的細節可被忽略以節省空間或以供更有效地進行說明。可在有額外元件或步驟及/或沒有所述之所有元件或步驟的情況下實踐某些實施例。
所揭露的是可整合機械相容的穿模的（through-mold）傳導性引線架以供熱及/或電互連大的高功率的外部附接的有源及無源元件的封裝設計及組裝方法學。
有源及/或無源元件可藉由使用嵌入在模組封裝內的內部引線架來附接至模製及/或未模製（unmolded）的SIP及具有完整電氣機能之模組的頂部。該等外部安裝的元件可與高度傳導性的引線架結合以提供用於散熱的額外熱路徑，且可強化熱特性及改良功率效率。
高度傳導性的引線架可為機械相容的及彈簧狀的。它們彈簧狀的行為可在組裝期間或之後吸收以模組的方向置於外部安裝的元件上的壓縮力，及/或可將該等力重定向為遠離基板、內部元件及/或受暴露的元件襯墊。
可藉由使用機械相容的引線架來提供電及/或熱路徑。引線架可經由模製化合物從模製的模組基板觸點內延伸以與內部元件接觸。引線架可延伸穿過到達模組的頂部以形成接觸墊以供連接至頂部安裝的有源或無源元件。
圖1A及圖1B繪示部分組裝的（圖1A）及完全組裝的（圖1B）封裝上元件（components-on-package, CoP）設備之實例的外部視圖。元件102可為附接至CoP模組封裝100之頂部的電感器或其他類型的無源或有源元件或元件集合。CoP模組封裝100可為完全模製的電路且可被建構為具有內部引線架，以形成一或更多個受暴露的金屬墊101以供電及/或熱連接至外部安裝的元件102。元件102可電、熱及/或機械地附接至封裝。
元件102可具有兩個接觸終端，且可電、熱及/或機械地附接至模組封裝的頂部。可藉由內部引線架來提供從模組到元件進行的電接連，該內部引線架可在塑性模製過程期間嵌在模組封裝內。
圖2繪示CoP模組封裝之實例的內部構造細節，該CoP模組封裝具有形成外部附接的元件104之電及/或熱路徑的內部引線架103。該實例可與圖1中所示的實例相同。引線架103可各為完成從基板上達元件104之電路的機械相容的穿模引線架，且可針對內部元件（例如具有受暴露墊的四扁平無導線（quad flat no-lead, QFN）封裝）提供額外的熱及電連接件105。引線架中的一或更多者亦可包含可各為圓形、卵形、矩形或任何其他形狀的一或更多個開口106。開口106可改良模製過程期間的塑性模製化合物流量及/或模製化合物的互鎖。
圖2中所繪示的內部引線架103可在模製過程之後各在模組頂表面處形成可焊接的接觸區域。它們亦可各提供從外部附接的元件104向下穿過模製化合物的高電流電連接件以連接到電路。
此引線架電路連接件可向下焊接到模組基板，且亦可連接至多個內部元件。此電路徑可提供供熱逸出模組封裝的熱路徑。
元件104可使用後模製SMT組裝過程藉由使用焊料及/或環氧樹脂附接材料來固定至模組頂部。黏著劑或其他類型的附接材料可用以針對額外的機械穩定性而將元件的主體附接至模組的塑性主體。
用以附接元件的焊料及環氧樹脂材料可為導電及/或導熱的，以提供通往模製的SIP的高電流（例如＞50安培）及高度導熱的連接件（例如＞每攝氏溫度每米25瓦特）。附接過程及材料可結合以提供足以在運作及可靠性測試期間的高溫熱循環下生存的壓制強度及熱工作特性。
元件104或多個元件可為無源及/或有源的。它們的數量可取決於由引線架設計所提供之穿模連接件的數量。
圖3A及圖3B及圖5圖示多封裝上元件（mCoP）設備的實例，該等多封裝上元件設備可包括電及/或熱附接至完全模製的SIP或模組之頂部的多個無源元件。
圖3A及圖3B繪示部分組裝的（圖3A）及完全組裝的（圖3B）多封裝上元件（multiple components-on-package, mCoP）設備之實例的外部視圖。附接的外部元件202可各為可附接至mCoP模組封裝200之頂部的電感器及/或其他類型的一或更多個元件。mCoP模組封裝200可為具有內部引線架的完全模製的電路，該等內部引線架形成一或更多個受暴露的墊201以供電及/或熱連接至外部元件202。外部元件可電、熱及/或機械附接至模組封裝200。
圖4繪示mCoP模組封裝之另一實例的內部構造細節，該mCoP模組封裝可具有可形成通往一或更多個外部附接的元件連接件204之電及/或熱路徑的一或更多個內部引線架203。該實例可與圖3A及圖3B中所示的實例相同。一或更多個機械相容的穿模引線架206可完成從基板上達元件連接件204中的各者的電路，且可提供通往內部元件（例如QFN）的額外的熱及/或電連接件205。引線架206中的該一或更多者亦可包含可各為圓形、卵形、矩形或任何其他形狀的一或更多個開口206。開口206可改良模製過程期間的塑性模製化合物流及/或改良模製化合物的互鎖。
圖5繪示多封裝上元件（mCoP）設備之另一實例的外部視圖，該多封裝上元件設備具有可附接至mCoP模組封裝300之頂部的四個單獨元件302。mCoP模組封裝300可為具有內部引線架的完全模製的電路，該等內部引線架形成受暴露的墊301以供電及/或熱連接至所有外部元件302。所有外部元件302可經由引線架電、熱及/或機械附接至封裝。可替代地使用不同數量的元件。
圖6繪示mCoP模組封裝的另一實例的內部構造細節，該mCoP模組封裝具有可形成外部附接的元件連接件304之電及/或熱路徑的機械相容的內部引線架303。該實例可與圖5中所示的實例相同。機械相容的穿模引線架可完成從基板上達元件的電路，且可提供內部元件的額外的熱及/或電連接件305。引線架中的一或更多者亦可包含可為圓形、卵形、矩形或任何其他形狀的開口306。該等開口306可改良模製過程期間的塑性模製化合物流及/或模製化合物的互鎖。
所採用的引線架（圖4及圖6）可針對各個附接的元件提供電及/或熱路徑，且可具有開口，該等開口可藉由強化塑性模製過程期間的模製流量及/或藉由將引線架模鎖（mold lock）在模製的結構內提供額外的機械穩定性來協助組裝過程。引線架設計亦可針對各元件的完整機能提供所有元件導線的絕緣及個別的連接件，如由模組封裝內之電路的功能所需求的。
圖7繪示多封裝上元件（mCoP）設備400之另一實例的外部視圖，該多封裝上元件設備可具有附接至模組封裝400之頂部的多個有源及/或無源元件402。mCoP模組封裝400可為具有內部引線架的完全模製的電路，該等內部引線架形成受暴露的墊401以供電及/或熱連接至一或更多個外部附接的元件402。
圖8繪示mCoP模組封裝之另一實例的內部構造細節，該mCoP模組封裝可具有形成外部附接的元件連接件404之電及/或熱路徑的內部引線架403。該實例可與圖7中所示的實例相同。機械相容的穿模引線架406可完成從基板上達元件的電路，且可提供內部元件的額外的熱及/或電連接件405。引線架406中的一或更多者可包含可各為圓形、卵形、矩形或任何其他形狀的開口。該等開口406可改良模製過程期間的塑性模製化合物流及/或模製化合物的互鎖。
圖7及圖8圖示mCoP設備的實例，該mCoP設備具有附接至模組封裝之頂面的多個有源及/或無源元件。此設備可能需要更複雜的引線架設計及/或後模製處理及/或後模製加工，但可提供如本文中先前所揭露的全部相同的功能特性。
在針對mCoP的適當電路運作而需要進一步電氣絕緣的情況下，一旦引線架被嵌在模製化合物內，可執行引線架的額外的加工及/或蝕刻。此加工步驟可包括藉由機械及電氣的手段來對於嵌入/附接的引線架進行添加性及減去性更改兩者。例如，研磨機、雷射加工、化學蝕刻及/或鋸蝕引線架的步驟可用以獲取外部安裝的元件的絕緣及/或路由的（routed）連接件。
已描述的機械相容的內部引線架可提供分佈在模組內之內部元件及電路以及附接的外部元件之間的導電及/或導熱路徑。角彎曲（angular bend）可在準確的位置處，且可用以解耦及重新分散肇因於組裝及模製包裝壓力的任何向下力，該向下力原本可能損傷基板及/或附接的元件。引線架中的開口可為圓形、卵形、矩形或任何其他形狀，且可促進模鎖、模流（mold flow）、及/或最小化模具空隙及/或防止大的剝層區域。
引線架亦可在包含薄化區域（一般是被加工及/或蝕刻所移除之厚度的一半）的各側上沿長度具有各種區域。該等半蝕刻的特徵可被提供在特定位置處以進一步減少後續回流期間的剝層的機會及其他可靠性相關的考量。
已論述的元件、步驟、特徵、目的、益處及優點僅為說明性的。它們或關於它們的論述沒有一個是要用來以任何方式限制保護範圍。亦考慮許多其他實施例。該等包括具有更少、額外及/或不同元件、步驟、特徵、目的、益處及/或優點的實施例。該等亦包括不同地佈置及/或排序之元件及/或步驟的實施例。
例如，內部引線架可用以在模組封裝內重新分佈電氣訊號，有效地在元件之間提供額外的訊號層。該等內部引線架會不一定需要暴露於封裝的頂表面。該等引線架可被視為中間傳導層，該等中間傳導層可用以橋接來自在封裝之一側處之元件的電氣訊號且延伸在許多內部元件上方以製作通往封裝之另一側處之其他元件的高電流連接件。形成從倒裝晶片（flip chip）矽晶粒的背側通往其他內部元件之內部連接件的引線架會是一個實例。將垂直的FET連接在一起及連接到基板會是另一實例。另一實例會是跨越封裝長度的整個距離以針對任何數量的元件提供電及熱連接件的引線架。
為了元件的表面連接而被暴露及/或顯露的內部引線架亦可形成通往外部散熱材料（例如散熱器、熱管及/或其他的導電及/或導熱材料）的連接件。例如為該等連接件的連接件可進一步強化從封裝內進行的散熱，且可能允許在較高的功率密度及電流下運作。
已描述者的變型可包括針對基板、內部元件及/或外部元件的各種附接方法。該等方法可包括（但不限於）對於熱及/或電力是傳導性或非傳導性的環氧樹脂、焊料及/或任何黏著劑。並且，內部引線架可包括可針對封裝的相關運作形成傳導路徑的任何數量的多個引線架及/或結構。引線架結構可連接/附接至中介層（interposer）、扣具、金屬支座（stand-off）及/或能夠針對熱及/或電力提供傳導路徑之材料結構的任何變型。外部安裝/附接的元件可包括（但不限於）無源元件、有源元件及/或導熱及/或導電材料的任何變型以包括散熱設備、熱管、中間冷卻器及/或外部附接的帕耳帖（Peltier）及/或能量收集及控制設備。
除非另有敘述，此說明書中所闡述、包括在以下請求項中的所有量測、值、等級、位置、幅度、尺寸及其他規格是近似的而非精確的。它們要具有與它們所相關的功能一致且與它們所屬領域中所慣用者一致的合理範圍。
已於此揭示案中所引用的所有文章、專利、專利申請案及其他出版品係以引用方式併入本文中。
用句「用於...的手段」當用於請求項中時係欲且應被解讀為包括已描述的相對應結構及材料及它們的等效物。類似地，用句「用於...的步驟」當用於請求項中時係欲且應被解讀為包括已描述的相對應行動及它們的等效物。請求項沒有出現該等用句意指該請求項不欲且不應被解讀為受限於該等相對應結構、材料或行動，或受限於它們的等效物。
保護範圍僅由就在以下的請求項所限制。當基於此說明書及以下的審查歷史來解讀時（除非已闡述特定意義），該範圍係欲且應被解讀為如同與請求項中所使用之語言的通常意義一致一樣地寬廣，且包括所有結構性及功能性等效物。
在不一定需要或不暗示實體或動作間之任何實際關係或順序的情況下，關係性用詞例如「第一」及「第二」及類似物可僅用以從另一實體或動作區隔一個實體或動作。用詞「包括」、「包含」及其任何其他變型當在說明書或請求項中與構件清單結合使用時，係欲指示該清單係非排他性的，且可包括其他構件。類似地，前置「一（a/an）」的構件在無進一步約束的情況下並不排除相同類型之額外構件的存在。
請求項中沒有一個是欲包括無法滿足專利法之需求的標的，或不應以此種方式來解讀。特此否認如此標的的任何不要的涵蓋範圍。除了如此段落中剛敘述的，已敘述或說明者係完全不欲或不應被解讀為使得將任何元件、步驟、特徵、目的、益處、優點或等效物貢獻給公眾，無論其是否載於請求項中。
係提供摘要以幫助讀者快速探明技術揭示的本質。係在了解摘要將不用以解讀或限制請求項的範圍或意義的情況下提出該摘要。此外，上述詳細說明中的各種特徵係在各種實施例中群集在一起以精簡本揭示案。此揭示方法不應被解讀為相較於各請求項中所明確記載的而言要所請求的實施例需要更多特徵。事實上，如以下的請求項所反映的，進步性的標的係在於少於單一揭露實施例的所有特徵。因此，在各請求項本身如同單獨請求的標的的情況下，特此將以下請求項併入詳細說明。
100‧‧‧CoP模組封裝 101‧‧‧受暴金屬墊 102‧‧‧元件 103‧‧‧內部引線架 104‧‧‧元件 105‧‧‧熱及電連接件 106‧‧‧開口 200‧‧‧mCoP模組封裝 201‧‧‧受暴露的墊 202‧‧‧外部元件 203‧‧‧內部引線架 204‧‧‧外部附接的元件連接件 205‧‧‧熱及/或電連接件 206‧‧‧機械相容的穿模引線架 300‧‧‧mCoP模組封裝 301‧‧‧受暴露的墊 302‧‧‧外部元件 303‧‧‧機械相容的內部引線架 304‧‧‧外部附接的元件連接件 305‧‧‧熱及/或電連接件 306‧‧‧開口 400‧‧‧mCoP模組封裝 401‧‧‧受暴露的墊 402‧‧‧外部附接的元件 403‧‧‧內部引線架 404‧‧‧外部附接的元件連接件 405‧‧‧熱及/或電連接件 406‧‧‧機械相容的穿模引線架
繪圖係屬於說明性實施例。它們並不繪示所有實施例。可補充地或替代性地使用其他實施例。可能是顯而易見的或不必要的細節可被忽略以節省空間或以供更有效地進行說明。可在有額外元件或步驟及/或沒有所繪示之所有元件或步驟的情況下實踐某些實施例。當相同的標號出現在不同的繪圖中時，其指相同的或類似的元件或步驟。
圖1A及圖1B繪示部分組裝的（圖1A）及完全組裝的（圖1B）封裝上元件（components-on-package, CoP）設備之實例的外部視圖。
圖2繪示CoP模組封裝之實例的內部構造細節，該CoP模組封裝具有形成外部附接的元件之電及/或熱路徑的內部引線架。
圖3A及圖3B繪示部分組裝的（圖3A）及完全組裝的（圖3B）多封裝上元件（multiple components-on-package, mCoP）設備之實例的外部視圖。
圖4繪示mCoP模組封裝之另一實例的內部構造細節，該mCoP模組封裝可具有可形成通往一或更多個外部附接的元件連接件之電及/或熱路徑的一或更多個內部引線架。
圖5繪示多封裝上元件（mCoP）設備之另一實例的外部視圖，該多封裝上元件設備具有可附接至mCoP模組封裝之頂部的四個單獨元件。
圖6繪示mCoP模組封裝的另一實例的內部構造細節，該mCoP模組封裝具有可形成外部附接的元件連接件之電及/或熱路徑的機械相容的內部引線架。
圖7繪示多封裝上元件（mCoP）設備之另一實例的外部視圖，該多封裝上元件設備可具有附接至模組封裝之頂部的多個有源及/或無源元件。
圖8繪示mCoP模組封裝之另一實例的內部構造細節，該mCoP模組封裝可具有形成外部附接的元件連接件之電及/或熱路徑的內部引線架。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
(請換頁單獨記載) 無
103‧‧‧內部引線架
104‧‧‧元件
105‧‧‧熱及電連接件
106‧‧‧開口

Claims (15)

  1. 一種封裝上元件電路，包括： 用於一電路的一元件；及 一電路模組，附接至該元件，該電路具有： 電路系統；及 至少一個引線架，將該電路系統皆電及熱地連接至該元件，該引線架具有一高度的導電性及導熱性兩者及一非平坦的形狀，該非平坦形狀提供了以該電路模組的方向施加至元件之力的彈簧狀緩衝。
  2. 如請求項1所述之封裝上元件電路，其中該引線架具有電連接至該電路系統的至少一個腳。
  3. 如請求項2所述之封裝上元件電路，其中該引線架具有至少兩個相異的腳。
  4. 如請求項1所述之封裝上元件電路，其中該引線架具有電及熱連接至該元件的至少一個頂表面。
  5. 如請求項4所述之封裝上元件電路，其中該引線架具有至少兩個分離的頂表面，該等頂表面各附接至該元件。
  6. 如請求項1所述之封裝上元件電路，其中該引線架具有： 至少一個腳，電連接至該電路系統； 至少一個頂表面，電及熱連接至該元件；及 至少一個階梯，在該腳及該頂表面之間。
  7. 如請求項6所述之封裝上元件電路，其中該引線架具有至少兩個相異的階梯。
  8. 如請求項7所述之封裝上元件電路，其中該至少兩個相異的階梯處於該至少一個腳及該至少一個頂表面之間的不同高度。
  9. 如請求項7所述之封裝上元件電路，其中該至少兩個相異的階梯處於相同的高度。
  10. 如請求項1所述之封裝上元件電路，其中： 該電路模組具有一第二引線架，該第二引線架將該電路系統皆電及熱地連接至該元件；及 該第二引線架具有一高度的導電性及導熱性兩者及一非平坦的形狀，該非平坦形狀提供了以該電路模組之方向施加至該元件之力的彈簧狀緩衝。
  11. 如請求項1所述之封裝上元件電路，其中： 包括該引線架的該電路模組被密封在模製材料中；及 該引線架具有不被該模製材料覆蓋的一頂表面。
  12. 如請求項11所述之封裝上元件電路，其中該元件亦不被該模製材料密封。
  13. 如請求項1所述之封裝上元件電路，其中該元件為一無源元件。
  14. 如請求項13所述之封裝上元件電路，其中該無源元件為一電感器。
  15. 一種製作一封裝上元件電路的方法，包括以下步驟： 將用於一電路的一元件附接至一電路模組，該電路模組具有電路系統及至少一個引線架，該至少一個引線架在該附接步驟之後將該電路系統皆電及熱地連接至該元件，該引線架具有一高度的導電性及導熱性兩者及一非平坦的形狀，該非平坦形狀提供了以該電路模組的方向施加至元件之力的彈簧狀緩衝；及 在該電路模組已附接至該元件之後將該電路模組密封在模製材料中，同時不密封該元件。
TW106113400A 2016-04-26 2017-04-21 用於封裝上元件之電路之機械相容的以及導電及導熱的引線架 TWI681523B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662327875P 2016-04-26 2016-04-26
US62/327,875 2016-04-26

Publications (2)

Publication Number Publication Date
TW201740526A true TW201740526A (zh) 2017-11-16
TWI681523B TWI681523B (zh) 2020-01-01

Family

ID=58610047

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106113400A TWI681523B (zh) 2016-04-26 2017-04-21 用於封裝上元件之電路之機械相容的以及導電及導熱的引線架

Country Status (5)

Country Link
US (2) US11272618B2 (zh)
EP (1) EP3449502B1 (zh)
CN (1) CN109075151B (zh)
TW (1) TWI681523B (zh)
WO (1) WO2017189224A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
JP7211267B2 (ja) * 2019-05-29 2023-01-24 株式会社デンソー 半導体パッケージの製造方法
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Family Cites Families (309)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4089041A (en) 1975-08-07 1978-05-09 Amp Incorporated Circuit programming device
JPS59155154A (ja) 1983-02-23 1984-09-04 Nec Corp 半導体装置
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
JPS6273650A (ja) * 1985-09-27 1987-04-04 Hitachi Ltd 電気部品
US4914259A (en) 1987-09-08 1990-04-03 The Furukawa Electric Co., Ltd. Molded circuit board
JPH0513666A (ja) 1991-06-29 1993-01-22 Sony Corp 複合半導体装置
US5535101A (en) 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
US5482898A (en) * 1993-04-12 1996-01-09 Amkor Electronics, Inc. Method for forming a semiconductor device having a thermal dissipator and electromagnetic shielding
US5647124A (en) * 1994-04-25 1997-07-15 Texas Instruments Incorporated Method of attachment of a semiconductor slotted lead to a substrate
US5514907A (en) 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
KR0148082B1 (ko) 1995-08-16 1998-08-01 김광호 지지 바를 사용한 적층형 반도체 패키지 및 적층형 패키지 소켓
US5804880A (en) * 1996-11-04 1998-09-08 National Semiconductor Corporation Solder isolating lead frame
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US20040124505A1 (en) * 2002-12-27 2004-07-01 Mahle Richard L. Semiconductor device package with leadframe-to-plastic lock
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
US20050095835A1 (en) 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
JP4700332B2 (ja) * 2003-12-05 2011-06-15 イビデン株式会社 多層プリント配線板
JP2006100385A (ja) 2004-09-28 2006-04-13 Rohm Co Ltd 半導体装置
US7394150B2 (en) * 2004-11-23 2008-07-01 Siliconix Incorporated Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys
JP5123664B2 (ja) 2005-09-28 2013-01-23 スパンション エルエルシー 半導体装置およびその製造方法
US7285849B2 (en) 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
CN101326636A (zh) * 2005-12-09 2008-12-17 飞兆半导体公司 用于组装顶部与底部暴露的封装半导体的装置和方法
US7663212B2 (en) * 2006-03-21 2010-02-16 Infineon Technologies Ag Electronic component having exposed surfaces
US7859098B2 (en) 2006-04-19 2010-12-28 Stats Chippac Ltd. Embedded integrated circuit package system
TWI451561B (zh) 2006-05-02 2014-09-01 Nxp Bv 包括經改進電極之電子裝置
US7569920B2 (en) * 2006-05-10 2009-08-04 Infineon Technologies Ag Electronic component having at least one vertical semiconductor power transistor
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US7977773B1 (en) * 2006-07-17 2011-07-12 Marvell International Ltd. Leadframe including die paddle apertures for reducing delamination
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US20080122049A1 (en) * 2006-11-28 2008-05-29 Texas Instruments Incorporated Leadframe finger design to ensure lead-locking for enhanced fatigue life of bonding wire in an overmolded package
US20080128890A1 (en) 2006-11-30 2008-06-05 Advanced Semiconductor Engineering, Inc. Chip package and fabricating process thereof
KR100818518B1 (ko) 2007-03-14 2008-03-31 삼성전기주식회사 Ｌｅｄ 패키지
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
JP5195903B2 (ja) 2008-03-31 2013-05-15 株式会社村田製作所 電子部品モジュール及び該電子部品モジュールの製造方法
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
US7842542B2 (en) 2008-07-14 2010-11-30 Stats Chippac, Ltd. Embedded semiconductor die package and method of making the same using metal frame carrier
US7829981B2 (en) 2008-07-21 2010-11-09 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8354740B2 (en) 2008-12-01 2013-01-15 Alpha & Omega Semiconductor, Inc. Top-side cooled semiconductor package with stacked interconnection plates and method
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
US8062932B2 (en) * 2008-12-01 2011-11-22 Alpha & Omega Semiconductor, Inc. Compact semiconductor package with integrated bypass capacitor and method
US8168458B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices
US9257356B2 (en) 2008-12-10 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming an IPD beneath a semiconductor die with direct connection to external devices
US7741148B1 (en) 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US7776655B2 (en) 2008-12-10 2010-08-17 Stats Chippac, Ltd. Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices
US7799602B2 (en) 2008-12-10 2010-09-21 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
US8900921B2 (en) 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
JP2012064600A (ja) 2008-12-12 2012-03-29 Murata Mfg Co Ltd 多層基板およびその製造方法
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8093151B2 (en) 2009-03-13 2012-01-10 Stats Chippac, Ltd. Semiconductor die and method of forming noise absorbing regions between THVS in peripheral region of the die
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US8067308B2 (en) 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
US7993976B2 (en) 2009-06-12 2011-08-09 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias with trench in saw street
US8003496B2 (en) 2009-08-14 2011-08-23 Stats Chippac, Ltd. Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8164158B2 (en) 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US20120326287A1 (en) 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US8531012B2 (en) 2009-10-23 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
TWI581384B (zh) 2009-12-07 2017-05-01 英特希爾美國公司 堆疊式電子電感封裝組件及其製造技術
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8138014B2 (en) 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8574960B2 (en) 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US8368187B2 (en) 2010-02-03 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming air gap adjacent to stress sensitive region of the die
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9922955B2 (en) 2010-03-04 2018-03-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP
US8241956B2 (en) 2010-03-08 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level multi-row etched lead package
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US20110241194A1 (en) 2010-04-02 2011-10-06 Advanced Semiconductor Engineering, Inc. Stacked Semiconductor Device Package Assemblies with Reduced Wire Sweep and Manufacturing Methods Thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US9508626B2 (en) 2010-04-23 2016-11-29 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height
FR2959350B1 (fr) 2010-04-26 2012-08-31 Commissariat Energie Atomique Procede de fabrication d?un dispositif microelectronique et dispositif microelectronique ainsi fabrique
US8241964B2 (en) 2010-05-13 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
US8582317B2 (en) * 2010-05-26 2013-11-12 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
US8525340B2 (en) 2010-06-11 2013-09-03 Premitec, Inc. Flexible electronic devices and related methods
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8642381B2 (en) 2010-07-16 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die
US9831393B2 (en) 2010-07-30 2017-11-28 Cree Hong Kong Limited Water resistant surface mount device package
US8318541B2 (en) 2010-08-10 2012-11-27 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435835B2 (en) 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
US8409918B2 (en) 2010-09-03 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming pre-molded substrate to reduce warpage during die mounting
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
US9337116B2 (en) 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US8546193B2 (en) 2010-11-02 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8384227B2 (en) 2010-11-16 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
US8877567B2 (en) 2010-11-18 2014-11-04 Stats Chippac, Ltd. Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die
US8288202B2 (en) 2010-11-22 2012-10-16 STATS ChiPAC, Ltd. Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die
JP5707902B2 (ja) * 2010-12-02 2015-04-30 ソニー株式会社 半導体装置及びその製造方法
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8445990B2 (en) 2010-12-10 2013-05-21 Stats Chippac, Ltd. Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor die
US20120159118A1 (en) 2010-12-16 2012-06-21 Wong Shaw Fong Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
CN201893335U (zh) * 2010-12-24 2011-07-06 安徽国晶微电子有限公司 一种双芯片集成电路引线框
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
US8525344B2 (en) 2011-02-24 2013-09-03 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires between semiconductor die contact pads and conductive TOV in peripheral area around semiconductor die
US8623702B2 (en) 2011-02-24 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8569882B2 (en) 2011-03-24 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof
US8883561B2 (en) 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9391046B2 (en) 2011-05-20 2016-07-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer
US8409979B2 (en) 2011-05-31 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
US8288209B1 (en) 2011-06-03 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
US9006099B2 (en) 2011-06-08 2015-04-14 Great Wall Semiconductor Corporation Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump
US8674516B2 (en) 2011-06-22 2014-03-18 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
US8587120B2 (en) 2011-06-23 2013-11-19 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure
US20130015569A1 (en) 2011-07-12 2013-01-17 Great Wall Semiconductor Corporation Semiconductor Device and Method of Forming Substrate With Seated Plane for Mating With Bumped Semiconductor Die
US9324659B2 (en) 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US8653635B2 (en) 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
US20140151880A1 (en) 2011-08-19 2014-06-05 Marvell World Trade Ltd. Package-on-package structures
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US9275877B2 (en) 2011-09-20 2016-03-01 Stats Chippac, Ltd. Semiconductor device and method of forming semiconductor package using panel form carrier
US9484259B2 (en) 2011-09-21 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US9824923B2 (en) 2011-10-17 2017-11-21 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming conductive pillar having an expanded base
US9281228B2 (en) 2011-11-01 2016-03-08 Stats Chippac, Ltd. Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor die
US20130127029A1 (en) * 2011-11-18 2013-05-23 Texas Instruments Incorporated Two level leadframe with upset ball bonding surface and device package
US8642384B2 (en) 2012-03-09 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
US9245834B2 (en) 2012-03-16 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
US20130249076A1 (en) 2012-03-20 2013-09-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
US9082780B2 (en) 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US8946880B2 (en) * 2012-03-23 2015-02-03 Texas Instruments Incorporated Packaged semiconductor device having multilevel leadframes configured as modules
US9390945B2 (en) 2012-05-08 2016-07-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing underfill material with uniform flow rate
US9406579B2 (en) 2012-05-14 2016-08-02 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage in semiconductor package
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8847369B2 (en) 2012-07-20 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging structures and methods for semiconductor devices
US9978654B2 (en) 2012-09-14 2018-05-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP
US9559039B2 (en) 2012-09-17 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
US9385102B2 (en) 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US9773719B2 (en) 2012-11-26 2017-09-26 Infineon Technologies Dresden Gmbh Semiconductor packages and methods of fabrication thereof
US9704780B2 (en) 2012-12-11 2017-07-11 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US9240331B2 (en) 2012-12-20 2016-01-19 Stats Chippac, Ltd. Semiconductor device and method of making bumpless flipchip interconnect structures
US10115661B2 (en) 2013-02-08 2018-10-30 Qualcomm Incorporated Substrate-less discrete coupled inductor structure
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US8786069B1 (en) 2013-03-15 2014-07-22 Invensas Corporation Reconfigurable pop
KR20140126598A (ko) 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9006870B2 (en) 2013-07-31 2015-04-14 Alpha & Omega Semiconductor Inc. Stacked multi-chip packaging structure and manufacturing method thereof
KR102161173B1 (ko) 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US9070627B2 (en) 2013-09-11 2015-06-30 Broadcom Corporation Interposer package-on-package structure
US10418298B2 (en) 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
US9299650B1 (en) 2013-09-25 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
CN103633056B (zh) 2013-12-06 2017-09-01 矽力杰半导体技术(杭州)有限公司 引线框、封装组件及其制造方法
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
CN105765711A (zh) 2013-12-23 2016-07-13 英特尔公司 封装体叠层架构以及制造方法
CN203839367U (zh) * 2013-12-31 2014-09-17 福建合顺微电子有限公司 一种带有脱离与锁定组合槽引线框架的半导体器件
MY171261A (en) * 2014-02-19 2019-10-07 Carsem M Sdn Bhd Stacked electronic packages
TWI541966B (zh) 2014-03-05 2016-07-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法
CN104934391B (zh) 2014-03-18 2018-05-18 日月光半导体制造股份有限公司 半导体装置和半导体工艺
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9330994B2 (en) 2014-03-28 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
US20150279815A1 (en) 2014-03-28 2015-10-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Having Conductive Columns
TWI587412B (zh) 2014-05-08 2017-06-11 矽品精密工業股份有限公司 封裝結構及其製法
TWI529883B (zh) 2014-05-09 2016-04-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法暨無核心層式封裝基板及其製法
US9881859B2 (en) 2014-05-09 2018-01-30 Qualcomm Incorporated Substrate block for PoP package
US9768066B2 (en) 2014-06-26 2017-09-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming conductive vias by direct via reveal with organic passivation
US10115701B2 (en) 2014-06-26 2018-10-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming conductive vias by backside via reveal with CMP
KR101736461B1 (ko) 2014-07-07 2017-05-16 인텔 아이피 코포레이션 패키지-온-패키지 적층형 초소형전자 구조물
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
TWI599007B (zh) 2014-09-03 2017-09-11 矽品精密工業股份有限公司 電子單體及其製法
KR102181013B1 (ko) 2014-09-05 2020-11-19 삼성전자주식회사 반도체 패키지
US9941207B2 (en) 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
TWI548050B (zh) 2014-11-03 2016-09-01 矽品精密工業股份有限公司 封裝結構及其製法與封裝基板
EP3018092A1 (en) 2014-11-10 2016-05-11 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft MEMS package
US9986646B2 (en) 2014-11-21 2018-05-29 Nxp Usa, Inc. Packaged electronic devices with top terminations, and methods of manufacture thereof
US10032652B2 (en) 2014-12-05 2018-07-24 Advanced Semiconductor Engineering, Inc. Semiconductor package having improved package-on-package interconnection
TWI560818B (en) 2014-12-05 2016-12-01 Siliconware Precision Industries Co Ltd Electronic package and the manufacture thereof
KR102506703B1 (ko) 2014-12-16 2023-03-03 데카 테크놀로지 유에스에이 인코포레이티드 반도체 패키지를 마킹하는 방법
WO2016099523A1 (en) 2014-12-19 2016-06-23 Intel IP Corporation Stacked semiconductor device package with improved interconnect bandwidth
US9443785B2 (en) 2014-12-19 2016-09-13 Advanced Semiconductor Engineering, Inc. Semiconductor package
US9496238B2 (en) 2015-02-13 2016-11-15 Advanced Semiconductor Engineering, Inc. Sloped bonding structure for semiconductor package
US9786623B2 (en) 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
TWI587458B (zh) 2015-03-17 2017-06-11 矽品精密工業股份有限公司 電子封裝件及其製法與基板結構
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US20160307799A1 (en) 2015-04-15 2016-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor substrates, semiconductor packages and processes of making the same
US9397074B1 (en) 2015-04-29 2016-07-19 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9502397B1 (en) 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US10163687B2 (en) 2015-05-22 2018-12-25 Qualcomm Incorporated System, apparatus, and method for embedding a 3D component with an interconnect structure
US9653407B2 (en) 2015-07-02 2017-05-16 Advanced Semiconductor Engineering, Inc. Semiconductor device packages
US10290414B2 (en) 2015-08-31 2019-05-14 Qualcomm Incorporated Substrate comprising an embedded inductor and a thin film magnetic core
US10784208B2 (en) 2015-09-10 2020-09-22 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
TWI712187B (zh) 2015-09-11 2020-12-01 晶元光電股份有限公司 發光元件以及其製造方法
US20170110392A1 (en) 2015-10-15 2017-04-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same structure
US10163867B2 (en) 2015-11-12 2018-12-25 Amkor Technology, Inc. Semiconductor package and manufacturing method thereof
US10083888B2 (en) 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
DE102015121044B4 (de) 2015-12-03 2020-02-06 Infineon Technologies Ag Anschlussblock mit zwei Arten von Durchkontaktierungen und elektronische Vorrichtung, einen Anschlussblock umfassend
CN108352379B (zh) 2015-12-21 2022-05-17 英特尔公司 系统级封装装置以及用于形成系统级封装装置的方法
US20170179041A1 (en) 2015-12-22 2017-06-22 Intel Corporation Semiconductor package with trenched molding-based electromagnetic interference shielding
TWI641087B (zh) 2015-12-28 2018-11-11 矽品精密工業股份有限公司 電子封裝件及封裝用之基板
US9741694B2 (en) 2015-12-31 2017-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method of manufacturing the same
TWI605557B (zh) 2015-12-31 2017-11-11 矽品精密工業股份有限公司 電子封裝件及其製法與基板結構
TWI582928B (zh) 2016-01-19 2017-05-11 矽品精密工業股份有限公司 基板結構及其製法
US10497674B2 (en) 2016-01-27 2019-12-03 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US10193442B2 (en) 2016-02-09 2019-01-29 Faraday Semi, LLC Chip embedded power converters
US9729059B1 (en) 2016-02-09 2017-08-08 Faraday Semi, LLC Chip embedded DC-DC converter
US10256173B2 (en) 2016-02-22 2019-04-09 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US11373990B2 (en) 2016-02-29 2022-06-28 Semtech Corporation Semiconductor device and method of stacking semiconductor die for system-level ESD protection
TWI611577B (zh) 2016-03-04 2018-01-11 矽品精密工業股份有限公司 電子封裝件及半導體基板
EP3217774B1 (en) 2016-03-08 2018-06-13 ABB Schweiz AG Semiconductor module
WO2017160284A1 (en) 2016-03-16 2017-09-21 Intel Corporation Stairstep interposers with integrated shielding for electronics packages
TWI589059B (zh) 2016-03-28 2017-06-21 矽品精密工業股份有限公司 電子封裝件
US9972579B1 (en) 2016-11-16 2018-05-15 Tdk Corporation Composite magnetic sealing material and electronic circuit package using the same
US10177099B2 (en) 2016-04-07 2019-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor package structure, package on package structure and packaging method
EP3449502B1 (en) * 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10049893B2 (en) 2016-05-11 2018-08-14 Advanced Semiconductor Engineering, Inc. Semiconductor device with a conductive post
US9985006B2 (en) 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9852971B1 (en) 2016-06-09 2017-12-26 Advanced Semiconductor Engineering, Inc. Interposer, semiconductor package structure, and semiconductor process
US10707157B2 (en) 2016-06-15 2020-07-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10186467B2 (en) 2016-07-15 2019-01-22 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10276382B2 (en) 2016-08-11 2019-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and stacked package assemblies including high density interconnections
US20180052281A1 (en) 2016-08-16 2018-02-22 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor device and semiconductor package structure
US10229859B2 (en) 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10037975B2 (en) 2016-08-31 2018-07-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
TWI601219B (zh) 2016-08-31 2017-10-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10475775B2 (en) 2016-08-31 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
TWI676259B (zh) 2016-09-02 2019-11-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10115692B2 (en) 2016-09-14 2018-10-30 International Business Machines Corporation Method of forming solder bumps
US20180090466A1 (en) 2016-09-29 2018-03-29 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10854556B2 (en) 2016-10-12 2020-12-01 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same
TWI595603B (zh) 2016-11-10 2017-08-11 矽品精密工業股份有限公司 封裝堆疊結構
US20180138113A1 (en) 2016-11-15 2018-05-17 Advanced Semiconductor Engineering, Inc. Semiconductor system and device package including interconnect structure
CN106558574A (zh) 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
US10381300B2 (en) 2016-11-28 2019-08-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package including filling mold via
US10700011B2 (en) 2016-12-07 2020-06-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
US10438889B2 (en) 2016-12-23 2019-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10535597B2 (en) 2017-01-13 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10157887B2 (en) 2017-03-09 2018-12-18 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10418332B2 (en) 2017-03-13 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming partition fence and shielding layer around semiconductor components
US10411766B2 (en) 2017-03-14 2019-09-10 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
TWI649839B (zh) 2017-03-15 2019-02-01 矽品精密工業股份有限公司 電子封裝件及其基板構造
WO2018182753A1 (en) 2017-04-01 2018-10-04 Intel Corporation Architectures and methods of fabricating 3d stacked packages
US10325868B2 (en) 2017-04-24 2019-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10381316B2 (en) 2017-05-10 2019-08-13 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10134677B1 (en) 2017-05-16 2018-11-20 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
TWI652787B (zh) 2017-05-25 2019-03-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10157821B1 (en) 2017-05-30 2018-12-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages
US9997447B1 (en) 2017-06-08 2018-06-12 Advanced Ssemiconductor Engineering, Inc. Semiconductor devices
CN109103167B (zh) 2017-06-20 2020-11-03 晟碟半导体（上海）有限公司 用于存储器装置的异构性扇出结构
US20180374798A1 (en) 2017-06-24 2018-12-27 Amkor Technology, Inc. Semiconductor device having emi shielding structure and related methods
US10229892B2 (en) 2017-06-28 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing a semiconductor package
WO2019004264A1 (ja) 2017-06-30 2019-01-03 株式会社村田製作所 電子部品モジュール及びその製造方法
US20190013301A1 (en) 2017-07-04 2019-01-10 Intel Corporation Stacked dies with passive components within facing recesses
US10224301B2 (en) 2017-07-05 2019-03-05 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10096578B1 (en) 2017-07-06 2018-10-09 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10978406B2 (en) 2017-07-13 2021-04-13 Mediatek Inc. Semiconductor package including EMI shielding structure and method for forming the same
US10522476B2 (en) 2017-07-18 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure, integrated fan-out package and method of fabricating the same
TW201911508A (zh) 2017-08-02 2019-03-16 矽品精密工業股份有限公司 電子封裝件
US10586751B2 (en) 2017-08-03 2020-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US11024569B2 (en) 2017-08-09 2021-06-01 Advanced Semiconducor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10453802B2 (en) 2017-08-30 2019-10-22 Advanced Semiconductor Engineering, Inc. Semiconductor package structure, semiconductor device and method for manufacturing the same
US10332862B2 (en) 2017-09-07 2019-06-25 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10468384B2 (en) 2017-09-15 2019-11-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
US10548249B2 (en) 2017-09-27 2020-01-28 Intel Corporation Shielding in electronic assemblies
WO2019066987A1 (en) 2017-09-30 2019-04-04 Intel Corporation STACK OF MULTIPLE MATERIALS WITH DIMENSION TOLERANCE
WO2019066986A1 (en) 2017-09-30 2019-04-04 Intel Corporation STACK OF NON-TSV CHIPS USING PLATED PILLARS / CROSSING MOLD INTERCONNECTION
US10515889B2 (en) 2017-10-13 2019-12-24 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10418314B2 (en) 2017-11-01 2019-09-17 Advanced Semiconductor Engineering, Inc. External connection pad for semiconductor device package
EP3481161A1 (en) 2017-11-02 2019-05-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with transistor components arranged side by side
KR102400101B1 (ko) 2017-11-03 2022-05-19 삼성전자주식회사 Pop 반도체 패키지 및 그를 포함하는 전자 시스템
US10714403B2 (en) 2017-11-03 2020-07-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package with patterned conductive layers and an interconnecting structure
US10629454B2 (en) 2017-11-08 2020-04-21 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
EP3483921A1 (en) 2017-11-11 2019-05-15 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding known-good component in known-good cavity of known-good component carrier material with pre-formed electric connection structure
US10546817B2 (en) 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support
US11335642B2 (en) 2017-12-29 2022-05-17 Intel Corporation Microelectronic assemblies
DE112017008333T5 (de) 2017-12-29 2020-09-10 Intel Corporation Mikroelektronische anordnungen
US11348897B2 (en) 2017-12-29 2022-05-31 Intel Corporation Microelectronic assemblies
US11494682B2 (en) 2017-12-29 2022-11-08 Intel Corporation Quantum computing assemblies
TWI643307B (zh) 2018-01-30 2018-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11004779B2 (en) 2018-02-09 2021-05-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
TWI645527B (zh) 2018-03-06 2018-12-21 矽品精密工業股份有限公司 電子封裝件及其製法
CN110299329A (zh) 2018-03-21 2019-10-01 华为技术有限公司 一种封装结构及其制作方法、电子设备
US10790161B2 (en) 2018-03-27 2020-09-29 Amkor Technology, Inc. Electronic device with adaptive vertical interconnect and fabricating method thereof
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11424195B2 (en) 2018-04-02 2022-08-23 Intel Corporation Microelectronic assemblies having front end under embedded radio frequency die
TWI647796B (zh) 2018-04-09 2019-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
US10811763B2 (en) 2018-04-11 2020-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11380609B2 (en) 2018-05-21 2022-07-05 Intel Corporation Microelectronic assemblies having conductive structures with different thicknesses on a core substrate
TWI688075B (zh) 2018-05-23 2020-03-11 矽品精密工業股份有限公司 電子封裝件
US11309192B2 (en) 2018-06-05 2022-04-19 Intel Corporation Integrated circuit package supports
US10861779B2 (en) 2018-06-22 2020-12-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an electrical contact with a high-melting-point part and method of manufacturing the same
US11227841B2 (en) 2018-06-28 2022-01-18 Intel Corporation Stiffener build-up layer package
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US10636756B2 (en) 2018-07-05 2020-04-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protrusion E-bar for 3D SIP
US20200051927A1 (en) 2018-08-13 2020-02-13 Mediatek Inc. Semiconductor device with an em-integrated damper
KR102509052B1 (ko) 2018-08-31 2023-03-10 에스케이하이닉스 주식회사 브리지 다이를 포함하는 스택 패키지
US11309294B2 (en) 2018-09-05 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US11605877B2 (en) 2018-09-07 2023-03-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11462463B2 (en) 2018-09-27 2022-10-04 Intel Corporation Microelectronic assemblies having an integrated voltage regulator chiplet
EP3633721A1 (en) 2018-10-04 2020-04-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with face-up and face-down embedded components
EP3633716A1 (en) 2018-10-05 2020-04-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Package with embedded electronic component being encapsulated in a pressureless way
US11244908B2 (en) 2018-11-06 2022-02-08 STATS ChipPAC Pte. Ltd. Method and device for reducing metal burrs when sawing semiconductor packages
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US10867929B2 (en) 2018-12-05 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US20200185293A1 (en) 2018-12-07 2020-06-11 Infineon Technologies Ag Semiconductor Package Having a Laser-Activatable Mold Compound
US11942334B2 (en) 2018-12-21 2024-03-26 Intel Corporation Microelectronic assemblies having conductive structures with different thicknesses
US11521914B2 (en) 2018-12-27 2022-12-06 Intel Corporation Microelectronic assemblies having a cooling channel
US10602612B1 (en) 2019-07-15 2020-03-24 Apple Inc. Vertical module and perpendicular pin array interconnect for stacked circuit board structure

Also Published As

Publication number Publication date
TWI681523B (zh) 2020-01-01
US20190141834A1 (en) 2019-05-09
EP3449502B1 (en) 2021-06-30
CN109075151A (zh) 2018-12-21
CN109075151B (zh) 2023-06-27
WO2017189224A1 (en) 2017-11-02
US11272618B2 (en) 2022-03-08
US20170311447A1 (en) 2017-10-26
EP3449502A1 (en) 2019-03-06

Similar Documents

Publication Publication Date Title
US6737750B1 (en) Structures for improving heat dissipation in stacked semiconductor packages
JP6122863B2 (ja) 複数の熱経路を備える積み重ねられた半導体ダイアセンブリ、ならびに関連するシステムおよび方法
KR101531746B1 (ko) 패키지 온 패키지 구조 및 패키지 온 패키지 구조를 형성하는 방법
KR102245003B1 (ko) 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
TWI681523B (zh) 用於封裝上元件之電路之機械相容的以及導電及導熱的引線架
CA2713151C (en) Semiconductor stack assembly having reduced thermal spreading resistance and methods of making same
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
US10658342B2 (en) Vertically stacked multichip modules
US9263375B2 (en) System, method and apparatus for leadless surface mounted semiconductor package
CN103378017A (zh) 高密度3d封装
US8610254B2 (en) Apparatus for integrated circuit packaging
US7999371B1 (en) Heat spreader package and method
CN103811436A (zh) 改进堆叠式封装结构中的逻辑芯片的热性能
CN103050454A (zh) 堆迭封装构造
US8946871B2 (en) Thermal improvement of integrated circuit packages
WO2022088179A1 (en) High power density 3d semiconductor module packaging
TWI820690B (zh) 功率模組及其製造方法
KR101708870B1 (ko) 적층형 반도체 패키지 및 이의 제조방법
TW201541574A (zh) 散熱型半導體立體封裝堆疊構造