JP7211267B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
- Publication number
- JP7211267B2 JP7211267B2 JP2019100522A JP2019100522A JP7211267B2 JP 7211267 B2 JP7211267 B2 JP 7211267B2 JP 2019100522 A JP2019100522 A JP 2019100522A JP 2019100522 A JP2019100522 A JP 2019100522A JP 7211267 B2 JP7211267 B2 JP 7211267B2
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- Prior art keywords
- lead frame
- semiconductor chip
- semiconductor package
- mold resin
- dimensional wiring
- Prior art date
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- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 7
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
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- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Description
第1実施形態の半導体パッケージP1およびこれを備える半導体装置S1について、図1~図3を参照して説明する。図1では、図2中のI-I間の断面構成を示している。図2では、見易くして理解を助けるため、後述のモールド樹脂7に覆われた各構成要素を実線で示すと共に、モールド樹脂7の外郭を二点鎖線で示している。また、図2では、平面視にて、前述の各構成要素のうち後述の立体配線6に隠れる部分を破線もしくは二点鎖線で示している。
次に、第2実施形態の半導体パッケージP2およびこれを用いた半導体装置S2について説明する。
次に、第2実施形態の半導体パッケージP2の変形例について、図7を参照して説明する。図7では、構成を分かり易くするため、後述する立体配線6A~6Dのうちモールド樹脂7に覆われた部分、および第2電子部品8に隠される部分の外郭をそれぞれ破線で示している。また、図7は、モールド樹脂7の上面7aに対する法線方向から見た上面レイアウト図である。
本発明は、実施例に準拠して記述されたが、本発明は当該実施例や構造に限定されるものではないと理解される。本発明は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらの一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本発明の範疇や思想範囲に入るものである。
てもよい。
Claims (3)
- 半導体パッケージ(P1、P2)の製造方法であって、
リードフレーム(1)に半導体チップ(2)を搭載することと、
複数の接続部(91)と、前記接続部に対して平行配置された複数の平坦部(92)と、前記平坦部から前記接続部とは反対側に延設され、複数の前記平坦部を連結する連結部(93)とを備える立体配線材(9)を用意することと、
前記立体配線材のうち前記接続部を前記リードフレームに接合材(3)を介して接続することと、
前記半導体チップおよび前記立体配線材を前記リードフレームに接続した後、前記リードフレームの一部、前記半導体チップおよび前記立体配線材を覆うモールド樹脂(7)を形成することと、
前記モールド樹脂の形成後、前記モールド樹脂のうち前記リードフレームとは反対側の面から切削して前記連結部を除去すると共に、前記平坦部の一面を前記モールド樹脂から露出させ、前記平坦部を端子部(63)とする二対以上の立体配線(6)を形成することと、を含む、半導体パッケージの製造方法。 - 前記半導体チップを前記リードフレームに接続した後、前記半導体チップと前記リードフレームの一部とをワイヤ(4)を用いてワイヤボンディングにより電気的に接続することをさらに含み、
前記リードフレームに前記半導体チップを搭載することにおいては、前記接合材を介して前記半導体チップを前記リードフレームに接続する、請求項1に記載の半導体パッケージの製造方法。 - 前記リードフレームに前記半導体チップを搭載することにおいては、バンプ(21)を備える前記半導体チップを用意し、前記バンプが前記リードフレームに当接するように前記半導体チップを配置し、フリップチップボンディングにより行う、請求項1に記載の半導体パッケージの製造方法。
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US20170311447A1 (en) | 2016-04-26 | 2017-10-26 | Linear Technology Corporation | Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits |
JP2018137466A (ja) | 2012-03-23 | 2018-08-30 | 日本テキサス・インスツルメンツ株式会社 | モジュールとして構成されるマルチレベルリードフレームを有するパッケージングされた半導体デバイス |
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JPH08330733A (ja) | 1995-05-30 | 1996-12-13 | Matsushita Electric Works Ltd | 多層プリント配線板 |
JPH09116263A (ja) | 1995-10-16 | 1997-05-02 | Shinko Electric Ind Co Ltd | 多層配線基板の製造方法 |
JP3983466B2 (ja) | 2000-10-04 | 2007-09-26 | 日本メクトロン株式会社 | 多層プリント基板の製造方法 |
JP4363947B2 (ja) | 2003-10-08 | 2009-11-11 | 富士通株式会社 | 多層配線回路基板およびその作製方法 |
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JP2008198660A (ja) | 2007-02-08 | 2008-08-28 | U-Ai Electronics Corp | プリント基板及びプリント基板の製造方法 |
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