TW200522328A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
TW200522328A
TW200522328A TW93135256A TW93135256A TW200522328A TW 200522328 A TW200522328 A TW 200522328A TW 93135256 A TW93135256 A TW 93135256A TW 93135256 A TW93135256 A TW 93135256A TW 200522328 A TW200522328 A TW 200522328A
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TW
Taiwan
Prior art keywords
semiconductor device
lead
sealing body
resin sealing
wire
Prior art date
Application number
TW93135256A
Other languages
English (en)
Chinese (zh)
Inventor
Nagahiro Fukaya
Toshiyuki Shintani
Hajime Hasebe
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200522328A publication Critical patent/TW200522328A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW93135256A 2003-12-25 2004-11-17 Semiconductor device and manufacturing method thereof TW200522328A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003430092A JP2005191240A (ja) 2003-12-25 2003-12-25 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW200522328A true TW200522328A (en) 2005-07-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW93135256A TW200522328A (en) 2003-12-25 2004-11-17 Semiconductor device and manufacturing method thereof

Country Status (5)

Country Link
US (2) US7410834B2 (enExample)
JP (1) JP2005191240A (enExample)
KR (1) KR20050065340A (enExample)
CN (1) CN1638111A (enExample)
TW (1) TW200522328A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI847658B (zh) * 2023-04-24 2024-07-01 強茂股份有限公司 具表面散熱結構的側面可濕潤半導體封裝元件及製法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US8330270B1 (en) * 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
JP4635471B2 (ja) * 2004-04-22 2011-02-23 ソニー株式会社 半導体装置及びその製造方法、半導体装置の実装構造並びにリードフレーム
JP5054923B2 (ja) * 2006-01-23 2012-10-24 Ｔｏｗａ株式会社 電子部品の樹脂封止成形方法
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8461694B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
JP2008016469A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置
JP4367476B2 (ja) * 2006-10-25 2009-11-18 株式会社デンソー モールドパッケージの製造方法
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
JP4872683B2 (ja) * 2007-01-29 2012-02-08 株式会社デンソー モールドパッケージの製造方法
JP2008187045A (ja) * 2007-01-30 2008-08-14 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームとその製造方法、半導体装置
JP2008218811A (ja) 2007-03-06 2008-09-18 Hitachi Metals Ltd 機能素子パッケージ
US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5549066B2 (ja) * 2008-09-30 2014-07-16 凸版印刷株式会社 リードフレーム型基板とその製造方法、及び半導体装置
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US10199311B2 (en) * 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
JP2010238693A (ja) * 2009-03-30 2010-10-21 Toppan Printing Co Ltd 半導体素子用基板の製造方法および半導体装置
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
JP5448727B2 (ja) * 2009-11-05 2014-03-19 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
CN102117753A (zh) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 封装半导体器件的方法
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
ITMI20120710A1 (it) * 2012-04-27 2013-10-28 St Microelectronics Srl Metodo per fabbricare dispositivi elettronici
US8841758B2 (en) * 2012-06-29 2014-09-23 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
US8716066B2 (en) 2012-07-31 2014-05-06 Freescale Semiconductor, Inc. Method for plating a semiconductor package lead
US8890301B2 (en) 2012-08-01 2014-11-18 Analog Devices, Inc. Packaging and methods for packaging
JP5959386B2 (ja) * 2012-09-24 2016-08-02 エスアイアイ・セミコンダクタ株式会社 樹脂封止型半導体装置およびその製造方法
US9070669B2 (en) 2012-11-09 2015-06-30 Freescale Semiconductor, Inc. Wettable lead ends on a flat-pack no-lead microelectronic package
US8535982B1 (en) 2012-11-29 2013-09-17 Freescale Semiconductor, Inc. Providing an automatic optical inspection feature for solder joints on semiconductor packages
KR101504897B1 (ko) * 2013-02-22 2015-03-23 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
US9589929B2 (en) * 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9190606B2 (en) * 2013-03-15 2015-11-17 Allegro Micosystems, LLC Packaging for an electronic device
US10345343B2 (en) 2013-03-15 2019-07-09 Allegro Microsystems, Llc Current sensor isolation
US20140299978A1 (en) * 2013-04-03 2014-10-09 Lingsen Precision Industries, Ltd. Quad flat non-lead package
US20140357022A1 (en) * 2013-06-04 2014-12-04 Cambridge Silicon Radio Limited A qfn with wettable flank
US9947636B2 (en) * 2014-06-02 2018-04-17 Stmicroelectronics, Inc. Method for making semiconductor device with lead frame made from top and bottom components and related devices
US20160148877A1 (en) * 2014-11-20 2016-05-26 Microchip Technology Incorporated Qfn package with improved contact pins
CN105895611B (zh) * 2014-12-17 2019-07-12 恩智浦美国有限公司 具有可湿性侧面的无引线方形扁平半导体封装
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices
JP6577857B2 (ja) 2015-12-21 2019-09-18 ルネサスエレクトロニクス株式会社 半導体装置
CN105470231A (zh) * 2015-12-25 2016-04-06 华天科技（西安）有限公司 一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法
US9806043B2 (en) * 2016-03-03 2017-10-31 Infineon Technologies Ag Method of manufacturing molded semiconductor packages having an optical inspection feature
JP6752639B2 (ja) 2016-05-02 2020-09-09 ローム株式会社 半導体装置の製造方法
US10388616B2 (en) 2016-05-02 2019-08-20 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP2018074067A (ja) * 2016-11-01 2018-05-10 旭化成エレクトロニクス株式会社 半導体装置
US9847283B1 (en) 2016-11-06 2017-12-19 Nexperia B.V. Semiconductor device with wettable corner leads
JP6841550B2 (ja) * 2017-05-29 2021-03-10 大口マテリアル株式会社 リードフレーム及びその製造方法
JP6917010B2 (ja) * 2017-09-06 2021-08-11 大日本印刷株式会社 半導体装置およびその製造方法
US10199312B1 (en) * 2017-09-09 2019-02-05 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
JP6423127B1 (ja) * 2017-11-10 2018-11-14 新電元工業株式会社 電子モジュール
JP7037368B2 (ja) * 2018-01-09 2022-03-16 ローム株式会社 半導体装置および半導体装置の製造方法
JP7144157B2 (ja) * 2018-03-08 2022-09-29 エイブリック株式会社 半導体装置およびその製造方法
US11600557B2 (en) * 2018-08-21 2023-03-07 Texas Instruments Incorporated Packaged device having selective lead pullback for dimple depth control
JP7210868B2 (ja) 2018-09-05 2023-01-24 ローム株式会社 半導体装置
CN109243988A (zh) * 2018-09-14 2019-01-18 上海凯虹科技电子有限公司 封装体及其封装方法
JP6827495B2 (ja) * 2019-05-16 2021-02-10 Ｔｏｗａ株式会社 半導体装置の製造方法
KR102363175B1 (ko) * 2020-04-06 2022-02-15 (주)포시스 반도체 패키지용 리드프레임의 리드 구조 및 그 리드 가공 방법
CN111668184B (zh) * 2020-07-14 2022-02-01 甬矽电子(宁波)股份有限公司 引线框制作方法和引线框结构
JPWO2022209819A1 (enExample) * 2021-04-01 2022-10-06
US11768230B1 (en) 2022-03-30 2023-09-26 Allegro Microsystems, Llc Current sensor integrated circuit with a dual gauge lead frame

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3153197B2 (ja) * 1998-12-24 2001-04-03 日本電気株式会社 半導体装置
JP2000294719A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP2000299400A (ja) 1999-04-14 2000-10-24 Sony Corp ノンリード・フラットパッケージ型半導体装置
JP3878781B2 (ja) * 1999-12-27 2007-02-07 株式会社ルネサステクノロジ 半導体装置の製造方法
US6452255B1 (en) * 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI847658B (zh) * 2023-04-24 2024-07-01 強茂股份有限公司 具表面散熱結構的側面可濕潤半導體封裝元件及製法

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