CN102117753A - 封装半导体器件的方法 - Google Patents

封装半导体器件的方法 Download PDF

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Publication number
CN102117753A
CN102117753A CN2010100021067A CN201010002106A CN102117753A CN 102117753 A CN102117753 A CN 102117753A CN 2010100021067 A CN2010100021067 A CN 2010100021067A CN 201010002106 A CN201010002106 A CN 201010002106A CN 102117753 A CN102117753 A CN 102117753A
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China
Prior art keywords
lead
lead frame
wire
saw
independent
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CN2010100021067A
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刘鹏
高勖
贺青春
齐兆彬
叶德洪
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN2010100021067A priority Critical patent/CN102117753A/zh
Priority to US12/830,424 priority patent/US20110165729A1/en
Publication of CN102117753A publication Critical patent/CN102117753A/zh
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Abstract

本发明涉及封装半导体器件的方法。使用具有不同宽度的两个不同锯片执行的两个拆分操作来制造方形扁平无引线封装器件，其中第一拆分操作使用宽于第二拆分操作的锯片。在拆分操作之间，用可焊接金属镀敷引线的暴露部分。通过在由第一拆分形成的第一切口内执行第二拆分操作，引线的暴露金属的至少一半保持被镀敷。因此，可以形成更好的焊点，这使得能够进行更简单的视觉检查。

Description

封装半导体器件的方法
技术领域
本发明总体上涉及半导体器件封装，并且更具体而言涉及对封装器件的引线框架进行镀敷(plate)并将其与其它封装器件的引线框架分离的方法。
背景技术
一直存在使诸如计算机、电视、立体声系统、蜂窝电话之类的电气设备更小的动力，这推动了对较小封装中的更加高度集成的半导体器件的需要。也就是说，存在对具有较小占位面积(footprint)的半导体器件的需要。一种半导体封装称为四方扁平封装(QFP)。图1是QFP器件10的侧视横截面图。QFP器件10包括半导体管芯12，其为用环氧树脂(epoxy)16附着于引线框架的薄层(flag)14的、在硅中形成的集成电路。管芯12通常通过导线结合工艺、用导线20电连接到引线18。管芯12、薄层14、导线20及引线18的一部分用塑料模塑化合物(plastic mold compound)22密封以便保护管芯12和导线20。引线18弯曲并伸出模塑化合物22的侧面。引线18使得QFP器件10能够附着到印刷电路板(未示出)以便连接到其它器件。器件的尺寸或占位面积用线A-A示出。
图2示出其中引线未延伸超过模塑化合物的不同但相似类型的封装。这类封装称为方形扁平无引线(QFN)封装。现在参照图2，示出了QFN器件30的放大横截面侧视图。QFN器件30包括具有其中形成有集成电路(IC)的半导体管芯32和使得能够连接到IC的多个导线结合焊盘。管芯32用诸如环氧树脂的粘合剂36附着于薄层34。IC结合焊盘通过导线40电连接到引线38，然后，管芯32、导线40及薄层34和引线38的顶面被模塑化合物或密封材料42覆盖。 通过除去外部引线，可以将封装占位面积减小几乎50％。线B-B指示器件30的占位面积，可以看到该占位面积比器件10的占位面积小得多(图1)。
引线38的远端和底面被露出以使得能够实现器件30到印刷电路板(PCB)的外部连接。然而，与QFP器件10不同，QFN器件30的焊点(solder joint)在封装下面形成。因此，用于检查焊点质量的传统视觉检查技术是困难且耗时的。例如，可能需要使PCB倾斜以检查焊点。可以执行光学和X射线检查，但是这些程序昂贵且需要专用设备。微切片是另一种检查焊点的方法，但这种方法实际上对生产检查没有用。因此，期望的是更容易地检查此类焊点。
图3是用于制造QFN器件30的方法的流程图。在第一步骤50中，用Sn或Pb等对引线框架进行镀敷。也就是说，引线框架(管芯焊盘和引线)通常由诸如铜箔的导电材料形成，并且通常通过切割、打孔、冲压或这些工艺的组合而由一片铜箔形成多个引线框架，随后将多个封装同时组装在一起。为了提供引线与PCB之间的良好结合，可以用诸如锡、镍、钯、或金的另一种材料对整个引线框架或其所选部分进行镀敷。在步骤52中，执行管芯附着、电连接、以及密封。在步骤54中，执行锯切拆分(saw singulation)以便同时将所形成的器件分离。在拆分操作中，使用旋转锯片将在引线框架阵列上形成的器件同时分离。然而，在锯切之后，引线框架的裸金属被暴露。也就是说，引线框架的未镀敷部分被暴露。
图4是按照常规制作的QFN器件下面的焊点的放大照片。该照片显示焊点、更精确地说是连接到引线框架的铜的焊料的延伸并不清晰，这是因为焊点制作到裸铜而不是镀敷表面上。因此，期望的是能够形成更清晰的焊点以便进行视觉检查。
附图说明
通过参考当前优选实施例的以下说明以及附图，可以最好地理解本发明以及其目的和优点。在附图中，相同的标记自始至终 用于相同的要素。
图1是传统QFP器件的放大横截面侧视图；
图2是传统QFN器件的放大横截面侧视图；
图3是制造图2的QFN器件的传统方法的流程图；
图4是在PCB与图2的QFN器件之间形成的焊点的放大照片；
图5是根据本发明的实施例的制造QFN器件的方法的流程图；
图6是在PCB与根据图5所示的工艺制造的QFN器件之间形成的焊点的放大照片；
图7A～7F示出依照本发明的实施例的拆分操作的步骤；以及
图8A～8D是依照本发明的实施例在拆分操作的各阶段的QFN器件的底面的放大照片。
本领域的技术人员应认识到图中的要素是为简单和明了而示出的，且不一定按比例绘制。例如，图中的某些要素的尺寸可以相对于其它要素被放大以帮助提高对本发明的实施例的理解。
具体实施方式
本发明以示例的方式示出且不受附图的限制，在附图中相同的附图标记指示类似的要素。
在一个实施例中，本发明提供了一种封装多个半导体器件的方法。该方法包括提供包括多个单独的引线框架的引线框架条。每个引线框架具有多个引线，且每个引线具有第一端部和第二端部。所述引线从大致为矩形的中心空间向外延伸。引线的第一端部接近于中心空间，而第二端部远离中心空间。一个或多个管芯焊盘被设置在中心空间中，且锯道(saw streets)位于所述多个引线框架的相邻引线框架之间。
所述方法包括分别在单独的引线框架的一个或多个管芯 焊盘中的相应的第一管芯焊盘上附着半导体管芯。每个管芯具有形成在其中的集成电路。接下来，将单独的引线框架的引线连接到管芯的相应的集成电路。随后用模塑化合物来密封单独的引线框架的半导体管芯、电连接和引线，但至少使引线的第二端部的底面暴露。沿着锯道用具有第一刀片(blade)宽度的第一锯片来执行第一拆分。第一拆分将引线框架的引线切割至第一深度。随后用可焊接金属来对引线框架的暴露部分进行镀敷。沿着锯道并在通过第一拆分形成的空间内用具有第二刀片宽度的第二锯片来执行第二拆分。第二拆分将引线框架相互分离，从而形成单独的半导体封装。
现在参照图5，示出了用于制造半导体器件的方法的流程图。该方法针对QFN型封装器件，然而，如本领域的技术人员将认识到的那样，所述方法可以在制造其它类型的封装器件时实施。在步骤60，提供引线框架。通常，该引线框架将是由延展性导电金属形成的引线框架阵列或引线框架条的一部分。在本实施例中，如本领域中已知的那样，通过打孔、冲压或切割而由一片铜箔形成引线框架。可以用诸如锡、锌、金、银或钯的可焊接金属来对铜引线框架进行镀敷。然而，因为依照本发明的实施例，在第一锯切拆分步骤之后对引线框架进行镀敷，因此不需要预先镀敷的引线框架。每个引线框架包括围绕大致的中心区域的多个引线。该中心区域可以包括管芯焊盘或薄层。该引线具有接近于管芯焊盘的第一端部和远离管芯焊盘的第二端部或远端。引线可以在一侧、两侧、三侧或全部的四侧上(在中心区域是矩形的情况下)围绕中心区域。
接下来，在步骤62，将具有在其中形成的集成电路(IC)和在其表面上形成的多个结合焊盘的半导体管芯附着到相应的引线框架的管芯焊盘。此类半导体管芯和集成电路是本领域的技术人员众所周知的，对于完整理解本发明而言，不需要对管芯或IC的进一步说明。此外，还可以将多于一个的半导体管芯或电组件(例如电容器)附着到引线框架。
可以使用例如环氧树脂的已知管芯附着粘合剂将管芯附 着到管芯焊盘。随后通过已知的导线结合技术和导线结合机器来将引线框架的引线电连接到管芯结合焊盘。通常，将管芯结合焊盘电连接到引线的近端。在进行电连接之后，执行模塑或密封步骤，其中用模塑化合物来覆盖管芯、将管芯结合焊盘与引线互连的导线、以及引线的顶面。密封和模塑化合物在本领域中众所周知，对于本发明的完整理解而言，不需要进一步的说明。
在步骤64，在模塑化合物已固化之后，执行第一锯切拆分。拆分是将阵列中的引线框架相互分离、从而提供单独的封装器件的工艺。引线框架阵列和引线条通常在相邻的引线框架之间具有用以切割引线框架阵列的锯道。依照本发明的实施例，使用具有第一尺寸或宽度的第一锯片来执行第一锯切拆分。第一锯片沿着锯道将引线框架切割至预定深度，该预定深度在本发明的当前优选实施例中约为引线厚度的二分之一。同样使用具有第一刀片宽度的锯片。在本发明的一个实施例中，第一预定刀片宽度是0.58mm。第一拆分使得引线的一部分暴露，即在锯片切割引线的地方暴露。
为了在成品器件被附着到印刷电路板(PCB)或某些其它衬底或器件时提供更加界限分明(well defined)的焊料连接，在步骤66，用诸如锡或钯的可焊接金属来对引线框架的这些新暴露部分进行镀敷。用于对引线框架进行镀敷的此类可焊接金属众所周知且可容易地在市场上获得。镀敷工艺也是众所周知的。
在镀敷工艺完成时，在步骤68执行第二锯切拆分步骤。在第二锯切拆分步骤中，使用具有第二预定刀片宽度的第二锯片来沿着锯道并在由第一拆分步骤形成的空间内进行切割。第二拆分切穿引线和密封材料并将引线框架相互分离，从而形成单独的半导体封装。在本发明的一个实施例中，第二预定刀片宽度小于第一预定刀片宽度，并且在一个实施例中，第二刀片宽度约为0.50mm。由于执行了两个拆分步骤，在切割之间执行镀敷工艺，并且第一锯片宽于第二锯片，所以在第二拆分之后锯道处的引线的侧壁的约一半保持镀敷有可焊接金属。因此，如在作为根据本发明的实施例制造的封装器件之间的焊 点的放大照片的图6中可看到的那样，如上所述，可以形成具有更容易看见的延伸部分的焊点并因此更容易实现成品的视觉检查。
图7A～7F示出显示依照本发明的实施例的方法的各步骤的引线框架阵列的一部分的简化横截面图。从图7A开始，示出了引线框架70，所述引线框架70已附着有管芯72、被电连接、并用密封材料74密封。引线框架70可以包括由诸如铜的导电金属形成的框架或诸如镀锡铜的预先镀敷金属框架。在本实施例中，引线框架70包括附着有管芯72的薄层或管芯焊盘。还示出了在管芯72的相对侧的锯道76。
图7B示出正在执行的第一拆分操作，其中图的左侧的锯道76已被切割，而图的右侧的锯道76正在用第一锯片78进行切割。锯片76具有第一预定宽度并用来将引线框架70切割至约为引线框架厚度的一半的深度。在本发明的一个实施例中，使用具有约0.58mm的刀片宽度的Z1尺寸锯片。图7C示出第一拆分操作之后的两个锯道76。
图7D示出在进行镀敷操作之后的引线框架70，在镀敷操作中已用诸如锡的可焊接金属涂层(metal finish)80对引线框架进行镀敷。金属涂层80还可以保护引线框架的暴露部分免受侵蚀和氧化。在一个实施例中，用多孔可焊接金属涂层对引线框架70进行涂饰，从而减少或防止毛刺。金属涂层80具有足以涂敷引线框架70的外表面或暴露表面的厚度。在一个实施例中，金属涂层80具有至少约为5微米、或者可选地至少约为9微米的厚度。可选地，金属涂层80可以具有在约5～25微米范围内、或者更优选地在5～15微米范围内的厚度。在一个实施例中，金属涂层80是多孔锡涂层。可选地，金属涂层80可以是诸如锡-银、锡-铋、锡-铜、以及锡-锌的锡合金。可选地，可以将其它金属或金属组合用于金属涂层80，例如锡、铝、银、镉、锌、其组合、或这些金属的合金。在一个实施例中，通过镀敷来形成金属涂层80。例如，可将引线框架70浸渍到镀敷槽(plating bath)中并通过镀敷槽来对金属引线和管芯焊盘进行镀敷。请注意，在可选 实施例中，可以使用诸如无电镀敷或喷镀的其它镀敷方法来形成金属涂层80，其中，例如，可以改变这些方法的参数以控制金属涂层80的孔隙率。
图7E示出正在使用第二锯片82执行的第二拆分操作。第二锯片82具有第二预定宽度并用来在锯道76处切穿引线框架70的其余部分。所述第二预定宽度应小于(第一锯片78的)第一预定宽度，使得第二锯片82不刮擦锯道76的内侧上的金属涂层80。在本发明的一个实施例中，使用具有约0.50mm的刀片宽度的Z2尺寸锯片。
图7F示出已被从引线框架阵列切割下来的封装器件84。如图所示，金属涂层80在锯道的内侧的至少一部分上保持完整无损。如本领域的技术人员所理解的那样，可以执行附加修整，但必须小心操作，以便不去除封装84的侧部的金属涂层。
现在参照图8A～8D，示出了依照本发明的实施例的进行拆分操作的PQFN(功率方形扁平无引线)封装器件的放大照片。图8A示出管芯已被附着于薄层区域并与引线电连接的引线框架阵列的一部分的底面(参照图7A)。该图的额外放大部分示出通过模塑化合物与连接杆分离的四个引线。图8B示出在如上文参照图7B和7C所讨论的那样使用第一锯片执行第一拆分操作之后的相同的四个引线。在第一拆分操作中，执行半切割。图8C示出在如上文参照图7D所讨论的那样用涂层金属进行镀敷之后的器件的底面。最后，图8D示出在如上文参照图7E和7F所讨论的那样在用第二锯片进行第二拆分操作之后的引线框架阵列。
虽然已描述并示出了本发明的实施例，但相关领域的技术人员应理解的是可以进行设计或构造的细节方面的许多变更和修改，该变更和修改仍在本发明的范围内。而且，由于用于实现本发明的工具大部分是众所周知的，诸如电路、封装结构和用来制造根据本发明的器件的组合物，所以不以比认为描述本发明所需的程度更多地解释细节，以便理解并认识本发明的根本构思且不混淆或偏离本发明的教导。
在前面的说明书中，已参照特定实施例描述了本发明。然而，本领域的技术人员将认识到在不脱离以下权利要求所阐述的本发明的范围的情况下可以做出各种变更和修改。因此，应将说明书和附图视为说明性而非限制性的，并且所有此类修改意图被包括在本发明的范围内。此外，说明书和权利要求中的诸如“前”、“后”、“顶”、“底”、“上”、“下”等相关术语(如果有的话)用于说明的目的且不一定用于描述永久性相对位置。应理解的是，这样使用的术语在适当的情况下可互换，使得本文所述的本发明的实施例例如能够在不同于本文所示或所述的其它取向进行操作。本文所使用的术语“包括”、“包含”或其任何其它变体意图涵盖非排他性包含，使得包括一系列要素的过程、方法、物件、或装置不仅包括那些要素，而且可以包括未明确列出或为此类过程、方法、物件、或装置所固有的其它要素。本文所使用的术语“一个”或“一种”被定义为一个或多于一个。本文所使用的术语“多个”被定义为两个或多于两个。本文所使用的术语“另一个”被定义为至少有第二个或更多个。
上文已相对于特定实施例描述了益处、其它优点、以及问题的解决方案。然而，不应将所述益处、优点、问题的解决方案、以及可促使任何益处、优点、或解决方案发生或变得更加明显的任何要素解释为任何或全部权利要求的关键、必要、或本质特征或要素。

Claims (10)

1.一种用于封装多个半导体器件的方法，该方法包括：
提供包括多个单独的引线框架的引线框架条，每个引线框架具有多个引线，每个引线具有第一端部和第二端部，其中，所述引线从大致为矩形的中心空间向外延伸，第一端部接近于中心空间且第二端部远离中心空间，并且其中，在所述中心空间中设置有一个或多个管芯焊盘，并且其中，锯道位于所述多个引线框架的相邻引线框架之间；
在所述单独的引线框架的一个或多个管芯焊盘中的相应的第一管芯焊盘上附着半导体管芯，每个管芯在其中具有集成电路；
将所述单独的引线框架的引线电连接到管芯的相应的集成电路；
用模塑化合物来密封所述单独的引线框架的半导体管芯、电连接和引线，其中，至少引线的第二端部的底面被暴露；
沿着所述锯道用具有第一刀片宽度的第一锯片执行第一拆分，其中，所述第一拆分将所述引线框架的引线切割至第一深度；
用可焊接金属对所述引线框架的暴露部分进行镀敷；以及
沿着所述锯道并在由第一拆分形成的空间内用具有第二刀片宽度的第二锯片执行第二拆分，其中，所述第二拆分使引线框架相互分离，从而形成单独的半导体封装。
2.权利要求1的封装多个半导体器件的方法，其中，所述引线框架条包括铜。
3.权利要求2的封装多个半导体器件的方法，其中，所述可焊接金属包括锡、锌、钯和金之一。
4.权利要求1的封装多个半导体器件的方法，其中，引线框架条在所述锯道处具有一定的厚度且所述第一深度约为所述厚度的一半。 
5.权利要求1的封装多个半导体器件的方法，其中，所述第一刀片宽度大于所述第二刀片宽度。
6.权利要求5的封装多个半导体器件的方法，其中，所述第一刀片宽度约为0.58mm。
7.权利要求6的封装多个半导体器件的方法，其中，所述第二刀片宽度约为0.50mm。
8.权利要求7的封装多个半导体器件的方法，其中，通过执行第一和第二拆分，锯道处的引线的侧壁的约一半在第二拆分之后保持镀敷有可焊接金属。
9.一种用于封装多个半导体器件的方法，该方法包括：
提供包括多个单独的引线框架的引线框架条，每个引线框架具有多个引线，每个引线具有第一端部和第二端部，其中，所述引线从大致为矩形的中心空间向外延伸，第一端部接近于中心空间且第二端部远离中心空间，并且其中，在所述中心空间中设置有一个或多个管芯焊盘，并且其中，锯道位于所述多个引线框架的相邻引线框架之间；
在所述单独的引线框架的一个或多个管芯焊盘中的相应的第一管芯焊盘上附着半导体管芯，每个管芯在其中具有集成电路；
将所述单独的引线框架的引线电连接到管芯的相应的集成电路；
用模塑化合物来密封所述单独的引线框架的半导体管芯、电连接和引线，其中，至少引线的第二端部的底面被暴露；
沿着所述锯道用具有第一刀片宽度的第一锯片执行第一拆分，其中，所述第一拆分将所述引线框架的引线切割至第一深度；
用可焊接金属对所述引线框架的暴露部分进行镀敷；以及
沿着所述锯道并在由第一拆分形成的空间内用具有第二刀片宽 度的第二锯片执行第二拆分，其中，所述第一刀片宽度大于所述第二刀片宽度，并且其中，所述第二拆分使引线框架相互分离，从而形成单独的半导体封装。
10.一种用于封装多个半导体器件的方法，该方法包括：
提供包括多个单独的引线框架的引线框架条，每个引线框架具有多个引线，每个引线具有第一端部和第二端部，其中，所述引线从大致为矩形的中心空间向外延伸，第一端部接近于中心空间且第二端部远离中心空间，并且其中，在所述中心空间中设置有一个或多个管芯焊盘，并且其中，锯道位于所述多个引线框架的相邻引线框架之间；
在所述单独的引线框架的一个或多个管芯焊盘中的相应的第一管芯焊盘上附着半导体管芯，每个管芯在其中具有集成电路；
将所述单独的引线框架的引线电连接到管芯的相应的集成电路；
用模塑化合物来密封所述单独的引线框架的半导体管芯、电连接和引线，其中，至少引线的第二端部的底面被暴露；
沿着锯道用具有第一刀片宽度的第一锯片执行第一拆分，其中，所述第一拆分将引线框架的引线切割至第一深度，其中，引线框架条在所述锯道处具有一定的厚度且所述第一深度约为所述厚度的一半；
用可焊接金属对所述引线框架的暴露部分进行镀敷；以及
沿着所述锯道并在由第一拆分形成的空间内用具有小于第一刀片宽度的第二刀片宽度的第二锯片来执行第二拆分，并且其中，所述第二拆分使引线框架相互分离，从而形成单独的半导体封装，并且其中，通过执行第一和第二拆分，所述锯道处的引线的侧壁的约一半在第二拆分之后保持镀敷有可焊接金属。 
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US9000589B2 (en) 2012-05-30 2015-04-07 Freescale Semiconductor, Inc. Semiconductor device with redistributed contacts
US20160148877A1 (en) * 2014-11-20 2016-05-26 Microchip Technology Incorporated Qfn package with improved contact pins
US10504736B2 (en) * 2015-09-30 2019-12-10 Texas Instruments Incorporated Plating interconnect for silicon chip
WO2020166512A1 (ja) * 2019-02-15 2020-08-20 Ａｓｅジャパン株式会社 半導体装置、および、半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP3764587B2 (ja) * 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
US6826986B2 (en) * 2001-05-05 2004-12-07 Ah Beng Lim Bi-directional singulation system and method
TW498443B (en) * 2001-06-21 2002-08-11 Advanced Semiconductor Eng Singulation method for manufacturing multiple lead-free semiconductor packages
US6872599B1 (en) * 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
JP2005191240A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
US7281535B2 (en) * 2004-02-23 2007-10-16 Towa Intercon Technology, Inc. Saw singulation
US7608916B2 (en) * 2006-02-02 2009-10-27 Texas Instruments Incorporated Aluminum leadframes for semiconductor QFN/SON devices
US7993979B2 (en) * 2007-12-26 2011-08-09 Stats Chippac Ltd. Leadless package system having external contacts
US8084299B2 (en) * 2008-02-01 2011-12-27 Infineon Technologies Ag Semiconductor device package and method of making a semiconductor device package

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