TW201212132A - A method of semiconductor package with die exposure - Google Patents

Abstract

The present invention refers to a semiconductor device, and particularly refers to a method of semiconductor package with die exposure. The present invention provides a no-lead semiconductor device package based on the requirement for reducing the body size. A back metal layer of the die constitute a drain electrode directly exposed outside the plastic body, and the back metal layer is also used for pad welding and assembly to the PCB with surface-mount technology. And the drain electrode forms the thermal conductance of the die. The conductive path between the die and the back metal layer, gate pad or source pad of the semiconductor package is very short. The semiconductor package has low inductance and low package resistance, which provides superior electrical performance and heat dissipation.

Description

201212132 VI. Description of the Invention: [Technical Field of the Invention] [_] The present invention generally relates to a semiconductor device, and more particularly to a wafer-exposed leadless semiconductor device and a method of producing the same. [Prior Art] [〇〇〇2] Electronic products mainly use surface mount technology (SMT) to assemble electronic components, and heat dissipation and device size in semiconductor power devices assembled on printed circuit boards (PCBs) are extremely important. Performance parameters, usually we expect to get a semiconductor power device with high heat dissipation and small size, thinner thickness. In addition, inside the plastic package of the conventional semiconductor device, it is used to electrically connect the internal wafer and the semiconductor device. The bonding wire of the external contact terminal such as a pin is a discrete inductor that is easy to bring a negative effect. How to avoid the defect to improve the electrical performance of the power device is one of the problems to be solved. US Patent No. 7,154,168 discloses a flip-chip semiconductor device and a method of fabricating the same, the semiconductor device having one or more windows reserved on the molded body and exposed outside the window On the back side of the wafer, the semiconductor device further includes a plurality of pins arranged on both sides of the plastic device of the semiconductor device. In the meantime, U.S. Patent No. 7,256,479 discloses a method of manufacturing a wafer: fcf. by means of a flip chip by means of a flip chip package, the conductive layer of one side of the wafer of the semiconductor device being exposed to the plastic package Outside the body, the semiconductor 099130196 device also includes a plurality of pins arranged on both sides of the molded body of the semiconductor device. However, the technical solution of the above-mentioned published patent is not satisfactory in solving the problem of the overall heat dissipation of the semiconductor device, especially the heat dissipation path of the chip in the package 0993353637-0 Form No. A0101 Page 4 / Total 40 Page 201212132 There is still room for improvement, and it is difficult to substantially reduce the size of the semiconductor device by extending the pins of the molded body, and the manufacturing process for producing the device is complicated, and the cost in practical application is too high. SUMMARY OF THE INVENTION [0003] In view of the above, in order to solve the above limitations and problems, the present invention proposes a leadless semiconductor device based on reducing the size requirements of a package, directly exposing the back metal layer constituting the drain electrode of the wafer. On the outside of the molded body for molding the wafer, the back metal layer is directly used as a pad for assembling soldering to a heat dissipation pad of a printed circuit board (PCB), and also serves as a heat conduction path of the wafer. In order to obtain the above-mentioned leadless semiconductor device, the present invention provides a method for producing a wafer-exposed semiconductor device, comprising the steps of: performing electrical bonding on a front surface of a wafer including a plurality of wafers to form an electric forging region on the wafer, Grinding on the back side of the wafer for thinning the thickness of the wafer; depositing a metal layer on the back side of the thinned wafer; > coating a surface of the plating area with a conductive material; Pasting a dicing film on the surface; cutting the wafer and the metal layer for separating the wafer from the wafer and forming a back metal layer on the back side of the wafer; providing a lead frame with which the wafer is pasted and a base island of the front surface of the corresponding lead frame; bonding a layer of tape to the front surface of the lead frame; injecting the molding compound from the back side of the lead frame; removing the tape; cutting the lead frame and the molding compound to form a plurality of plastic sealing bodies Covering Station 099130196 Form No. A0101 Page 5 of 40 0993353637-0 201212132 The semiconductor device of the wafer. In the above method, any one of the wafers is provided with a first gate metal layer constituting the gate electrode of the wafer and a first source metal layer constituting the source electrode of the wafer on the front surface of the wafer, and the plating region is plated on the first gate. a layer of a second ruthenium metal layer on the surface of the polar metal layer and a second source metal layer electrically coupled to the surface of the first source metal layer. In the above method, the back metal layer of the wafer constitutes the drain electrode of the wafer. The method of the above-mentioned island includes a first metal contact piece and a plurality of second metal contact pieces on the same plane. In the above method, the bonding of the wafer to the base island region of the lead frame is realized by a flip chip production process. In the above method, the second gate metal layer is bonded to the first metal contact piece by a conductive material applied to the surface of the second gate metal layer; and the conductive material applied to the surface of the second source metal layer The second source metal layer is bonded to the plurality of second metal contact pads. In the above method, the first metal contact pads are connected to a gate pad through a gate pad extension structure; and the plurality of second metal contact pads are connected to a source pad via a source pad extension structure. In the above method, after the wafer is pasted, a bottom surface of the gate pad, a bottom surface of the source pad, a bottom surface of the back metal layer, and a front surface of the lead frame are located on the same plane. In the above method, a layer of tape bonded to the front surface of the lead frame contacts and covers a bottom surface of the gate pad, a bottom surface of the source pad, a bottom surface of the back metal layer, and a front surface of the lead frame. 099130196 Form No. A0101 Page 6 / Total 40 Page 0993353637-0 201212132 The above method 'Removal of the tape from the bottom of the genus layer, the bottom of the gate Tan plate: the middle and the outer exposed gold I*, +, female, i 7. Connect the bottom surface of the 4 discs. In the above method, the lead frame is connected to the island area by a plurality of connections. The above method is used to connect the thumb pad extension structure to the lead frame. , ,,. Structure and source pad The above method, the molding compound is also used for the disk extension structure, the first metal contact piece to cover the gate pad, the gate soldering electrode, the impurity pad delay, the above method, and the cutting lead frame :: Material body - the sidewall is exposed outside the grid _ ~ surface. The side of the surface of the surface of the surface of the surface of the surface of the surface of the wafer is a titanium alloy. Based on the above method, one of the present invention includes: an exposed semiconductor device, Ο: the wafer is on the front side of the wafer Providing a first source metal layer, a layer and a layer on the back side of the wafer, and a metal layer on the back side of the wafer; an electro-mineral on the surface of the first-gate metal layer, and a gate metal layer and electricity Mine = a layer of second source metal layer on the surface of the source metal layer; the gate welding dissimilar structure is provided with an extended extension structure,

Li=2 connects the first gate metal layer and the first metal contact piece by coating a conductive material on the second gate metal layer. One source pad and one extended source pad connected to the source pad The extension structure is provided to extend to the extension, . 099130196 Form number face 7 (four) 4. The number of the first source metal layers of the page 201212132 second metal contact pieces, the second source metal layer is coated with a conductive material on the second source metal layer, and the second source metal layer is bonded to the second metal contact piece for plastic packaging a molding body of the wafer, the first gate metal layer, the first source metal layer, the second gate metal layer, the second source metal layer, and the back metal layer, wherein a bottom surface of the back metal layer is exposed on a bottom surface of the molding body . In the above-mentioned wafer-exposed semiconductor device, the first gate metal layer constitutes the gate electrode of the wafer, and the first source metal layer constitutes the source electrode of the wafer. The back metal layer constitutes the drain of the wafer. electrode. The above-mentioned wafer exposed semiconductor device, the plastic package is also used for plastic-clad coated gate pad, gate pad extension structure, first metal contact piece, source pad, source pad extension structure, second metal contact a semiconductor device in which the wafer is exposed, a bottom surface of the gate pad, and a bottom surface of the source pad are exposed on a bottom surface of the molding body; and a side surface of the gate pad and a source pad One side is exposed on one side wall of the molding body. In the above-described wafer exposed semiconductor device, the gate pad extension structure is perpendicular to the gate pad, and the source pad extension structure is perpendicular to the source pad. In the above-described wafer exposed semiconductor device, the first metal contact piece and the plurality of second metal contact pieces are located on the same plane. In the above-mentioned wafer-exposed semiconductor device, the second gate metal layer, the second source metal layer, and the back metal layer are all titanium-recorded silver alloys. These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt; [Embodiment] Form No. A0101 099130196 Page 8 of 40 pages 0993353637-0 201212132 [0004] As disclosed in the scope of the patent application and the disclosure of the present invention, the technical solution of the present invention is specifically as follows: As shown in the figure, the semiconductor device 100 is a leadless package (N〇_lead Package) structure, and the sealing material of the semiconductor device 1 is a plastic package 丨3〇, and the molded body 130 includes a top surface 1, a bottom surface 102, and a The side wall 1〇3 exposes a side surface 121' of the gate pad 121 of the semiconductor device 1 and a side surface 122 of the source pad 122 on the sidewall 103. As shown in FIG. 2, the bottom surface 1〇2 of the semiconductor device 100 has a back metal layer 113 on which the plastic body 130 is exposed, a bottom surface 121' of the gate pad 121, and a bottom surface 122 of the source pad 122. One side of the back metal layer 1 exposed to the molding body 130 is the bottom surface 113 of the back metal layer 113. Referring to FIG. 3, the semiconductor device loo includes a wafer 11 which is molded in a molded body 130. The molded body 130 is "generally derived from a cured epoxy resin (Epoxy Molding Compound). See Fig. 4' The front surface 11 of the wafer 110 is provided with a first gate metal layer 11a and a first source metal layer ii〇c, and the back surface 110&quot; of the wafer 11〇 is provided with a “back layer metal layer-Π3, The back metal layer 113 includes a bottom surface 113'; and a second gate metal layer 11b plated on the surface of the first gate metal layer 11〇3 and a second layer on the surface of the first source metal layer The source metal layer 110d. The gate region and the source region (not shown) of the wafer 110 are located on the front surface 110' of the wafer 110, and the drain region (not shown) of the wafer 11 is located on the back surface 110 of the wafer 110. The first gate metal layer 110a is in electrical contact with the gate region (not shown) of the wafer 110 to constitute the gate electrode 'the first source metal layer 11' of the wafer 110 and the source region of the wafer 110 (not shown) Electrically contacting the source electrode of the wafer 110, the back metal layer 113 and the drain region of the wafer 110 (not Shown) Electrical contact constituting the drain of the wafer 110 099130196 Form No. A0101 Page 9 / Total 40 pages 0993353637-0 201212132 Pole. The gate electrode and the source electrode are usually copper or aluminum beryllium copper. The second gate metal A preferred material of the layer 110b, the second source metal layer 110d, and the back metal layer 113 is a titanium nickel silver alloy (Ti/Ni/Ag). Referring to FIG. 4, the second gate metal layer 1 of the wafer 110 L〇b is coated with a conductive material 111, and the second source metal layer 11〇d is coated with a conductive material 112. The preferred material of the conductive material m, 112 is conductive silver paste (Epoxy) or solder paste (s〇 The structure of the semiconductor device 1 shown in FIG. 3 in combination with the structure of the wafer 110 shown in FIG. 4 includes a gate pad 121 and a gate connected to the gate pad 1纟1. The pad extension structure 121a, the gate pad extension structure 121a is provided with a first metal contact piece 121b extending to the second gate metal layer U 〇b (not shown) of the wafer 110, through the second gate metal The conductive material ill coated on the layer smear adheres the second gate metal layer 110b to the first metal contact piece 121b The semiconductor device 10A shown in FIG. 3 further includes a source pad ι22 and a source pad extension structure 122a connected to the source pad 122. The source pad extension structure 122a is provided to extend close to the worm blade no. a plurality of second metal contact pads 122t) of the second source metal layer 110d (not shown), the second source metal layer is deposited by the conductive material 112 coated on the second source metal layer 110d 110d is bonded to a plurality of second metal contact pieces i22b. That is, in the third figure, the first metal contact piece 121b is bonded to the second gate metal layer 11b by the conductive material Hi in FIG. 4, and the plurality of second metal contact pieces 122b in the third figure are passed through the fourth A plurality of conductive materials u 2 in the figure are bonded to the second source metal layer 110d. Referring to FIG. 5, in the semiconductor device 1 of FIG. 3, the first metal contact piece 121b is connected to the gate pad 121 through a gate pad extension structure 21a; a plurality of second metals Contact pad 22b extends through a source pad 0993353637-0 099130196 Form No. A0101 Page 10 / Total 40 page 201212132 Structure 122a is connected to source pad 122. The vestibule extension structure i2ia is perpendicular to the gate pad 121, and the source pad extension structure 122a is perpendicular to the source pad 122. The metal-contact piece 121b and the plurality of second metal contact pieces 12 2 b are located on the same plane.

Referring to FIG. 6, in the semiconductor device 1A of FIG. 3, the wafer 110 is pasted to the first metal contact by a flip chip in the form of a flip chip by the conductive materials 111, 112 in FIG. The plurality of second metal contact pads 122b of the chip i21b are disposed such that a bottom surface 113' of the back metal layer 113 is located at the same bottom surface 12 of the gate pad 121 and a bottom surface 12 2 of the source pad 12 2 flat. ϋ In the third and fourth figures, the molded body 13'.0 is used for the plastic package: the covering wafer 11 〇, the first gate metal layer 110a, the first source metal layer 110 (;, the second gate metal layer) 110b, the second source metal layer 11dd and the back metal layer 113, the molding body 130 is also used for molding the cladding gate pad 121, the outline pad extension structure 121a, the first metal contact piece 121b, and the source soldering The disk 122, the source pad extension structure 122a, the second metal contact piece 122b, and the conductive materials in, 112. In Fig. 2, the bottom surface of the gate pad 121 exposed to the bottom surface 1〇2 of the body 130 is 1_21&quot; An external gate contact terminal for forming a crystal plate. The bottom surface 122' of the source pad 122 exposed on the bottom surface 102 of the molding body 130 is used to form an external source contact terminal of the wafer 11A. The bottom surface 113 of the back metal layer 113 exposed on the bottom surface of the plastic stamping 130 is used to form an external drain contact terminal of the wafer 110. Typically, the external gate contact terminal, the external source contact terminal, and the external drain contact terminal are used as electricity. The signal transmission terminal is used to connect the semiconductor device 100 to the external component device, respectively Gate, Source, and Drain of the conductor device 100 ° 099130196 Form No. A0101 Page 11 / Total 40 Page 0993353637-0 201212132 In Figure 4, the front side of the wafer no. a first gate metal layer 110a and a first source metal layer 11〇 (usually an alloy of metal aluminum such as copper or aluminum beryllium copper, first gate metal layer 11〇a and first source The metal layer 110c is insulated and insulated by a passivation layer. In the conventional 1 (: packaging field, the first gate metal layer 11 〇a of the aluminum material and the first source metal layer 11 〇c are used.

The bonding area is electrically connected to the 1C pin by wire bonding. However, the aluminum material is extremely susceptible to oxidation, which is different from the conventional technology. The present invention strongly avoids the first gate metal layer 11 which is easily oxidized. a. The first source metal layer 1106 is directly bonded to the first metal contact piece i21b and the second metal contact piece 12 2 b to electroplate a titanium-nickel silver alloy (Ti/Ni/Ag) which is chemically stable. The second gate metal layer 110b and the second source metal layer 110d are formed by the surface mount technology (SMT) in the first gate metal layer ii 〇 a, the first source metal layer l · 〇 2 The semiconductor device 1 is assembled onto a printed circuit board (PCB), and the exposed back metal layer 113 is soldered to a PC: B: heat-dissipating solder: on the disk: the semiconductor device 100 is soldered by a solder paste or the like. It has excellent electrical and thermal performance after being placed on the PCB. The semiconductor device 100 is not arranged with a bonding wire inside the molding body like a conventional semiconductor package (such as a TS〇p package), the wafer 100 and the back metal layer 113, the gate pad 121, and the source. The conductive path between the pads 122 is short, the self-inductance coefficient and the wiring resistance in the package are low, so that it can provide excellent electrical performance. In addition, it provides excellent heat dissipation performance through the exposed back metal layer 113, the gate pad 121, and the source pad 122. The heat dissipation pad of the PCB for soldering the back metal layer 113 has a direct heat dissipation channel. The heat inside the package of the semiconductor device is released. Usually 'back metal layer 113, gate pad 121, source 099130196 form number A0101 page 12 / total 40 page 0993353637-0 201212132 pole plate 122 directly soldered on the PCB board 'thermal cooling vias in the PCB help To dissipate excess power into the copper ground plane' to absorb excess heat. The No-lead Package design is suitable for applications where size, weight and performance are required due to its small size and light weight. Another aspect of the present invention provides a method of producing a wafer-exposed semiconductor device based on the above technical features, comprising the steps of:

Electroplating on a front side of a wafer containing a plurality of wafers to form a plating area on the wafer; grinding on the back side of the wafer for thinning the thickness of the wafer; depositing a layer on the back side of the thinned wafer a metal layer; coating a surface of the electro-bonding region with a conductive material; coating a surface of the metal layer with a dicing film; cutting the crystal layer and the metal layer for separating the wafer from the money and forming the wafer The back metal layer on the back;

Providing a lead frame with which the (6) wafer is pasted to the base island area of the front surface of the corresponding lead frame; the adhesive tape is bonded to the positive: surface of the frame; the plastic seal is injected from the back side of the lead frame Removing the tape; the plastic body encapsulates the cut lead frame and the molding compound to form a plurality of semiconductor devices described. 099130196 Specifically, the specific steps are as follows. Referring to FIG. 7, the wafer (Wafer) 2 white a U includes a plurality of wafers (Die) 210' cast together to perform electroplating on the front side 1 of the wafer 200 to form a plating on the wafer 210. Area Form No. A0101 Page 13 of 40 Figure 8 shows the front structure of the wafer 0993353637-0 201212132 21 0. Any one of the wafers 21 is provided with a layer of the gate electrode of the wafer 210 on the front side of the wafer 2〇〇. a first gate metal layer (not shown) and a first source metal layer (not shown) constituting a source electrode of the wafer 210. Therefore, after plating on the front surface 201 of the wafer 200, the plating region includes plating A second gate metal layer 21 on the surface of the first gate metal layer and a second source metal layer 212 plated on the surface of the first source metal layer. It is not shown in FIG. 8 that the first gate metal layer is covered by the second gate metal layer 211, and the first source metal layer is not shown covered by the second source metal layer 212. See FIG. Schematic diagram of the cross-sectional structure of the wafer 2, the wafer 2 includes a front surface 201 and a back surface 202, and is polished on the back surface 2: 02 (Wafer Backside Grinding) for thinning the thickness of the crystal surface 200, and the thinned wafer 200 See the picture in Figure 1. 'Refer to Figure 11, on the back side 2〇2 of the thinned wafer 2〇〇, deposit a layer of titanium-nickel alloy or silver-nickel alloy with high electrical properties and chemical stability 213 〇 See Figure 12 As shown, in combination with the wafer 210 shown in the eighth window, the electric forging on the wafer 210 on the front side 201 of the wafer 200: the surface is coated with a layer of conductive silver paste (Epoxy) or solder paste (Solder paste). The conductive material forms a conductive material 21 涂覆 coated on the surface of the second gate metal layer 211 of any one of the wafers 210; and a plurality of conductive materials 212 coated on the surface of the second source metal layer 212 of the wafer 210. The present invention selectively coats a plurality of regions of conductive material 212' at predetermined regions of the surface of the second source metal layer 212. Referring to Fig. 13, a dicing film 214 is attached to the surface of the metal layer 213, and the dicing film 214 is usually a blue film. See Fig. 099130196 Form No. A0101 Page 14/Total 40 Page 0993353637-0 201212132 Show 'Wafer Saw, cut wafer 200 and cut film 214 from front side 2〇1, Tushen cut 21 5 For a predetermined cutting line, the metal layer 213 is simultaneously cut, and the cutting film 214 is partially cut in the longitudinal direction for dividing the wafer 200 into a plurality of wafers having the back metal layer 2 j 3 in FIG. 210, the back metal layer 213, derived from the cutting of the metal layer 213. So far, the plurality of wafers 210 are separated from the wafer 200, and the back metal layer 213 constitutes the drain electrode of the wafer 210. Referring to Fig. 15, the front surface 201' of the wafer 210 having the cooking surface metal layer 213 is the same as the front surface 202' of the wafer 210 on the front side of the wafer 200 in Fig. 14, that is, the same as in Fig. 14. The back surface 202' of the wafer 200 is bonded to the wafer 210 shown in Figs. 15 and 8, and in Fig. 15, the second gate metal layer 211 coated on the wafer 21 is formed on the front surface 20|&gt; Figure 15 is not shown, the conductive material 21 表面 on the surface of the 'well reference §' and the second source metal layer 212 coated on the wafer 21 ( (not shown in Figure 15) Multiple conductive material 212' regions. Referring to Fig. 16, a front side 301 of a lead frame 300 and a back side surface 30.2, not shown, are shown. The present invention comprises a plurality of wafer assembly areas 31 0 . A schematic structure in which the wafer assembly area 31 is connected to the lead frame 300 is shown in Fig. 17. The specific structure of the wafer assembly area 31 is shown in Fig. 18. The wafer assembly area 310 includes a base island for pasting the wafer (Paddle The island area is composed of a plurality of second metal contact pieces 3i2b and a first metal contact piece 311b, and the plurality of second metal contact pieces 312b are located on the same plane as a first metal contact piece 31 lb. In the wafer assembly area 310, the first metal contact piece 311b is connected to a gate pad 311 through a gate pad extension structure 311a, and the plurality of second metal contact pieces 312b are connected to the source pad extension structure 312a through a source pad extension structure 312a. A source pad 099130196 Form No. A0101 Page 15 / Total 40 page 0993353637-0 201212132 312 'In this structure, the gate pad extension structure 311a is perpendicular to the peach pad 311, the source pad extension structure 312a is perpendicular to source pad 312. As shown in FIG. 17 and FIG. 18, the source pad extension structure 312a is connected to a connecting rib 312c. The plurality of second metal contact pads 312b and the source pad 312 are connected to the lead frame 3 through the connecting rib 312c. The gate pad extension structure 31a is connected to a connecting rib 311c. The first metal contact piece 3Ub and the gate pad 311 are connected to the lead frame 300 through the connecting rib 311c. The invention discloses a relatively simple base island region and lead frame connection manner. In fact, the first metal contact piece 311b, the gate pad 311 and the gate pad extension structure 3 ua and the plurality of second metal contact pieces 312b, the source pad 31 2 and the source pad extension structure 312a are connected to the lead frame 300. Other connection arrangements may be selected, for example, by connecting to the gate pad 311 and the source pad 312. The ribs connect the gate pad 311 and the source pad 312 to the lead frame 3A. A bottom surface 311 of the gate pad 311, a bottom surface 312 of the source pad 312, and a positive electrode of the lead frame 300 are located on the same plane. Referring to FIG. 19, a die attach process using a Fip Chip (Die Attach) * a conductive material 211, 212 coated on the front surface 201' of the wafer 210 shown in FIG. The wafer 210 is pasted to the base island region of the front surface 3〇1 of the lead frame 300 in FIG. 16 corresponding thereto, as shown in FIG. 15, since the wafer 210 is formed on the front surface 2〇1, the second gate metal is formed thereon. The conductive material 21Γ on the surface of the layer 211 (not shown) and the plurality of conductive materials 212' regions located on the surface of the second source metal layer 212 (not shown) are finished after the wafer is pasted, and then the second ultra-polar metal layer 211 is just right. The conductive material 211' is bonded to the first metal contact piece 311b of FIG. 18'. The first source metal layer 212 passes through a plurality of conductive materials 099130196. Form No. A0101 Page 16 / Total 40 Page 0993353637-0 201212132 Area 212 Bonding to the plurality of second metal contact pieces 312b in FIG. 18 to obtain a schematic view of the wafer bonding in the paddle as shown in FIG. 19, the wafer 210 pasted to the first metal of the island area Contact piece 31 lb, several second metals After the contact piece 312b, the back surface of the metal layer 213 'of the bottom surface 213' and the gate pad 311 of the bottom surface 311 ,, a source pad 312 of a bottom surface 312, located in the same plane.

Referring to Fig. 20, the lead frame 300 has been subjected to wafer bonding, i.e., the wafer assembly area 31 of the lead frame 3 in Fig. 16 to complete the pasting of the wafer 210. At this time, as shown in Fig. 21, Fig. 22, a layer of tape 4 is bonded to the front surface 3〇1 of the lead frame 3〇〇, and a layer of tape 400 bonded to the lead frame as shown in Fig. 23 is obtained. The front surface of the 300 has a cross-sectional structure of 3,1, and the other side opposite to the front surface 301 is a lead frame 3 (10) and a rear surface 3〇2. Referring to Fig. 24, in the cross-sectional structure of the wafer 210 in the lead frame 300 to which a layer of tape is bonded, the tape 4 is in contact with and covers a bottom surface 312 of the source pad 312, and the back metal The bottom surface of layer 213, 213&quot;

And the front surface 301 of the lead frame 300, a bottom surface 31 of the gate pad 311, a bottom surface 312' of the source pad 312, and the front surface 301 of the lead frame 3〇〇 are located on the same plane, in combination with FIG. Similarly, a bottom surface 311 of the gate pad 311 which is not shown in FIG. 24 is also contacted and covered by the tape 4 . Referring to Fig. 25, a molding compound is injected from the back surface 3〇2 of the lead frame 300 to perform molding (Molding). In the molding process, the lead frame 3〇〇 is placed in a cavity of a mold of a molding apparatus, and the mold includes a top mold and a bottom mold, and the tape 400 is closely attached to the lower mold. On the upper surface of the mold, the molding compound is plastic-molded on one side of the back surface 302 of the lead frame 300. The molding material 099130196 Form No. A0101/page 40/0993353637-0 201212132 is generally an Epoxy Molding Compound. After the molding process is completed, as shown in FIG. 26, the back surface 302 of the lead frame 3 and the lead frame 300 and the wafer 210, the second metal contact piece 312b, the first metal contact piece 311b, the gate pad extension structure 31la, The gap between the gate pad 311, the source pad extension structure 312a, the source pad 312, the continuous rib 312c, and the connecting rib 312c is filled with a molding compound 5 〇〇. In the molding process, the bottom surface 312' of the source pad 312 that is in contact with the tape 400 and covered, the bottom surface 311' of the gate pad 311, and the bottom surface 213' of the back metal layer 213 are protected by the tape 400 without being protected by the tape 400. The molding material touches 'to prevent the bottom surface 312' of the source pad 312, the bottom surface 311' of the gate pad 311, the bottom surface 213&quot; of the back metal layer 213', and the lower mold (Bottom)

There is a plastic compound intrusion (, f.n vas i〇n ) between the upper surfaces of Chase to produce Bleeding. If the bottom surface 312 of the source pad 312, the bottom surface 311' of the gate pad 311, and the bottom surface 213&quot; of the back metal layer 213 are adhered with unnecessary molding materials, in the SMT process, the bottom surface 312, 'bottom surface 311 , the bottom surface 213 ” is difficult to adhere to the solder paste and insult: it can not maintain the normal assembly of the PCB JL: and this is not what we expected 〇 &lt; See Figure 27 The front surface 301 of the lead frame 300 is removed from the tape 4A. Here, the cross-sectional structure of the wafer 210 in the lead frame 300 of the removal tape 4A is obtained as shown in Fig. 28, and the gap around the wafer 21 is already Filled with a molding compound 500, a wafer 210, a second metal contact piece 312b, a first metal contact piece 311b, a gate pad extension structure 311a, a gate pad 311, a source pad extension structure 312a, and a source pad 312 The continuous rib 312c, the continuous rib 312c and other components are sealed by the molding compound 5 但是 'But, since the tape 400 is removed', therefore, it is in contact with the tape 4〇〇 and 099130196 0993353637-0 Form No. A0101 Page 18 / Total 40 pages 201212132 Covered source pad 3 A bottom surface 312 of the 12, a bottom surface 31 of the gate pad 311, a bottom surface 213 of the back metal layer 213, and a front surface 301 of the lead frame 300 are exposed. After the molding is completed, the molded lead frame 300 is cut. (Package Saw), the cutting lead frame 300 and the molding compound 500 are simultaneously performed. Referring to Fig. 29, the cutting lines 312d, 31 Id are pre-designed cutting positions, and the connecting ribs 312c and the connecting ribs 312c are cut ( Package Saw)

The art is cut off, in fact, the cut ribs 312c and the connected ribs 312c. 丨: ...:

More or less portions are retained on the source iterative disk extension structure 312a, the gate pad extension structure 311a (not shown below for brevity and ease of description). The wafer 210 together with the second gold: contact piece 312b, first metal contact piece 311b, gate pad extension structure 311a, gate pad 311, source pad extension structure 312a, source pad 312, and others are attached Each component on the wafer 210 is cut and separated from the lead frame 300. 'The semiconductor mosquito set 600 J shown in FIG. 30 is obtained. See FIG. 30 and FIG. 31. FIG. 30 is a perspective view of the semiconductor 600. F 丨. Schematic structure '31 is a cross-sectional structure of the semiconductor device 600, and the molded body 500' is derived from the cutting of the molding compound 5 。. 8 to 31, the semiconductor device 600 includes a gate pad 311 and a gate pad extension structure 3Ua connected to the gate pad 311, and the gate pad extension structure 311a is provided to extend adjacent to the wafer 210. The first metal contact piece 311b' of the second thumb metal layer 211 is bonded to the first metal contact piece 311b by the conductive material 211' coated on the second gate metal layer 211 Source pad 312 and source pad extension 312a connected to source pad 312 'Source pad extension 312a is provided to extend near wafer 099130196 Form No. A0101 Page 19 / Total 40 Page 0993353637-0 a plurality of second metal contact pads 31 2b of the second source metal layer 21 2 of 201212132 21 0, the second source metal layer 212 is separated by a plurality of conductive materials 212 coated on the second source metal layer 212 A plurality of second metal contact pieces 312b are bonded. In FIG. 19, a bottom surface 312' of the source pad 312, a bottom surface 311' of the gate pad 311, and a bottom surface 2131' of the back metal layer 213 are exposed to the semiconductor device 6 in FIG. 30 and FIG. The bottom surface of the crucible is 6〇2. In Fig. 30 and Fig. 31, the top surface 602 of the semiconductor device 6 is opposed to the bottom surface 602, and the adjacent top surface 601 and the bottom surface 602 are a side wall 6〇3 of the conductor device 600. Referring to FIG. 30, in the above method, the molding compound 5〇〇 and the lead frame 300 are obtained to obtain the molded body 5·, while a side surface 312 of the source pad 3丨2 and the gate pad 311 are obtained. One side 311 &quot; semiconductor device 60 暴露 exposed to sidewall 603 of semiconductor device 6 〇, bottom surface 311 of exposed gate pad 3n, for forming external gate contact terminal of wafer 210, exposed source soldering The bottom surface 31 2' of the disk 31 2 is used to form an external source contact terminal of the wafer 21 , and the bottom surface 213 of the exposed back metal layer 213 ′ is used to shape the external drain contact terminal of the wafer 21 . Based on the coplanarity requirement of the semiconductor device, the bottom surface of the back metal layer 213' and the bottom surface 311 of the gate pad 311, and the bottom surface of the source pad 312 312, the bottom surface 213&quot;, the bottom surface 311, and the bottom surface 312 in the same plane, after the solder paste is soldered to the PCB circuit board, the conductive conductor device _ and the PCB maintain good electrical conductivity and heat dissipation performance. To have stable reliability. It will be apparent to those skilled in the art that various changes and modifications may be Based on the present invention, the semiconductor device disclosed in the present invention has many variations. For example, the present invention 0993353637-0 099130196 form number A0101 page 20 / total 40 page 201212132 is a single wafer as an example, according to the same The inventive concept is also applicable to a bi-wafer or multi-wafer device; or the invention is applied to a device comprising a pin. These variants are undoubtedly considered by the inventors to be an important part of the invention. A typical embodiment of a particular configuration of a particular embodiment is set forth by the description and drawings. Although the above invention presents a prior preferred embodiment, these are not intended to be limiting. It will be apparent to those skilled in the art that the present invention is susceptible to various other specific forms. The present invention can be applied to these embodiments without undue experimentation. Accordingly, the scope of the appended claims is intended to cover all such changes and modifications of the present invention. Any and all equivalent ranges and contents are intended to be within the scope and spirit of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0005] Embodiments of the present invention will be described more fully with reference to the accompanying drawings. The accompanying drawings, which are for the purpose of illustration, Fig. 1 is a schematic plan view showing a top surface structure of a semiconductor device. Fig. 2 is a schematic plan view showing the structure of the bottom surface of the semiconductor device. Figure 3 is a schematic perspective view of a semiconductor device. Fig. 4 is a view showing the structure of a second gate metal layer on the surface of the wafer and the first gate metal layer and a second source metal layer on the surface of the first source metal layer in the semiconductor device. Fig. 5 is a view showing the structure of a gate pad, a gate pad extension structure, a first metal contact pad and a source pad, a source pad extension structure, and a plurality of second metal contact pads in a semiconductor device. 099130196 Form No. A0101 Page 21 of 40 Stomach 0993353637-0 201212132 FIG. 6 is a schematic view showing the structure in which a wafer is bonded to a first metal contact piece and a source pad and a plurality of second metal contact pieces in a semiconductor device. Figure 7 is a top plan view of the front side of a wafer containing a plurality of wafers. Figure 8 is a top plan view of the front side of the wafer on the wafer. Figure 9 is a schematic cross-sectional view of the wafer. Figure 10 is a schematic illustration of back grinding of the wafer. Figure 11 is a schematic illustration of the deposition of a metal layer on the back side of the wafer. Figure 12 is a schematic illustration of the application of a layer of electrically conductive material to the surface of the electroplating zone. Figure 13 is a schematic view of attaching a dicing film to the surface of the metal layer on the back side of the wafer. Figure 14 is a schematic view of the wafer being cut. Fig. 15 is a schematic view showing the structure of the wafer obtained by cutting the wafer. Fig. 16 is a plan view showing the front structure of the lead frame used in the present invention. Fig. 17 is a view showing the structure of the connection of the lead frame around the base island region and the base island region. Figure 18 is a schematic view showing the structure of the base island and the connecting ribs connecting the lead frames. Figure 19 is a schematic view showing the structure of the wafer pasted to the island area. Fig. 20 is a plan view showing the front structure of the lead frame on which the wafer bonding is completed. Figure 21 is a flow chart showing the bonding of a layer of tape to the front side of the lead frame. 〇 Figure 22 is a top plan view showing the structure of bonding a layer of tape to the front side of the lead frame. Figure 23 is a schematic cross-sectional view of a lead frame bonded with a layer of tape 099130196 Form No. A0101 Page 22 of 40 0993353637-0 201212132 Figure 24 is a cross-sectional structure of the wafer in a lead frame bonded with a layer of tape. schematic diagram. Figure 25 is a schematic view of the injection of a molding compound from the back side of the lead frame. Fig. 26 is a schematic sectional view showing the structure of the lead frame in which the molding material is injected. 〇 Fig. 27 is a schematic sectional view showing the structure of the lead frame from which the tape is removed. Figure 28 is a schematic cross-sectional view of the wafer in the lead frame from which the tape is removed. ❹ [0006]

Figure 29 is a schematic view showing the cutting of the lead frame and the molding compound. Fig. 30 is a perspective structural view showing a semiconductor device obtained by cutting a lead frame and a molding compound. Fig. 31 is a schematic sectional view showing the structure of a semiconductor device obtained by cutting a lead frame and a molding compound. [Description of main component symbols] 100 '600 semiconductor device 101, 601 semiconductor device top surface 102, 602 semiconductor device bottom surface 103 &gt; 603 semiconductor device sidewall 110 semiconductor device wafer 110' semiconductor device wafer front surface 110" semiconductor device wafer rear surface 110a · a thumb metal layer 110b, 211 a second gate metal layer 110c a first source metal layer 110d' 212 a second source metal layer 099130196 111 '112, 211, 212' Form No. A0101 Page 23 of 40 Page conductive material 0993353637-0 201212132 113, 113, 121, 121' 121" 121a 121b 122, 122, 122" 122a 122b 130 '200 201 202 202, 202" 210 213 213" 214 215 300 301 302 back metal layer 213, Bottom metal layer 311 gate pad, 311' gate pad bottom surface, 311" gate pad side, 311a gate pad extension, 311b first metal contact 312 source pad, 312' source solder The bottom surface of the disk, the 312" source pad bottom surface source pad extension structure, 312b the second metal contact piece 500, the back side of the front side wafer of the molded wafer wafer The back side of the wafer is formed on the back side of the wafer. The back side of the wafer is made of nickel-nickel alloy or the metal layer of the silver-plated alloy. The back side of the metal layer is cut on the back side of the lead-lead lead frame. The front side of the lead frame is 099130196. Form No. A0101 Page 24 of 40 0993353637-0 201212132 310 Wafer assembly area 311c, 312c rib 312a Source pad extension 312d Cutting line 400 Tape 500 Pair of molding material 99 099130196 Form number Α 0101 Page 25 / Total 40 page 0993353637-0

Claims (1)

201212132 VII. Patent application scope. i.- A method for producing a semiconductor device exposed by a wafer, comprising the steps of: performing electric forging on the front surface of a wafer containing a plurality of wafers to form an electric clock region on the wafer, Grown on the back side of the wafer for thinning the thickness of the wafer; depositing a metal layer on the back side of the thinned wafer; coating a surface of the conductive layer with a conductive material; and pasting a surface of the metal layer with a dicing film; Cutting the wafer and the metal layer for separating the wafer from the wafer and forming a back metal on the back side of the wafer; providing a lead frame with which the wafer is pasted to a corresponding lead The base of the front side of the frame; bonding a layer of tape to the front side of the lead frame; injecting the molding compound from the back side of the lead frame; removing the tape; cutting the lead frame and the molding compound to form a plurality of plastic packaging bodies A semiconductor device of a wafer. 2. The method of claim 1, wherein the arbitrary wafer has a first gate metal layer constituting the gate electrode of the wafer and a first source constituting the source electrode of the wafer on the front surface of the wafer. The electrode metal layer comprises a second gate metal layer plated on the surface of the first gate metal layer and a second source metal layer plated on the surface of the first source metal layer. 3. The method of claim 1, wherein the back metal layer constitutes a drain electrode of the wafer. 4. The method of claim 2, wherein the base island region 099130196 form number A0101 page 26 / total 40 page 0993353637-0 201212132 includes a first metal contact piece and number in the same plane Second metal contact pads. 5. The method of claim 4, wherein the bonding of the wafer to the base island region of the lead frame is implemented by a flip chip production process. 10 . The method of claim 5, wherein the second gate metal layer is bonded to the first metal contact piece by a conductive material applied to the surface of the second gate metal layer, and by coating The conductive material on the surface of the two source metal layer bonds the second source metal layer to the plurality of second metal contact pads. The method of claim 5, wherein the first metal contact piece is connected to a gate pad through a gate pad extension structure; and the plurality of second metal contact pieces are extended through a source pad Connect to a source pad. The method of claim 7, wherein after the wafer is pasted, a bottom surface of the gate pad, a bottom surface of the source pad, a bottom surface of the back metal layer, and a front surface of the lead frame are located on the same plane. The method of claim 8, wherein the adhesive tape bonded to the front surface of the lead frame contacts and covers the bottom surface of the gate pad, the bottom surface of the source pad, the bottom surface of the back metal layer, and the lead frame. positive. The method of claim 9, wherein the bottom surface of the back metal layer, the bottom surface of the gate pad, and the bottom surface of the source pad are exposed from the molding compound after the tape is removed. The method of claim 7, wherein the lead frame is connected to the island area by a plurality of connecting ribs. The method of claim 11, wherein the rib is used for the gate 099130196, the form number A0101, the 27th page, the total 40 page, the 0993353637-0 12 11 . 201212132 the electrode pad extension structure u 13 as claimed in the patent scope The party described in 7 items:;, on its framework. The plastic encapsulated gate „, the gate pad 1 (four) material is also used for, the source pad, the source soldering silver · L structure, the metal-metal contact metal layer and the conductive material., structure, 'second metal contact piece The back side 14 is as described in claim 13 of the patent application, and the molding compound is also used to expose the side surface of the sealing electrode on the side wall of the sealing body. Source pad - side. On the disk 16 as claimed in the scope of patents! The method described in the 'the metal layer of the alloy is a nickel-silver alloy. The semiconductor device exposed on the wafer surface includes: - the wafer is provided with a - layer first gate on the front side of the wafer a metal layer and a layer of electric shovel on the - - "layered back metal layer; and the second source metal of the surface of the first ο (4) | the first gate metal layer and the electroplated two - source metal layer a gate pad and a nine-electrode μ-oil gate pad extension structure connected to the gate pad, the gate pad k-extension structure is provided to extend into the metal (four) y-gate metal The first and the splicing of the layer are bonded to the first metal contact piece through the second gate metal layer and the first metal contact piece; the source pad extension structure connected to the source side and the source pad, source _. Η u a plurality of first metal contact sheets of a source metal layer, the second source metal layer and the second metal contact sheet are adhered by coating a conductive material on the second source metal _ a Λ ^ genus layer Connected; used to mold the coated wafer, the first gate metal layer, 窜^ .. _ increase the first source metal layer The second gate metal layer, the second source metal 0 and the surface metal layer of the plastic body, wherein the bottom surface of the four U layers is exposed to the plastic seal 099130196 Form No. 1010101 Page 28/Total 4 Page 0993353637-0 201212132 17 . The wafer-exposed semiconductor device according to claim 16, wherein the first gate metal layer constitutes a gate electrode of the wafer, and the first source metal layer constitutes a source electrode of the wafer, and a back metal The layers constitute the drain electrode of the wafer. 18. The wafer-exposed semiconductor device of claim 16, wherein the molding body is further used for molding a gated pad, a gate pad extension, a first metal contact, and a source pad. a source pad extension structure, a second metal contact piece, and a conductive material. 19. The wafer-exposed semiconductor device according to claim 18, wherein a bottom surface of the gate pad and a bottom surface of the source pad are exposed on a bottom surface of the molding body; and a gate pad One side of the source pad and one side of the source pad are exposed on one side wall of the molding body. The wafer-exposed semiconductor device of claim 16, wherein the gate pad extension structure is perpendicular to the gate pad, and the source pad extension structure is perpendicular to the source pad. The semiconductor device of the wafer disclosed in claim 16, wherein the first metal contact piece and the plurality of second metal contact pieces are located in the same plane 22; as in claim 16 In the wafer-exposed semiconductor device, the second gate metal layer, the second source metal layer, and the back metal layer are all titanium-recorded silver alloys. 099130196 Form No. A0101 Page 29 of 40 0993353637-0