CN105470231A - 一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法 - Google Patents

一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法 Download PDF

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CN105470231A
CN105470231A CN201510990730.5A CN201510990730A CN105470231A CN 105470231 A CN105470231 A CN 105470231A CN 201510990730 A CN201510990730 A CN 201510990730A CN 105470231 A CN105470231 A CN 105470231A
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李万霞
郭玲芝
吕海兰
冯后清
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本发明公开了一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法，所述框架引脚在框架背面，其上有凹槽，所述凹槽处有锡膏，该方法采用化学蚀刻的方法替代第一次切割分离，避免了物理切割引脚受力的问题，降低引脚根部分层风险，也解决了切割后引起的毛刺，导致短路的问题，具有蚀刻精度高、定位准的优点。

Description

一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法
技术领域
本发明涉及微电子的QFN/DFN封装领域，具体是一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法。
背景技术
现有QFN/DFN封装的切割工序会进行两次切割，先用较宽的刀片切刀框架厚度的一半，再用窄的刀片完全切割分离，可将引脚切割为台阶式引脚，SMT时引脚侧面锡量饱满，容易爬锡。
存在的问题：
1、第一次的半切割方式会导致裂纹及连筋异常；
2、由于刀片只在框架表面划过，铜延展非常严重甚至连筋；
3、产品经过两次机械切割，容易造成产品引脚根部毛刺、分层异常；
4、切割加工误差较大，对位不准造成产品切割后尺寸、形状不符。
发明内容
针对上述现有技术存在的问题，本发明提供了一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法，该方法采用化学蚀刻的方法替代第一次切割分离，避免了物理切割引脚受力的问题，降低引脚根部分层风险，也解决了切割后引起的毛刺，导致短路的问题，具有蚀刻精度高、定位准的优点。
一种采用半蚀刻工艺形成阶梯式框架引脚，所述框架引脚在框架背面，其上有凹槽，所述凹槽处有锡膏。
一种采用半蚀刻工艺形成阶梯式框架引脚的制造方法，按照如下步骤进行：
第一步，按照传统工艺完成上芯、压焊、塑封工序，芯片通过焊线与框架连接，并被塑封体包围；
第二步，在框架背面的框架引脚处进行化学蚀刻，形成凹槽；
第三步，在框架背面的框架载体和框架引脚处上锡膏，包括在框架引脚处形成的凹槽内上锡膏；
第四步，从框架正面塑封体开始，沿着凹槽中心线用刀具切割，直至完成分离。
附图说明
图1为按照传统工艺完成上芯、压焊、塑封工序后的封装件图；
图2为塑封完成后进行框架背面蚀刻，蚀刻后图；
图3为蚀刻完成后再进行上锡、切割图。
图中，1为芯片、2为塑封体、3为框架载体、4为框架引脚、5为凹槽、6为锡膏、7为凹槽中心线。
具体实施方式
如图3所示，一种采用半蚀刻工艺形成阶梯式框架引脚，所述框架引脚4在框架背面，其上有凹槽5，所述凹槽5处有锡膏6。
一种采用半蚀刻工艺形成阶梯式框架引脚的制造方法，按照如下步骤进行：
第一步，按照传统工艺完成上芯、压焊、塑封工序，芯片1通过焊线与框架连接，并被塑封体2包围，如图1所示；
第二步，在框架背面的框架引脚4处进行化学蚀刻，形成凹槽5，如图2所示；
第三步，在框架背面的框架载体3和框架引脚4处上锡膏6，包括在框架引脚4处形成的凹槽5内上锡膏6，如图3所示；
第四步，从框架正面塑封体2开始，沿着凹槽中心线7用刀具切割，直至封装件完成分离，如图3所示。

Claims (2)

1.一种采用半蚀刻工艺形成阶梯式框架引脚，其特征在于，所述框架引脚（4）在框架背面，其上有凹槽（5），所述凹槽（5）处有锡膏（6）。
2.一种采用半蚀刻工艺形成阶梯式框架引脚的制造方法，其特征在于，按照如下步骤进行：
第一步，按照传统工艺完成上芯、压焊、塑封工序，芯片（1）通过焊线与框架连接，并被塑封体（2）包围；
第二步，在框架背面的框架引脚（4）处进行化学蚀刻，形成凹槽（5）；
第三步，在框架背面的框架载体（3）和框架引脚（4）处上锡膏（6），包括在框架引脚（4）处形成的凹槽（5）内上锡膏（6）；
第四步，从框架正面塑封体（2）开始，沿着凹槽中心线（7）用刀具切割，直至完成分离。
CN201510990730.5A 2015-12-25 2015-12-25 一种采用半蚀刻工艺形成阶梯式框架引脚及其制造方法 Pending CN105470231A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1638111A (zh) * 2003-12-25 2005-07-13 株式会社瑞萨科技 半导体元件的制造方法
US20110244629A1 (en) * 2010-04-01 2011-10-06 Zhiwei Gong Packaging Process to Create Wettable Lead Flank During Board Assembly
CN102347225A (zh) * 2010-08-03 2012-02-08 凌力尔特有限公司 用于端子的侧镀的激光加工
CN205303418U (zh) * 2015-12-25 2016-06-08 华天科技（西安）有限公司 一种采用半蚀刻工艺形成阶梯式框架引脚

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1638111A (zh) * 2003-12-25 2005-07-13 株式会社瑞萨科技 半导体元件的制造方法
US20110244629A1 (en) * 2010-04-01 2011-10-06 Zhiwei Gong Packaging Process to Create Wettable Lead Flank During Board Assembly
CN102347225A (zh) * 2010-08-03 2012-02-08 凌力尔特有限公司 用于端子的侧镀的激光加工
CN205303418U (zh) * 2015-12-25 2016-06-08 华天科技（西安）有限公司 一种采用半蚀刻工艺形成阶梯式框架引脚

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