CN105097755A - 单体化封装的方法和引线框 - Google Patents

单体化封装的方法和引线框 Download PDF

Info

Publication number
CN105097755A
CN105097755A CN201510234604.7A CN201510234604A CN105097755A CN 105097755 A CN105097755 A CN 105097755A CN 201510234604 A CN201510234604 A CN 201510234604A CN 105097755 A CN105097755 A CN 105097755A
Authority
CN
China
Prior art keywords
encapsulation
lead frame
matrix array
predefine
encapsulant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510234604.7A
Other languages
English (en)
Inventor
邱尔万
林丽叶
薛长宙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN105097755A publication Critical patent/CN105097755A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及单体化封装的方法和引线框。提供一种单体化封装的矩阵阵列的方法，其中该方法包括：提供封装的矩阵阵列，其中矩阵阵列被形成在引线框上；通过穿孔工艺来切割引线框的预定义引线；以及通过锯切工艺来单体化封装的矩阵阵列的封装。

Description

单体化封装的方法和引线框
技术领域
各种实施例涉及单体化封装的方法和引线框。
背景技术
半导体芯片被制作、测试和封装用于制造电子模块。利用常规的半导体塑料封装工艺，几个芯片在被称为引线框的载体上被同时处理并且封装的所谓的矩阵阵列被形成。在封装已被完成并且引线已被切割且被最终形成（例如在相同方向上弯曲以允许板安装）之后，从引线框将器件或芯片封装单体化被如下执行。器件仍被连杆（其是引线框的片段）保持到引线框外轨。在常规的单体化操作期间，在这些轨道正被保持在适当的位置时器件被冲模（punch）向上推动，连杆最终折断。通过在穿孔工艺期间以弯曲和法向应力的组合压弯连杆的材料来折断连杆。
切割或折断的连杆典型地在穿孔工艺之后突出，从而导致因突出的连杆的撞击或碰撞引起的其它封装的成型化合物的潜在损坏。
发明内容
各种实施例提供单体化封装的矩阵阵列的方法，其中该方法包括：提供封装的矩阵阵列，其中矩阵阵列被形成在引线框上；通过穿孔工艺来切割引线框的引线；以及通过锯切工艺来单体化封装的矩阵阵列的封装。
此外，各种实施例提供封装的矩阵阵列，该封装的矩阵阵列包括：引线框，该引线框包括布置在包括行和列的矩阵阵列中的多个芯片接收区域；以及密封材料，该密封材料密封引线框的至少部分，其中密封材料包括与矩阵阵列的行垂直延伸的预定义切割区域，其中预定义切割区域具有小于0.50mm的宽度。
而且，各种实施例提供用于制造多个芯片封装的方法，其中该方法包括：提供包括多个芯片接收区域的引线框；组装至少一个电子芯片到多个芯片接收区域的每个上；通过将密封材料成型到组装的电子芯片上来形成多个封装；通过穿孔工艺来切割引线框的引线；以及通过锯切工艺来单体化多个封装。
附图说明
在附图中，贯穿不同视图，同样的参考字符通常指代相同的部分。附图不必成比例，而是重点通常放在图解本发明的原理。在下面的描述中，各种实施例参考下面的附图来描述，其中：
图1A和1B示意性示出依据示范性实施例的引线框；
图2A到2C示意性示出压缩成型工艺；
图3A和3B示意性示出在压缩成型工艺之后的包括图1的引线框的封装的矩阵阵列；
图4A和4B示意性示出图2的并且图解穿孔步骤的矩阵阵列；
图5示意性示出图解锯切工艺的图4的矩阵阵列的横截面视图；
图6示意性图解依据示范性实施例的单体化方法的流程图；以及
图7示意性图解制造多个芯片封装的方法。
具体实施方式
在下面将解释测试探针和制造测试探针的方法的进一步示范性实施例。应当注意的是，在一个特定示范性实施例的上下文中描述的特定特征的描述也可以与其它示范性实施例组合。
词语“示范性”在本文中被用来表示“用作示例、实例、或说明”。在本文中被描述为“示范性”的任何实施例或设计不必被理解为比其它实施例或设计优选或有利。
各种示范性实施例提供用于封装的矩阵阵列的引线框，其中引线框被适配于通过锯切工艺来切割。特别地，引线框可以被适配为被用于封装的矩阵阵列，其中单体化以混合方式（即通过两个不同分离步骤或子步骤）来执行。例如，通过穿孔来执行的第一步骤将引线框的预定义引线断开或分离，而通过例如沿着引线框和/或至少部分密封引线框的密封材料的例如由两个切割线形成的预定义切割区域锯切来执行第二步骤，该第二步骤将封装彼此单体化或分离。
特别地，封装可以是例如双平无引线（DFN）封装。每个封装可以包括至少一个电子芯片例如晶体管或功率晶体管。引线框可以是铜引线框和/或可以通过冲压工艺来生产。密封材料可以是成型化合物或层压件或基于聚合物的材料。
特别地，预定义切割区域可以形成预定义断裂点或断裂线。即，“预定义切割区域”可以是引线框的部分或区段，其旨在以后在用于分离形成的封装的工艺中被切割或折断。此外或可替代地，预定义切割区域可以被形成在引线框上或在密封材料中，该密封材料被布置在引线框和布置在引线框上的可选的电子芯片上或者至少部分围住引线框和布置在引线框上的可选的电子芯片。应当注意的是，预定义切割区域可以定义或形成矩阵阵列的两个列之间的分离。即，预定义切割区域与矩阵阵列的行或带垂直延伸。特别地，例如通过两个切割线之间的距离形成的预定义切割区域的宽度被定义在与矩阵阵列的行或带平行的方向上。特别地，引线框可以包括铜或铝或任何其它合适的导电材料或者可以由铜或铝或任何其它合适的导电材料组成。
应当注意的是，可以可能使用这样的狭窄预定义切割区域或线，因为单行的矩阵阵列的封装的分离或单体化可以事后通过锯切工艺而不通过穿孔工艺来执行。在使用穿孔工艺来分离封装（如在通常已知的工艺中使用的那样）时，大于1mm（例如在1.5mm与3.1mm之间）的封装之间的距离将必须被维持，以便确保穿孔工艺不损坏封装。
因此，在该意义上，用于封装的矩阵阵列的引线框被提供，该封装的总的矩阵阵列或引线框被适配于通过锯切工艺来切割。特别关于分离，引线框被适配于事后以依据示范性实施例的方法来处理。
应当注意的是，当然矩阵阵列的行和列的命名或确定在原则上能够被互换。
依据根据示范性实施例的分离封装的矩阵阵列的方法，混合的切割或分离工艺可以被提供。混合的工艺可以生产封装外形，该混合工艺与已知的工艺类似但实现在矩阵阵列中的封装的更高密度和/或更耐用的封装而没有改变封装的占用面积或尺寸。
在下面描述将封装的矩阵阵列单体化的方法的进一步示范性实施例。然而，所描述的实施例的特征和元件也可以与依据示范性实施例的制造多个芯片封装的方法以及封装的矩阵阵列或引线框组合。
依据方法的示范性实施例，穿孔工艺在锯切工艺被执行之前被执行。
通过在锯切步骤之前执行穿孔工艺或穿孔步骤，可以可能的是：测试矩阵阵列的多个封装（例如完整的行或列）同时它们仍然彼此机械连接。特别地，穿孔工艺通过切割引线框的引线而将封装彼此分离，同时封装仍然彼此机械连接。
依据示范性实施例，该方法进一步包括在锯切工艺被执行之前测试矩阵阵列的至少一个封装。
优选地，在被用于切割或分离与不同封装有关的引线框的引线或预定义引线的穿孔步骤之后执行测试。特别地，测试可以是带测试，即封装的带或行的几个或所有封装可以被同时测试。因此，可以可能简化大量封装的测试。
依据方法的示范性实施例，针对封装的矩阵阵列的行的多个封装来同时执行测试。
特别地，行的所有封装可以被同时测试。一个带或行的几个或所有封装的测试可以对于在不要求包含的热沉的电隔离的产品中使用的封装而言是特别有利的。
依据示范性实施例，方法进一步包括标记至少一个测试的封装。
特别地，带或行的所有测试的封装或所有封装可以被标记。标记可以指示涉及测试结果的一些信息，例如一些质量要求或质量标准是否被满足。标记或标注可以通过任何合适的工艺例如通过激光标记来执行。
依据示范性实施例，方法进一步包括：通过将多个电子芯片组装到引线框上来形成封装的矩阵阵列；以及通过压缩成型而在引线框上形成密封材料。
特别地，电子芯片可以通过表面安装技术通过焊接工艺被布置到引线框上，通过任何其它合适的工艺可以被粘合或可以被布置在引线框上。例如，一个或多个电子芯片可以针对封装的矩阵阵列的每个封装来布置。
能够通过压缩成型工艺的使用来避免附加的废料残品（cull）和流道（runner）。依据该实施例，测试可以在封装被单体化之前执行并且它们在引线隔离之后仍然彼此连接。因此，可以存在增加的成品率，因为被用于附着流道和废料残品的引线框的额外空间可以利用该设计来节省。此外，引线框的生产可以经受较少约束，使得引线框可以被容易冲压，这也可以减少成本。
依据方法的示范性实施例，密封材料被形成为引线框上的连续带。
特别地，封装的单元可以在组装工艺之后以带形式来成型。这些单元可以对应于封装的矩阵阵列的行，该行例如可以通过预定义引线被彼此连接。封装的这些带或行然后可以通过穿孔工艺来分离。特别地，密封材料可以形成覆盖布置或组装在引线框的行上的所有电子芯片的连续带或元件。
通过使用依据示范性实施例的方法，可以可能特别在如下的情况下避免使连杆突出：封装的分离或单体化通过包括连续成型带的封装的带或行的锯切工艺来执行。特别地，这样的“齐平的”密封材料边沿可以仅通过锯切高效可实现并且没有专用的修整工具可以是必要的以便在连杆的区域中实现“齐平的”密封材料边沿。因此，非对称的连杆对于避免邻近的封装的连杆的碰撞可以不是必要的，该非对称性可以原本导致与其它封装的密封材料的直接接触（成型化合物的潜在切削）和非平衡连杆，该非平衡可以导致管芯垫稳定性的风险。
在下面描述封装的矩阵阵列的进一步示范性实施例。然而，所描述的实施例的特征和元件也可以与将依据示范性实施例的制造多个封装的方法和单体化封装的矩阵阵列的方法组合。
依据封装的矩阵阵列的示范性实施例，引线框包括在芯片接收区域的两个相对侧面上的预定义引线，其中预定义引线将一列的芯片接收区域连接。
特别地，在仅在封装的两个相对侧面上对引线预定义的情况下，例如在双平无引线封装的情况下，引线被优选地布置在将一列的芯片接收区域连接的侧面上。
术语“预定义引线”可以具体表示引线框的元件或区段，其在组装和单体化封装之后旨在形成单体化的封装的引线或连接元件。
依据封装的矩阵阵列的示范性实施例，预定义引线被彼此分离并且引线框的连杆连接一行的芯片接收区域。
即，矩阵阵列可以例如通过穿孔关于预定义引线（即逐行）来分离，但它可以不沿着预定义切割区域或切割线来切割。因此，封装的矩阵阵列或引线框可以形成被电分离但仍然彼此机械连接的封装的带、行或一维阵列。封装的该带或行然后可以被电测试。特别地，带的所有封装可以被同时测试，例如可以关于其电属性来测试。
依据封装的矩阵阵列的示范性实施例，引线框的连杆沿着预定义切割区域来切割。
特别地，整个矩阵阵列的或矩阵阵列的行的几个或所有连杆可以同时或在彼此之后被切割。连杆的切割可以将矩阵阵列的封装分离或单体化。
依据封装的矩阵阵列的示范性实施例，密封材料和引线框沿着相同切割边沿来切割。
特别地，密封材料和引线框可以在单个工艺步骤中例如沿着由预定义切割线形成的预定义切割区域来切割。因此，单体化的封装可以具有延伸经过密封材料和引线框的单个切割边沿。
依据封装的矩阵阵列的示范性实施例，密封材料的预定义切割区域由预定义切割线形成并且引线框包括与密封材料的预定义切割线重合的预定义切割线。
特别地，密封材料以及引线框可以包括形成预定义切割区域的预定义切割线，其中在到矩阵阵列上的顶视图中预定义切割区域可以彼此重合或重叠。
依据封装的矩阵阵列的示范性实施例，密封材料是从由成型化合物、层压件和基于聚合物的材料组成的组中的至少一个材料。
下面详细的描述参考附图，该附图通过说明的方式示出其中可以实践本发明的特定细节以及实施例。
图1A和1B示意性示出依据示范性实施例的引线框。特别地，图1A示出引线框100，该引线框100包括形成行或带102和列103的芯片接收区域101的矩阵阵列。图1B描绘示出芯片接收区域101的引线框100的细节，该芯片接收区域101具有在其上侧面和下侧面处的预定义引线104，即连接在图1的定向中的列的芯片接收区域。此外，预定义切割区域通过将每行102的芯片接收区域101分离的线105来示意性指示。该预定义切割区域的宽度可以在0.75mm以下的范围内，例如可以在0.1mm与0.7mm之间的范围内，优选地在0.2mm与0.5mm之间的范围内，像0.3mm，例如如在图1B中指示的。该范围比在普通引线框中的低，该普通引线框被用于事后通过穿孔工艺来单体化的封装的矩阵阵列。预定义切割区域105越过连杆106或与连杆106相交。
图2A到2C示意性示出压缩成型工艺。特别地，图2A以减少的比例示出图1A的引线框100，其中电子芯片被布置在该引线框100上或被组装到该引线框100上。图2B示出具有布置在其上的电子芯片210的引线框100的详细视图，该电子芯片210被电连接到在图2B中由线211指示的引线框。在图2B的下部分中，密封材料212被示意性描绘为布置在印模或冲模213的凹槽中。对于压缩成型，冲模213然后被压到被布置在支撑结构214上的引线框100上。此外，某一间隔物215被示意性描绘在图2B中，其确保引线框和/或组装的电子芯片不被冲模213损坏。在成型之后，成型带220被形成在引线框100上，每个成型带220包含封装的行或带，其在图2C中被示意性示出。
图3A和3B示意性示出在压缩成型工艺之后包括图1的引线框的封装300的矩阵阵列。特别地，图3A在更大的视图中示出包含成型带220的图2C的相同引线框100，而图3B示出图3A的引线框100的详细视图。应当注意的是，预定义引线104也能够在图3B中看到。密封材料330在图3A和3B中（以及在下面的图4A和4B中）通过形成密封材料或成型密封的边沿或边界的水平线331并且通过使布置在成型化合物下面的引线框的相应线虚线化来指示。
图4A和4B示意性示出图3的并且图解穿孔步骤的矩阵阵列300。特别地，预定义引线104和连杆106能够在图4A中看到，其分别连接相应列和相应行的芯片接收区域101或从此形成的封装。此外，线440指示沿着其执行穿孔步骤以便将列的预定义引线104彼此分离的线。能够看到的是，通过沿着这些线440的穿孔，矩阵阵列封装的列的引线被彼此电分离。图4B示出描绘图4A的矩阵阵列300的更大部分的图4A的概况视图。
图5示意性示出图4的包括布置在引线框100上的密封材料330的并且图解锯切工艺的矩阵阵列300的横截面视图。特别地，锯切步骤通过将封装的行或带的密封材料330分离的喷水器551来示意性指示。然而，锯切步骤可以通过机械锯切或通过激光锯切或切割来执行。此外，图5示出形成或布置在密封材料550中以及指示预定义切割区域的两个预定义切割线552。两个切割线之间的距离是在0.50mm以下，例如在0.02mm与0.35mm之间的范围内，更具体地在0.05mm与0.25mm之间的范围内，例如0.15mm。
图6示意性图解依据示范性实施例的单体化方法600的流程图。特别地，将封装的矩阵阵列单体化的方法600包括提供封装的矩阵阵列，其中矩阵阵列被形成在引线框上（步骤601）。在随后的步骤602中，引线框的引线通过穿孔工艺来切割。此外，封装的矩阵阵列的封装通过锯切工艺来分离或单体化（步骤602）。因此，单体化在引线框上形成的芯片封装的混合工艺可以被提供，其中单体化以两个子步骤（穿孔步骤和锯切步骤）执行。
图7示意性图解制造多个芯片封装的方法700。在第一步骤（步骤701）中，像提供引线框（例如如在图1中示出的引线框）的预组装步骤被执行。小方块或电子芯片被附着到这个引线框（步骤702）并且例如通过接合被电连接（步骤703）。事后，可选的等离子体刻蚀可以被执行，以便执行图样化工艺例如以形成往返于管芯的导电路径（步骤704）。然后，在下一个可选的步骤中，粘合促进剂可以被施加，以便改进模具的粘合（步骤705）。事后，成型工艺例如压缩成型工艺在步骤706中被执行，从而形成围住附着或组装的小方块的密封。此外，后成型固化步骤可以被执行（步骤707），其可以后面是去除毛刺（deflashing）和/或镀覆工艺（步骤708）。
随后，穿孔工艺被执行（步骤709），从而将引线框的预定义引线分离，使得在行或列中仍然彼此机械连接的封装被电断开。因此，可选的测试可以事后在带层级上，即在仍然机械连接并且形成带或行的封装上来执行（步骤710）。在执行测试之后，测试的带和/或整个带的封装一起可以例如通过激光或任何其它合适的标记方法来标记或标注（步骤711）例如用于指示测试结果。随后，仍然机械连接的封装通过第二单体化子步骤来单体化（步骤712），该第二单体化子步骤由锯切步骤例如通过激光、机械锯切或喷水式锯切来执行。在下面，单体化的封装可以针对错误来扫描以及被包装。
虽然本发明已参考特定实施例被具体示出和描述，但是本领域技术人员应当理解的是，在不脱离如由所附权利要求书限定的本发明的精神和范围的情况下，可以在其中做出形式和细节上的各种改变。本发明的范围因而由所附权利要求书指示并且落入权利要求书的等效的意义和范围内的所有改变因此旨在被涵盖。

Claims (15)

1.一种单体化封装的矩阵阵列的方法，所述方法包括：
提供封装的矩阵阵列，其中矩阵阵列被形成在引线框上，
通过穿孔工艺来切割引线框的预定义引线；以及
通过锯切工艺来单体化封装的矩阵阵列的封装。
2.根据权利要求1的所述方法，其中所述穿孔工艺在锯切工艺被执行之前被执行。
3.根据权利要求1的所述方法，进一步包括：
在锯切工艺被执行之前，测试矩阵阵列的至少一个封装。
4.根据权利要求3的所述方法，其中针对封装的矩阵阵列的行的多个封装同时执行测试。
5.根据权利要求3的所述方法，进一步包括：
标记所述至少一个测试的封装。
6.根据权利要求1的所述方法，进一步包括：
通过将多个电子芯片组装到引线框上来形成封装的矩阵阵列；以及
通过压缩成型而在引线框上形成密封材料。
7.根据权利要求6的所述方法，其中所述密封材料被形成为引线框上的连续带。
8.一种封装的矩阵阵列，所述封装的矩阵阵列包括：
引线框，包括布置在包括行和列的矩阵阵列中的多个芯片接收区域；
密封材料，将引线框的至少部分密封，
其中密封材料包括与矩阵阵列的行垂直延伸的预定义切割区域，其中预定义切割区域具有小于0.50mm的宽度。
9.根据权利要求8的所述封装的矩阵阵列，其中所述引线框包括在芯片接收区域的两个相对侧面上的预定义引线，其中所述预定义引线将一列的芯片接收区域连接。
10.根据权利要求8的所述封装的矩阵阵列，其中预定义引线被彼此分离并且引线框的连杆连接一行的芯片接收区域。
11.根据权利要求8的所述封装的矩阵阵列，其中所述引线框的连杆沿着预定义切割区域来切割。
12.根据权利要求8的所述封装的矩阵阵列，其中所述密封材料和引线框沿着相同的切割边沿来切割。
13.根据权利要求8的所述封装的矩阵阵列，其中所述密封材料的预定义切割区域由预定义切割线形成并且引线框包括与所述密封材料的预定义切割线重合的预定义切割线。
14.根据权利要求8的所述封装的矩阵阵列，其中所述密封材料是由以下组成的组中的至少一个材料：
成型化合物；
层压件；以及
基于聚合物的材料。
15.一种用于制造多个芯片封装的方法，所述方法包括：
提供包括多个芯片接收区域的引线框；
组装至少一个电子芯片到多个芯片接收区域的每个上；
通过将密封材料成型到组装的电子芯片上来形成多个封装；
通过穿孔工艺来切割引线框的预定义引线；以及
通过锯切工艺来单体化多个封装。
CN201510234604.7A 2014-05-08 2015-05-08 单体化封装的方法和引线框 Pending CN105097755A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/272,568 US20150325503A1 (en) 2014-05-08 2014-05-08 Method of singularizing packages and leadframe
US14/272568 2014-05-08

Publications (1)

Publication Number Publication Date
CN105097755A true CN105097755A (zh) 2015-11-25

Family

ID=54336741

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510234604.7A Pending CN105097755A (zh) 2014-05-08 2015-05-08 单体化封装的方法和引线框

Country Status (3)

Country Link
US (1) US20150325503A1 (zh)
CN (1) CN105097755A (zh)
DE (1) DE102015107232A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326424A (zh) * 2018-12-14 2020-06-23 无锡华润矽科微电子有限公司 Qfn框架的布置及封装生产方法
CN112185707A (zh) * 2020-11-06 2021-01-05 株洲宏达电子股份有限公司 一种片式钽电容器的制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102020101098B4 (de) * 2020-01-17 2022-05-12 Infineon Technologies Ag Leadframe, gekapseltes Package mit gestanzter Leitung und gesägten Seitenflanken, und entsprechendes Herstellungsverfahren

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6483177B1 (en) * 2000-10-09 2002-11-19 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US20030011006A1 (en) * 2000-11-02 2003-01-16 St Assembly Test Services Ltd. Leaded semiconductor packages and method of trimming such packages
US6521987B1 (en) * 1998-10-21 2003-02-18 Amkor Technology, Inc. Plastic integrated circuit device package and method for making the package
US6525405B1 (en) * 2000-03-30 2003-02-25 Alphatec Holding Company Limited Leadless semiconductor product packaging apparatus having a window lid and method for packaging
US6858470B1 (en) * 2003-10-08 2005-02-22 St Assembly Test Services Ltd. Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof
US20110129962A1 (en) * 2009-11-30 2011-06-02 Alpha And Omega Semiconductor Incorporated Encapsulation method for packaging semiconductor components with external leads

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7051427B2 (en) * 2000-09-29 2006-05-30 Texas Instruments Incorporated Integrated circuit trimming device broken die sensor
US6783316B2 (en) * 2001-06-26 2004-08-31 Asm Assembly Automation Limited Apparatus and method for testing semiconductor devices
US6717822B1 (en) * 2002-09-20 2004-04-06 Amkor Technology, Inc. Lead-frame method and circuit module assembly including edge stiffener
US7125747B2 (en) * 2004-06-23 2006-10-24 Advanced Semiconductor Engineering, Inc. Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe
JP5322817B2 (ja) * 2009-07-17 2013-10-23 富士フイルム株式会社 ３次元画像撮像装置及び３次元画像表示方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521987B1 (en) * 1998-10-21 2003-02-18 Amkor Technology, Inc. Plastic integrated circuit device package and method for making the package
US6525405B1 (en) * 2000-03-30 2003-02-25 Alphatec Holding Company Limited Leadless semiconductor product packaging apparatus having a window lid and method for packaging
US6483177B1 (en) * 2000-10-09 2002-11-19 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US20030011006A1 (en) * 2000-11-02 2003-01-16 St Assembly Test Services Ltd. Leaded semiconductor packages and method of trimming such packages
US6858470B1 (en) * 2003-10-08 2005-02-22 St Assembly Test Services Ltd. Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof
US20110129962A1 (en) * 2009-11-30 2011-06-02 Alpha And Omega Semiconductor Incorporated Encapsulation method for packaging semiconductor components with external leads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326424A (zh) * 2018-12-14 2020-06-23 无锡华润矽科微电子有限公司 Qfn框架的布置及封装生产方法
CN112185707A (zh) * 2020-11-06 2021-01-05 株洲宏达电子股份有限公司 一种片式钽电容器的制备方法

Also Published As

Publication number Publication date
DE102015107232A1 (de) 2015-11-12
US20150325503A1 (en) 2015-11-12

Similar Documents

Publication Publication Date Title
CN101611484B (zh) 无引脚半导体封装及其制造方法
CN100576477C (zh) 形成引脚模块阵列封装的方法
US9363901B2 (en) Making a plurality of integrated circuit packages
US9184118B2 (en) Micro lead frame structure having reinforcing portions and method
CN104854695A (zh) 具有印刷形成的端子焊盘的引线载体
US8865524B2 (en) Lead carrier with print-formed package components
US20190115289A1 (en) Lead frame assembly
CN105097755A (zh) 单体化封装的方法和引线框
US9673122B2 (en) Micro lead frame structure having reinforcing portions and method
JP2010021374A (ja) 半導体パッケージ
USRE43818E1 (en) Fabrication of an integrated circuit package
JP2003209215A (ja) 半導体用リードフレーム
US7943424B1 (en) Encapsulation method for packaging semiconductor components with external leads
US8643156B2 (en) Lead frame for assembling semiconductor device
US20200235042A1 (en) Electronic device with lead pitch gap
CN104681528A (zh) 停止集成电路引线成品上树脂溢出和模具溢料的方法和设备
CN106796931B (zh) 引线框、半导体装置的制造方法
CN114981940A (zh) 在坚固的封装衬底中具有分割裸片垫的经封装电子装置
CN206584920U (zh) 分离式预成形封装导线架
US20150144389A1 (en) Method of minimizing mold flash during dambar cut
CN104347570B (zh) 无引线型半导体封装及其组装方法
CN103400811A (zh) 一种基于框架采用特殊点胶技术的扁平封装件及其制作工艺
CN109904081B (zh) 基于idf引线框架的半导体产品的封装方法
US20150097278A1 (en) Surface mount semiconductor device with additional bottom face contacts
JPH1079463A (ja) 半導体装置製造用切断装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20151125