CN104347570B - 无引线型半导体封装及其组装方法 - Google Patents

无引线型半导体封装及其组装方法 Download PDF

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CN104347570B
CN104347570B CN201310317710.2A CN201310317710A CN104347570B CN 104347570 B CN104347570 B CN 104347570B CN 201310317710 A CN201310317710 A CN 201310317710A CN 104347570 B CN104347570 B CN 104347570B
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wick
lead
semiconductor packages
corner
die body
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CN104347570A (zh
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白志刚
姚晋钟
王志杰
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NXP USA Inc
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Abstract

本发明公开了一种无引线型半导体封装及其组装方法,无引线型半导体封装具有用于形成模体的模盖。模体的角部以模柱来增强使得角部具有圆形突起而非形成90°角。模柱防止角部焊盘剥落。

Description

无引线型半导体封装及其组装方法
技术领域
本发明涉及集成电路封装,并且更特别地涉及无引线型半导体封装以及无引线型封装的组装方法。
背景技术
响应于对尺寸和成本减小的且功能和性能增加的信息及通信产品的不断增加的需求,半导体封装已发展为适应具有更多I/O和更小占用面积的增大的构件密度。一种这样的封装是无引线型半导体封装,例如方形扁平无引线封装(QFN)。无引线半导体封装是使用引线框组装的树脂密封型器件,并且通过模塑于引线框的一侧上来形成。引线平齐于模体(mold body),而不是从模体延伸出。
但是,由集成增加的功能与小型化而引起不同的挑战。例如,对于QFN封装,在多次插入测试以及通过托盘或载带和卷轴的装运过程中,封装的冲裁(punch)角部焊盘(pad)可能会剥落,这会严重地影响封装的质量并且能够导致客户质量事故(CQI)。
因此,所希望的是改进封装以解决上述问题。
附图说明
本发明以示例的方式来说明但并不受在附图中示出的本发明的实施例所限制,在附图中相同的附图标记指示相似的元件。元件在附图中出于简单和清晰起见而示出,并不一定按比例绘制。
图1是常规的无引线半导体封装的透视图;
图2是图1所示的常规封装的一部分的局部放大图;
图3是根据本发明的一种实施例的无引线半导体封装的透视图;
图4是图3所示的半导体封装的一部分的局部放大图;
图5A是根据本发明的一种实施例的在部分组装的状态下的图3的封装的一部分的透视图;
图5B是在经过模塑处理之后的组装期间的图3的封装的一部分的透视图;
图5C是在经过冲裁操作之后的组装期间的图3的封装的一部分的透视图;以及
图6是以示例的方式来示出根据本发明的一种实施例的用于制造图3所示的封装的方法的流程图。
具体实施方式
关于附图的详细描述旨在作为关于本发明的当前优选的实施例的描述,而并非旨在表示可以用以实现本发明的唯一形式。应当理解,相同的或相当的功能可以通过意欲包含于本发明的精神和范围之内的不同实施例来实现。
图1是常规的无引线型半导体封装10的透视图。封装10是包括以模塑料包封的管芯(未示出)的QFN封装,该模塑料形成模盖(moldcap)12。图2是半导体封装10的角部14的局部放大图。模盖12具有模体16以及沿着模体16的底面及侧面暴露出来的多个引线18。引线18在封装10的侧面上的暴露部分可以具有沿着其侧翼(flank)的凹槽或沟槽,称为可润湿侧翼。引线18为在管芯与外部器件(例如,电路板(未示出))之间的功率及信号传输提供通路。
一般地,常规的半导体封装10以下列步骤或过程来组装:提供包括管芯基岛(flag)以及围绕管芯基岛的引线的引线框;用于将管芯贴附于管芯基岛的管芯键合;用于以键合丝线将管芯电连接至引线的丝线键合;用于以模盖12来覆盖管芯、引线及键合丝线的包封;以及用于将所组装的器件从同时形成的相邻器件中分离出的修整和成形。在修整和成形步骤中,引线框连结杆以及引线的延伸超出模体16之外的部分通过例如冲裁来切除。如果通过冲裁,则引线18和连结杆在单个步骤中冲裁。
半导体封装10可以通过将引线18的底面匹配并焊接于电路板上的匹配图形来安装。但是,本发明人已经发现,在经受到多次插入测试时,引线18在角部14处易于从模体16剥落下来。而且,与角部14相邻的引线18在电测试和托盘处理期间具有开裂的倾向。具体地,当对封装10执行电测试时,封装10利用在角部14与插口之间的摩擦力来定位于测试仪(未示出)的插口内。因而,与角部14相邻的引线18受到机械剥离应力,这使得引线18在角部14处存在高剥落风险。同时,在封装10处于托盘内时的处理期间,封装10的角部14能够碰撞托盘(未示出),这同样能够导致角部引线18被破坏。
本发明提供了可克服上述角部引线剥落问题的一种半导体封装及组装方法。在一种实施例中,本发明提供了一种半导体封装,包括:具有上表面和下表面的管芯基岛;贴附于管芯基岛的上表面的半导体管芯;围绕着管芯基岛的多个引线,其中每个引线都具有顶面以及与顶面相反的底面,并且顶面以键合丝线来与半导体管芯电连接;以及用于覆盖半导体管芯、键合丝线以及每个引线的至少一部分的模盖。模盖包括总体上为矩形的模体。模体已经增强了角部,所述角部包括从每个所述角部突出的模柱(mold column)。
在另一种实施例中,本发明提供了一种组装半导体封装的方法,包括以下步骤:提供包括管芯基岛以及围绕管芯基岛的多个引线的引线框,其中每个引线都具有顶面以及与顶面相反的底面;将半导体管芯键合于管芯基岛的顶面上;以键合丝线使在半导体管芯的顶面上的焊盘与引线的顶面电连接;通过以模塑料包封管芯基岛、半导体管芯、键合丝线以及每个引线的至少一部分来形成模盖,其中模盖包括总体上为矩形的模体,所述模体具有包括从每个所述角部突出的模柱的增强的角部;并且执行用于去除引线框的延伸超出所述模盖之外的若干部分的修整和成形操作。
在一种实施例中,修整和成形操作包括:用于去除引线的延伸超出模体之外的若干部分以及引线从其中延伸出的引线框的导轨的第一冲裁处理,以及用于去除位于与导轨相接的引线框的外角部处的连结杆焊盘的第二冲裁处理。
以上相当宽泛地概述了本发明的特征及技术优点,以便下面关于本发明的详细描述可以被更好地理解。以下将描述本发明另外的特征及优点,这些特点及优点构成了本发明的权利要求书的主题。本领域技术人员应当意识到,所公开的概念和具体的实施例可以被容易地用作用于修改或设计用于实现本发明的相同目标的其他结构或过程的基础。本领域技术人员还应当意识到,此类等价的构造并不脱离在所附的权利要求书中阐明的本发明的精神和范围。
现在参照图3,图中示出了根据本发明的一种实施例的无引线型半导体封装20的透视图。封装20是具有包括模体24的模盖22的QFN型封装。模体24的形状总体上为矩形,具有四个角部26以及分别形成于这四个角部26中的每个角部处的模柱28。模柱28形成于模体24的角部26处,使得在所示的实施例中,模体24的角部26被圆形化。在常规的封装中,角部成90°角,然而在本发明中,由于模柱28从模体24突出,角部26不成90°角。模盖22可以通过模塑处理用环氧树脂材料或塑料来形成,如在本技术领域内所知的。
图4是封装20的角部26之一的放大透视图。在图4中,能够看出,模柱28具有与模体24的高度相等的高度。但是,在其他实施例中,模柱28的高度能够小于模体24的高度。模柱28增强了角部26,这将在下文更详细地讨论。
再次参照图3,封装20还具有在模体24的底部边缘附近暴露出来的多个引线30。引线30还可以在封装20的外围边缘附近的封装20的底面上暴露出来。在封装10的侧面附近暴露出来的引线30可以包含凹槽或沟道,使得它们为可润湿侧翼。可润湿侧翼意指引线30的暴露边缘包含电镀的(而非裸铜)沟道或凹槽,这允许焊料流入沟道内并且粘附于引线的侧面。可润湿侧翼允许对焊点的视觉检测。
图5A是处于局部组装状态的封装20的透视图,特别地示出了封装20的引线框32的一部分。引线框32包括用于支持半导体管芯36的管芯基岛34。如本技术领域所已知的,管芯36以管芯贴附粘合剂(未示出)贴附于管芯基岛34的表面。管芯基岛34被调整大小并被成形为接纳管芯36,因而在所示的实施例中,管芯基岛34如同管芯36一样总体上为矩形,并且略微大于管芯36。但是,本发明也可以使用其他尺寸及形状的管芯基岛,例如,X形基岛或尺寸更小的基岛。
引线框32具有与管芯基岛34间隔开且围绕管芯基岛34的多个导轨38。因而,由于基岛34为矩形,因而存在四个围绕基岛34的导轨38(在图5A中示出了两个导轨的一些部分)。引线30从导轨38向管芯基岛34延伸。还存在从导轨38延伸出以远离管芯基岛34的与引线30相反的其他引线40。其他引线40实际上向另一管芯基岛(未示出)延伸,如本技术领域所知的,因为引线框32是形成为允许同时组装多个封装的阵列的多个引线框之一。导轨38在角部连结杆焊盘42处相接。根据本发明,优选的是角部连结杆焊盘42具有比导轨38的宽度大的宽度,因为连结杆焊盘42被用来支持模柱28。连结杆44通过从基岛34的角部延伸到连结杆焊盘42来使管芯基岛34与连结杆焊盘42互连。引线框32可以由导电材料(例如铜)形成,并且通常由可以用或者可以不用另一种金属(例如钯)来电镀的裸金属(Cu)板形成。
图5B是图5A的无引线半导体封装20在经过模塑处理之后的一部分的透视图,在该模塑处理中,管芯36、用于将管芯36连接至引线30(未示出)的键合丝线以及引线30的若干部分以模塑料来覆盖。也就是,模塑处理形成模盖22。模塑处理使用允许形成模柱28的改进的模腔(mold cavity),而不是使用总体上为矩形的标准模腔。能够看出,模盖22部分地覆盖着引线30(通至导轨38的部分),并且此外,在角部处,模柱28形成于角部连结杆焊盘42的一部分之上。因而,连结杆44的端部以及连结杆焊盘42的一部分支持着模柱28。
图5C是图5B的部分组装的封装20在经过了作为修整和成形处理的第一步骤之后的透视图。更特别地,在模塑或包封处理之后,第一冲裁操作被执行用于去除导轨38以及引线30的延伸超出模体24之外的部分。图5B示出了被去除之前的导轨38和引线30,而图5C示出了去除了导轨38以及引线30的若干部分之后的封装20。虽然冲裁处理是优选的,但是也能够使用其他分离处理,例如,以锯或激光来切割。在第一冲裁处理之后,第二冲裁处理被执行用于去除角部连结杆焊盘42的延伸超出模体24之外的若干部分。
图6是示出用于组装封装20的步骤的流程图。在第一步骤50中,提供包括管芯基岛以及围绕管芯基岛的多个引线的引线框。引线框可以包括形成于允许同时组装多个封装的矩阵内的多个引线框之一。每个引线都具有顶面以及与顶面相反的底面。引线框可以包括裸铜的或者电镀或局部电镀的铜框,如本技术领域所知的。
在第二步骤52中,使用粘合剂将半导体管芯贴附或键合于管芯基岛的顶面上,并且然后将半导体管芯的顶面上的焊盘使用已知的丝线键合工艺以键合丝线来与引线的顶面电连接。
在第三步骤54中,包封或模塑处理被执行用于形成用于覆盖管芯、键合丝线以及引线框的若干部分的模盖22。模塑处理包括形成图3所示的角部模柱28。在一种实施例中,模盖包括总体上为矩形的模体,模体具有包括从每个所述角部突出的模柱的增强的角部。
最后,在步骤56中,修整和成形操作被执行用于去除引线框的延伸超出模盖之外的若干部分。在一种优选的实施例中,修整和成形处理包括用以去除引线框导轨以及引线30的若干部分的第一冲裁操作,随后是用以去除连结杆焊盘42的若干部分的第二冲裁操作。
上述实施例是关于单个半导体封装20来提供的。实际上,能够每次在包括多个引线框的矩阵配置中制造根据本发明的多个半导体封装20,该多个半导体封装20稍后在模塑处理之后被分离或“被切单”。结果,根据本发明能够快速且低成本地生产封装的电子器件。本领域技术人员应当了解如何应用本发明示出的单个半导体封装的制造方法来同时制造多个半导体封装。
虽然已经示出并描述了本发明的各种实施例,但是应当清楚,本发明并不限制于这些实施例。本领域技术人员应当清楚不脱离权利要求书所描述的本发明的精神和范围的众多的修改、变更、变化、替代及等价物。

Claims (12)

1.一种半导体封装,包括:
具有上表面和下表面的管芯基岛;
贴附于所述管芯基岛的所述上表面上的半导体管芯;
围绕所述管芯基岛的多个引线,其中所述引线的每一个具有顶面和与所述顶面相反的底面,并且所述顶面以键合丝线与所述半导体管芯电连接;以及
覆盖所述半导体管芯、键合丝线以及所述引线的每一个的至少一部分的模盖,其中所述模盖包括总体上为矩形的模体,并且其中所述模体具有增强的角部,其包括模柱,所述模柱从每个所述角部突出;
其中所述模柱形成于所述模体的角部,使得所述模体的角部被圆形化。
2.根据权利要求1所述的半导体封装,其中所述模盖由环氧树脂材料形成。
3.根据权利要求1所述的半导体封装,其中多个模柱中的每一个具有与所述模体的高度相等或比其小的高度。
4.根据权利要求1所述的半导体封装,其中所述引线的每一个的底面被暴露。
5.根据权利要求4所述的半导体封装,其中所述管芯基岛的所述下表面被暴露。
6.根据权利要求4所述的半导体封装,其中所述引线的远端被沿所述模体的侧边缘暴露。
7.根据权利要求1所述的半导体封装,其中所述模柱防止所述角部形成90°角。
8.一种组装半导体封装的方法,包括:
提供包括管芯基岛以及围绕所述管芯基岛的多个引线的引线框,其中所述引线的每一个具有顶面以及与所述顶面相反的底面;
将半导体管芯键合于所述管芯基岛的顶面;
以键合丝线将在所述半导体管芯的顶面上的焊盘与所述引线的顶面电连接;
通过以模塑料包封所述管芯基岛、所述半导体管芯、所述键合丝线以及所述引线的每一个的至少一部分来形成模盖,其中所述模盖包括总体上为矩形的模体,所述模体具有包括模柱的增强的角部,所述模柱从每个所述角部突出;以及
执行用于去除所述引线框的延伸超出所述模盖之外的若干部分的修整和成形操作;
其中所述引线框还包括多个导轨,所述多个导轨围绕所述管芯基岛并且所述引线从所述导轨向所述管芯基岛延伸,其中所述导轨的每一个平行于所述管芯基岛的侧面、从所述管芯基岛的角部延伸到所述导轨的多个连结杆、以及用于将所述连结杆中的相应连结杆与所述导轨在所述引线框的角部处接合的多个连结杆焊盘中的相应一个,并且其中所述修整和成形操作包括去除所述导轨和连结杆焊盘。
9.根据权利要求8所述的组装半导体封装的方法,其中所述导轨和连结杆焊盘通过冲裁来去除。
10.根据权利要求9所述的组装半导体封装的方法,其中第一冲裁操作被执行用于去除所述导轨,并且第二冲裁操作被执行用于去除所述连结杆焊盘。
11.根据权利要求9所述的组装半导体封装的方法,其中所述半导体封装是冲裁QFN封装。
12.根据权利要求8所述的组装半导体封装的方法,其中所述多个模柱中的每一个具有与所述模体的高度相等或比其小的高度。
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