SG10201810052WA - Packaging process and packaging structure - Google Patents

Packaging process and packaging structure

Info

Publication number
SG10201810052WA
SG10201810052WA SG10201810052WA SG10201810052WA SG10201810052WA SG 10201810052W A SG10201810052W A SG 10201810052WA SG 10201810052W A SG10201810052W A SG 10201810052WA SG 10201810052W A SG10201810052W A SG 10201810052WA SG 10201810052W A SG10201810052W A SG 10201810052WA
Authority
SG
Singapore
Prior art keywords
packaging
packaging structure
packaging process
Prior art date
Application number
SG10201810052WA
Inventor
Chien-Ming Chen
Beng Beng Lim
Original Assignee
Delta Electronics Int’L Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Electronics Int’L Singapore Pte Ltd filed Critical Delta Electronics Int’L Singapore Pte Ltd
Priority to SG10201810052WA priority Critical patent/SG10201810052WA/en
Priority to TW108102091A priority patent/TWI686878B/en
Priority to US16/262,363 priority patent/US11121110B2/en
Priority to CN201910097526.9A priority patent/CN111180348B/en
Priority to US16/824,021 priority patent/US11081461B2/en
Publication of SG10201810052WA publication Critical patent/SG10201810052WA/en

Links

Classifications

    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
SG10201810052WA 2018-11-12 2018-11-12 Packaging process and packaging structure SG10201810052WA (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SG10201810052WA SG10201810052WA (en) 2018-11-12 2018-11-12 Packaging process and packaging structure
TW108102091A TWI686878B (en) 2018-11-12 2019-01-18 Packaging process and packaging structure
US16/262,363 US11121110B2 (en) 2018-11-12 2019-01-30 Packaging process and packaging structure
CN201910097526.9A CN111180348B (en) 2018-11-12 2019-01-31 Packaging method and packaging structure
US16/824,021 US11081461B2 (en) 2018-11-12 2020-03-19 Packaging process and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG10201810052WA SG10201810052WA (en) 2018-11-12 2018-11-12 Packaging process and packaging structure

Publications (1)

Publication Number Publication Date
SG10201810052WA true SG10201810052WA (en) 2020-06-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201810052WA SG10201810052WA (en) 2018-11-12 2018-11-12 Packaging process and packaging structure

Country Status (4)

Country Link
US (2) US11121110B2 (en)
CN (1) CN111180348B (en)
SG (1) SG10201810052WA (en)
TW (1) TWI686878B (en)

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TWI723932B (en) * 2020-08-06 2021-04-01 強茂股份有限公司 Side wettable package component and its manufacturing method
US11387203B2 (en) 2020-09-08 2022-07-12 Panjit International Inc. Side wettable package
CN112509991A (en) * 2020-09-10 2021-03-16 成都芯源系统有限公司 Integrated circuit package structure, integrated circuit package unit and related manufacturing method
TWI777389B (en) * 2021-01-27 2022-09-11 鴻鎵科技股份有限公司 Package structure of dual transistors
TWI751008B (en) * 2021-01-27 2021-12-21 鴻鎵科技股份有限公司 Package structure of double transistor

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SG10201501021PA (en) * 2015-02-10 2016-09-29 Delta Electronics Int L Singapore Pte Ltd Package structure
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SG10201608773PA (en) * 2016-10-19 2018-05-30 Delta Electronics Intl Singapore Pte Ltd Method Of Packaging Semiconductor Device
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US10903148B2 (en) * 2018-04-10 2021-01-26 Microchip Technology Incorporated High performance multi-component electronics power module

Also Published As

Publication number Publication date
TWI686878B (en) 2020-03-01
US11121110B2 (en) 2021-09-14
US20200152593A1 (en) 2020-05-14
CN111180348A (en) 2020-05-19
US11081461B2 (en) 2021-08-03
CN111180348B (en) 2024-04-09
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