CN105706215A - 半导体元件的制造方法和半导体元件 - Google Patents
半导体元件的制造方法和半导体元件 Download PDFInfo
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- CN105706215A CN105706215A CN201480061046.2A CN201480061046A CN105706215A CN 105706215 A CN105706215 A CN 105706215A CN 201480061046 A CN201480061046 A CN 201480061046A CN 105706215 A CN105706215 A CN 105706215A
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- semiconductor
- crystal wafer
- semiconductor element
- film
- manufacture method
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Classifications
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Abstract
半导体元件(10)的制造方法包括:形成包含电介质膜(3)的半导体元件(10)的半导体元件形成工序;将区划半导体元件(10)的区划区域中的电介质膜(3)除去来形成划片区域(11)的划片区域形成工序;和在划片区域(11)进行划片的划片工序。
Description
技术领域
本发明涉及半导体元件的制造方法和半导体元件。
背景技术
近年来,具有高耐压特性且用于大电流流动的用途的功率器件被广为开发。在这样的功率器件的开发之中,氮化物半导体作为具有高绝缘击穿电场和高饱和电子速度的材料受到关注。其中,如非专利文献1和非专利文献2中介绍的那样,使用了GaN(氮化镓)类半导体的功率器件有望在将来的低损耗、高速功率开关系统中对节能作出巨大的贡献。
不过,在GaN功率器件的制造中,若进行硅制半导体晶圆的切断中通常使用的切刀划片,则会因为GaN膜较硬而无法顺利地切断半导体晶圆。另外,由于硅衬底与GaN膜的晶格常数和热膨胀系数的差异,在半导体晶圆中,硅类衬底与GaN膜的界面附近会产生较大的应力。该状态下,若在上述界面附近施加划片的机械冲击,则存在以上述界面附近为起点产生裂纹等问题。因此,在GaN功率器件的制造中多使用激光划片。
现有技术文献
专利文献
专利文献1:日本公开专利公报“特开2005-12206号(2005年1月13日公开)”
非专利文献
非专利文献1:上田哲三,“GaNパワーデバイスの現状とその応用”(GaN功率器件的现状及其应用),KEC情報(KEC信息),2013年1月,No.224,p.35-38
非专利文献2:生方映德,另5名,“Si基板上パワーデバイス向けMOCVD装置の開発”(以Si衬底上功率器件为对象的MOCVD装置的开发),大陽日酸技報(大阳日酸技报),2011年,No.30,p.23-28
发明内容
发明要解决的技术问题
不过,在激光划片中由于会产生碎屑(蒸发物残渣),因此需要除去该碎屑,并且切断要耗费时间,从而存在划片的成本升高的问题。另外,由于采用激光划片,存在芯片侧面导通而形成漏电路径(leakpath)的问题。
为了解决上述激光划片中的问题,存在利用蚀刻来除去GaN膜后进行划片的方法。例如,专利文献1中公开了一种在分割半导体晶圆前,在由氮化物类半导体构成的层叠体上形成电极用凹部和区划槽的氮化物类半导体元件的制造方法。通常,由于GaN是化学性质非常稳定的物质,所以GaN膜不溶解于常见的酸(盐酸、硫酸、硝酸等)和碱,在室温下不能被任何溶液蚀刻掉。因此,在上述专利文献1中,作为GaN膜的蚀刻技术优选采用基于反应离子蚀刻的干法蚀刻。
不过,干法蚀刻由于蚀刻速度较慢存在生产效率降低的问题。
本发明用于解决上述问题,其目的在于提供一种减少划片时衬底与GaN类半导体膜的界面附近产生的裂纹的GaN类半导体元件的制造方法。
解决问题的技术手段
为解决上述问题,本发明的一个技术方案的半导体元件的制造方法的特征在于,包括:半导体元件形成工序,在形成于衬底上的GaN类半导体膜上形成电介质膜,由此形成多个半导体元件;划片区域形成工序,将区划上述多个半导体元件的区划区域中的上述电介质膜除去,由此形成槽形状的划片区域;和划片工序,在上述划片区域进行划片,由此切割出上述多个半导体元件。
另外,本发明的一个技术方案的从半导体晶圆切割出的半导体元件的特征在于:该半导体晶圆包括形成在衬底上的GaN类半导体膜和形成在上述GaN类半导体膜上的电介质膜,上述半导体元件通过在除去了上述电介质膜的划片区域进行划片而从上述半导体晶圆被切割出。
发明效果
根据本发明的一个技术方案,能够起到以下技术效果:提供一种减少划片时衬底与GaN类半导体膜的界面附近产生的裂纹的GaN类半导体元件的制造方法。
附图说明
图1是用于说明本发明实施方式1的半导体芯片的制造方法的图,(a)是放大表示半导体晶圆的一部分的俯视图,(b)是半导体芯片的各制造工序中(a)所示的半导体晶圆的A-A线向视截面图。
图2是本发明实施方式1的半导体器件的截面图。
图3是用于说明本发明实施方式1的半导体器件的制造方法的各制造工序的示意图。
图4中,(a)是表示本发明实施方式1的整个半导体晶圆的俯视图,(b)是放大表示(a)所示的半导体晶圆的一部分的俯视图,(c)是(b)所示的半导体晶圆的B-B线向视截面图。
图5是表示现有的半导体芯片的制造方法中划片后的半导体晶圆的表面状态的图。
图6是表示现有的半导体芯片的制造方法中划片后的半导体晶圆的截面状态的图。
图7是表示实施方式1的半导体芯片的制造方法中划片后的半导体晶圆的表面状态的图。
图8是关于划片后的半导体晶圆的表面崩边(崩角)和层间裂纹的产生量,表示实施方式1的半导体芯片的制造方法与现有的半导体芯片的制造方法的比较的图。
图9是用于说明本发明实施方式2的半导体芯片的制造方法的图,(a)是放大表示半导体晶圆的一部分的俯视图,(b)是半导体芯片的各制造工序中(a)所示的半导体晶圆的C-C线向视截面图。
图10是表示实施方式2的半导体芯片的制造方法中划片后的半导体晶圆的表面状态的图。
图11是表示实施方式2的半导体芯片的制造方法下的划片后的半导体晶圆的状态的截面图。
图12是关于划片后的半导体晶圆的表面崩边和层间裂纹的产生量,表示实施方式1的半导体芯片的制造方法与实施方式2的半导体芯片的制造方法的比较的图。
具体实施方式
以下对本发明实施方式进行说明。
[实施方式1]
对本发明实施方式1的半导体芯片111的制造方法,基于图1至图8进行说明。
(半导体器件100的结构)
首先,对具备半导体芯片111的半导体器件100的结构进行说明。图2是本实施方式的半导体器件100的截面图。如图2所示,半导体器件100包括半导体芯片111(半导体元件)、基岛112、浆料113、焊盘115、引脚116、导线117和封装121。
半导体芯片111隔着浆料113搭载在基岛112上。并且,半导体芯片111与引脚116通过焊盘115和导线117彼此电连接。
基岛112上隔着浆料113搭载半导体芯片111。
为了将半导体芯片111搭载在基岛112上,浆料113使半导体芯片111与基岛112粘接。
焊盘115是用于与引脚116或其它的半导体芯片电连接的电极,设置在半导体芯片111的上端面上。
引脚116是用于与外部电连接的端子。引脚116的封装121外的部分与安装半导体器件100的配线衬底等连接,引脚116的封装121内的部分与导线117电连接。
导线117是用于使半导体芯片111与引脚116彼此电连接的连接配线。导线117的一端被连接在焊盘115上,导线117的另一端被连接在引脚116的上端面上。
封装121是将半导体芯片111、基岛112、浆料113、焊盘115、导线117以及一部分引脚116包覆的密封部件。
此处,半导体芯片111是从半导体晶圆101(参考图4)切割出元件区域10而得到的。详细内容将在后文描述。
(半导体器件100的制造方法的概要)
针对本实施方式的半导体器件100的制造方法的概要,基于图3说明各工序的内容。
如图3所示,本实施方式的半导体器件100的制造方法包括半导体晶圆制造工序(工序1)、表面保护胶带粘贴工序(工序2)、背面研磨工序(工序3)、划片胶带粘贴工序(工序4)、表面保护胶带剥离工序(工序5)、划片工序(工序6)、芯片焊接工序(工序7)、导线焊接工序(工序8)、树脂模塑工序(工序9)、外装电镀工序(工序10)、打标工序(工序11)、成型工序(工序12)、测试工序(工序13)、外观检验工序(工序14)和包装工序(工序15)。
在工序1的半导体晶圆制造工序中制造半导体晶圆101。关于半导体晶圆101的结构和制造的细节将在后文描述。
在工序2的表面保护胶带粘贴工序中,为了保护半导体晶圆101的表面(电路部)不受工序3中进行的背面研磨时的应力或污染的影响,在半导体晶圆101的表面粘贴表面保护胶带102。详细而言,将半导体晶圆101设置在利用胶带辊103a而移动的表面保护胶带102之下。通过将半导体晶圆101的表面按压在表面保护胶带102的面上,使表面保护胶带102粘贴在半导体晶圆101的表面。之后,使用胶带切刀将表面保护胶带102裁切成半导体晶圆101的形状,并将沿着半导体晶圆101切下的没用的胶带部分卷绕回收。
在工序3的背面研磨工序中,为了使半导体晶圆101成为规定的厚度而对半导体晶圆101的背面(没有粘贴表面保护胶带102的面)进行研磨。在背面研磨工序中,使用研磨轮105和研磨台106作为研磨装置。半导体晶圆101以背面向上的方式被固定在研磨台106上。研磨轮105配置在研磨台106的上方,在半导体晶圆101一侧具有磨石104。在使研磨台106和研磨轮105旋转的状态下利用磨石104对半导体晶圆101的背面进行研磨,从而将半导体晶圆101的厚度调整成与封装类型相应的规定的厚度。
在工序4的划片胶带粘贴工序中,作为工序6的划片(半导体晶圆101的切断)的准备工序,在半导体晶圆101的背面粘贴划片胶带107。详细而言,划片胶带107被粘贴在晶圆环108上,半导体晶圆101在晶圆环108的内侧被粘贴在划片胶带107上。
在工序5的表面保护胶带剥离工序中,使用剥离胶带109将表面保护胶带102从半导体晶圆101剥离。详细而言,将利用胶带辊103b而移动的带状的剥离胶带109粘贴在表面保护胶带102上,之后使其离开半导体晶圆101,从而将表面保护胶带102从半导体晶圆101剥离。
在工序6的划片工序中,半导体晶圆101被切断(划片)成规定的芯片尺寸(元件区域10:参考图4)。半导体晶圆101使用划片刀110沿着后述的划片区域11(切断线:参考图4)在纵向和横向上被切断。半导体晶圆101经划片而按元件区域10(参考图4)被单片化,从而形成半导体芯片111即半导体元件。
在工序7的芯片焊接工序中,将半导体芯片111配置在基岛112上,并搭载到引脚框架(未图示)上。详细而言,在基岛112上涂布浆料113。并且,将利用吸具114拾取的半导体芯片111载置到浆料113上的规定位置处。接着,在将半导体芯片111载置到浆料113的规定位置处的状态下,使浆料113热固化。
在工序8的导线焊接工序中,将半导体芯片111与引脚116或将半导体芯片111与其它的半导体芯片电连接。详细而言,利用导线117将焊盘115与引脚116电连接,来将半导体芯片111与引脚116电连接。并且,同样地利用导线117将焊盘115与形成在其它的半导体芯片111上的焊盘115电连接,来将半导体芯片111与其它的半导体芯片111电连接。导线117例如能够使用金线、银线、铜线、铝线等。
在工序9的树脂模塑工序中,利用模塑树脂119包覆半导体芯片111、基岛112、浆料113、焊盘115、导线117以及一部分引脚116,形成上述的封装121。详细而言,在设置了引脚框架(未图示)的模具118中,利用柱塞120注入模塑树脂119(塑料树脂),之后使模塑树脂119热固化来形成封装121。
在工序10的外装电镀工序中,除去露出到外引脚即没有被模塑树脂119包覆的引脚116上的模塑树脂毛边。之后,对外引脚实施焊料电镀,使得用户能够将半导体器件100焊接到衬底上。
在工序11的打标工序中,在封装121的表面标示出类型名等必要信息。必要信息的打标例如使用这样的方法,即,利用热固化墨等墨水来印刷必要信息,或利用激光照射来在封装表面标刻必要信息。
在工序12的成型工序中,从引脚框架将各封装逐个地切断分离,并使用模具将外引脚加工成规定的形状。
在工序13的测试工序中,使用测试仪来判断制成的封装是良品还是不良品。
在工序14的外观检验工序,按照设定的检验标准的内容确认制成的半导体器件100的最终外观状态。在外观检验中,例如使用由人来进行确认的目视检验或基于检验仪的测量检验等。
在工序15的包装工序中,将制成的半导体器件100收纳到规定的包装中。作为上述规定的包装,例如有使用了塑料套管的套管包装,使用了塑料托盘的托盘包装和使用了压纹带的带卷包装等。并且,对上述包装进行铝层压密封,从而实现封装的防湿包装。另外,将上述包装收纳到指定的收纳盒中出厂。
以上是制造半导体器件100时必要的工序的概要。本实施方式的半导体芯片111的制造方法在与工序1的半导体晶圆制造工序和工序6的划片工序对应的工序中尤其具有特点。下面详细进行说明。
(半导体晶圆101的结构)
首先,基于图4说明半导体晶圆101的结构。图4的(a)是表示整个半导体晶圆101的俯视图。图4的(b)是放大表示半导体晶圆101的一部分的俯视图。图4的(c)是(b)所示的半导体晶圆101的B-B线向视截面图。
如图4的(a)、(b)所示,半导体晶圆101包括多个元件区域10(半导体元件)和划片区域11。划片区域11设置成格子状以区划多个元件区域10。另外,各元件区域10由密封环4包围,在密封环4的内侧形成电路和焊盘115。
另外,如图4的(c)所示,半导体晶圆101包括硅类衬底1、GaN类半导体膜2、电介质膜3、密封环4、保护膜5和划片区域11。
GaN类半导体膜2形成在硅类衬底1(衬底)的表面。电介质膜3和密封环4形成在GaN类半导体膜2上。划片区域11形成在相对的密封环4之间。
(半导体芯片111的各制造工序中的半导体晶圆101)
接着,基于图1的(a)、(b)对半导体芯片111的各制造工序中的半导体晶圆101进行说明。图1的(a)、(b)是用于说明本实施方式的半导体芯片111的制造方法的图。详细而言,图1的(a)是放大表示半导体晶圆101的一部分的俯视图。而图1的(b)是半导体芯片111的各制造工序中图1的(a)所示的半导体晶圆101的A-A线向视截面图。此处,图1的(b)所示的第一工序至第七工序与上述的半导体器件100的制造方法的各制造工序具有如下对应。
第一工序至第四工序与上述工序1的半导体晶圆制造工序对应。第五工序与上述工序2的表面保护胶带粘贴工序和工序3的背面研磨工序对应。第六工序与上述工序4的划片胶带粘贴工序和工序5的表面保护胶带剥离工序对应。第七工序与上述工序6的划片工序对应。以下对第一工序至第七工序进行说明。
在第一工序中,在硅类衬底1上形成GaN类半导体膜2。硅类衬底1的厚度和大小可适当设定,本实施方式中硅类衬底1厚度为625μm,尺寸为6英寸。
在第二工序(半导体元件形成工序)中,在GaN类半导体膜2上形成电介质膜3,并形成多个元件区域10(半导体元件)。另外,在多个元件区域10中形成电路。并且,在各元件区域10的周边以包围元件区域10的方式形成密封环4。密封环4以从电介质膜3突出的方式形成。
另外,在半导体晶圆101中,由密封环4包围的元件区域10以外的部位成为区划区域9。换言之,在第二工序中,以将半导体晶圆101区划为多个元件区域10的方式,呈格子状地形成区划区域9。
在第三工序中,在电介质膜3和密封环4上形成保护膜5。
在第四工序(划片区域形成工序)中,在区划区域9中通过蚀刻而除去电介质膜3和保护膜5,从而形成槽6即划片区域11。详细而言,在半导体晶圆101上,遮蔽区划区域9以外的区域。换言之,在元件区域10的位置配置掩模(未图示)。之后,以除去电介质膜3和保护膜5的方式进行蚀刻(例如湿法蚀刻)。其结果,配置有掩模的元件区域10的腐蚀受到抑制,元件区域10被保留,而没有被遮蔽的区划区域9中的电介质膜3和保护膜5被除去,形成了槽6即槽形状的划片区域11。此时,本实施方式中将区划区域9内的电介质膜3和保护膜全部除去。槽6的宽度可适当设定,本实施方式中槽6的宽度为90μm。
在第五工序中,为了保护半导体晶圆101的表面不受半导体晶圆101的背面研磨时的应力或污染的影响,在半导体晶圆101的表面粘贴表面保护胶带102。另外,为了使半导体晶圆101成为规定的厚度而对半导体晶圆101的背面进行研磨。此时,由于硅类衬底1与GaN类半导体膜2的热膨胀类数和晶格常数存在差异,在硅类衬底1与GaN类半导体膜2的界面附近会产生较大的应力。因此,在进行半导体晶圆101的背面研磨时,半导体晶圆101可能破裂。为此,为了避免半导体晶圆101破裂,也可以使用WSS(wafersupportsystem,晶圆承载系统)。
在第六工序中,作为划片的准备工序,将半导体晶圆101粘贴到划片胶带107上。并且,使用剥离胶带109(参考图3)将表面保护胶带102从半导体晶圆101剥离。此时顺序也可以颠倒,例如先将表面保护胶带102剥离,之后再粘贴到划片胶带107上。
在第七工序(划片工序)中,将半导体晶圆101切断成规定的芯片尺寸。通过在除去电介质膜3和保护膜5而形成的槽6即划片区域11中进行划片,来切断半导体晶圆101。半导体晶圆101经切断而单片化,形成半导体芯片111。
在本实施方式中,半导体晶圆101由区划区域9区划成多个元件区域10。因此,通过在形成于区划区域9中的划片区域11进行划片,能够得到多个半导体芯片111(半导体元件)。另外,划片区域11通过在区划区域9中除去电介质膜3和保护膜5而形成。因此,能够在除去了电介质膜3和保护膜5的划片区域11中切断半导体晶圆101,所以能够减少切断半导体晶圆101时在硅类衬底1与GaN类半导体膜2的界面附近产生的层间裂纹、表面崩边和膜剥离。因而,无需使用激光划片就能够减少上述层间裂纹等,所以能够抑制制造成本。另外,无需蚀刻GaN类半导体膜2就能够减少上述层间裂纹等,所以能够缩短制造时间。其结果,能够实现半导体芯片111的制造中的成品率的改善和生产效率的提高。关于层间裂纹、表面崩边和膜剥离的减少,后文将详细说明。
另外,划片条件可适当设定,本实施方式中,划片条件设定为划片刀转速30000rpm,切割速度5mm/s。
并且,切刀划片的方式并没有特别限定。不过,在沿着切断线(本实施方式中为划片区域11)通过一次切削来切断半导体晶圆101的全断方式下,划片刀110的负载较大,表面崩边和层间裂纹的产生率变高。因此,本实施方式采用分步切断方式,使用刀刃厚度不同的2个旋转刀刃通过2次切削来切断半导体晶圆101。
详细而言,在分步切断方式中,划片刀110具有单轴旋转刀刃(未图示)和刀刃的厚度比单轴旋转刀刃薄的双轴旋转刀刃(未图示)。单轴旋转刀刃在第一次切削中切断GaN类半导体膜2。双轴旋转刀刃在第二次切削中切断硅类衬底1,将半导体晶圆101切断。其结果,如图1的(b)的第七工序所示,形成了单轴切断区域7和双轴切断区域8。根据上述结构,与一次性切断衬底的全断方式相比,分步切断方式能够减轻划片刀110的负担。其结果,与上述全断方式相比,分步切断方式能够进一步减少切断半导体晶圆101时在硅类衬底1与GaN类半导体膜2的界面附近产生的表面崩边、层间裂纹和膜剥离。另外,由于利用分步切断方式能够减轻划片刀110的负担,所以通过抑制切刀划片中的孔堵塞,能够进一步减少表面崩边20和层间裂纹21。
(表面崩边和层间裂纹)
接着,基于图5至图8,对本实施方式的半导体芯片111的制造方法与现有的半导体芯片的制造方法中划片后产生的表面崩边20和层间裂纹21的差异进行说明。表面崩边20表示半导体晶圆101表面的缺损,层间裂纹21表示硅类衬底1与GaN类半导体膜2的界面附近的龟裂。表面崩边20和层间裂纹21会导致半导体芯片111的成品率降低。
图5是表示现有的半导体芯片的制造方法中划片后的半导体晶圆101的表面状态的图。现有的半导体芯片的制造方法表示的是,不将划片区域11的电介质膜3蚀刻就对半导体晶圆101进行切刀划片的制造方法。在现有的半导体芯片的制造方法中,如图5所示,在划片后的半导体晶圆101上产生了表面崩边20和层间裂纹21。所产生的表面崩边20和层间裂纹21与密封环4接触。并且,能够观察到侵入到密封环4内即元件区域10内的层间裂纹21。
图6是表示现有的半导体芯片的制造方法中划片后的半导体晶圆101的截面状态的图,是产生了层间裂纹21的部分的截面图。如图6所示,层间裂纹21在硅类衬底1与GaN类半导体膜2的附近产生。另外,层间裂纹21还在GaN类半导体膜2下产生。因此,形成在GaN类半导体膜2上的密封环4不能防止层间裂纹21侵入元件区域10内。其结果,存在层间裂纹21侵入到元件区域10内的可能性。
对此,本实施方式的半导体芯片111的制造方法中,通过除去GaN类半导体膜2上的电介质膜3和保护膜5,能够降低硅类衬底1与GaN类半导体膜2的层间应力。其结果,起到了能够减少表面崩边20和层间裂纹21的效果。关于上述效果,基于图7和图8说明如下。
图7是表示本实施方式的半导体芯片111的制造方法中划片后的半导体晶圆101的表面状态的图。与图5相比能够看到,表面崩边20和层间裂纹21减少并且缩小。
图8是关于划片后的半导体晶圆101的表面崩边20和层间裂纹21的产生量,表示本实施方式的半导体芯片111的制造方法与现有的半导体芯片的制造方法的比较的图。在图8中,电介质膜未除去表示现有的半导体芯片的制造方法,电介质膜除去表示本实施方式的半导体芯片111的制造方法。另外,X轴表示所产生的表面崩边20和层间裂纹21从槽侧面向元件区域10内部延伸的宽度(自槽侧面的距离),Y轴表示表面崩边20和层间裂纹21产生的数量。
如图8所示,与现有的半导体元件的制造方法相比,本实施方式的半导体芯片111的制造方法中,表面崩边20和层间裂纹21的产生数量减少。另外,表面崩边20和层间裂纹21从槽侧面向元件区域10内部延伸的宽度也减小,侵入元件区域10内的表面崩边20和层间裂纹21也减少。并且,其结果,因表面崩边而引起的膜剥离的产生数量也能够得到抑制。
如图7和图8所示可知,根据本实施方式的半导体芯片111的制造方法能够减少表面崩边20和层间裂纹21。
如上所述,根据本实施方式的半导体芯片111的制造方法,能够减少表面崩边20和层间裂纹21。因而,能够改善半导体芯片111的成品率,与现有的半导体芯片的制造方法相比,能够抑制制造成本。
[实施方式2]
对本发明实施方式2的半导体芯片111的制造方法,基于图9至图12进行说明。另外,为便于说明,对于与实施方式1中说明的部件具有相同功能的部件,标注相同的标记省略其说明。
实施方式2与实施方式1的不同点如下。
在实施方式1中,在第四工序中形成槽6时,区划区域9内的电介质膜3和保护膜5被全部除去。而实施方式2中,区划区域9内的电介质膜3和保护膜5不被全部除去。即,在实施方式2中,划片区域11形成为在区划区域9的两侧部残留有电介质膜3和保护膜5的状态(参考图9的(b))。
根据上述结构,与实施方式1,即不在区划区域9的两侧部残留电介质膜3地形成划片区域11的半导体芯片111的制造方法相比,能够进一步减少划片时产生的表面崩边20、层间裂纹21和膜剥离。下面详细进行说明。
(半导体芯片111的各制造工序中的半导体晶圆101)
首先,基于图9的(a)、(b)对半导体芯片111的各制造工序中的半导体晶圆101进行说明。图9的(a)、(b)是用于说明本实施方式的半导体芯片111的制造方法的图。详细而言,图9的(a)是放大表示半导体晶圆101的一部分的俯视图。而图9的(b)是半导体芯片111的各制造工序中图9的(a)所示的半导体晶圆101的C-C线向视截面图。并且,第一工序至第三工序以及第五工序至第七工序与实施方式1相同。
在第四工序(划片区域形成工序)中,在区划区域9中通过蚀刻而除去电介质膜3和保护膜5,从而形成槽6a即划片区域11。此时,在区划区域9中,以在自密封环4起一定距离的范围内残留电介质膜3和保护膜5的状态形成槽6a。详细而言,在半导体晶圆101上,在元件区域10和区划区域9中的自密封环4起一定距离的范围内配置掩模(未图示)。之后,以除去电介质膜3和保护膜5的方式进行蚀刻(例如湿法蚀刻)。此时,配置有掩模的元件区域10和区划区域9中的上述范围的腐蚀受到抑制。其结果,元件区域10和区划区域9的上述范围被保留下来,而没有被遮蔽的区划区域9中的电介质膜3和保护膜5被除去,形成了槽6a即划片区域11。换言之,划片区域11形成为在区划区域9的两侧部残留有电介质膜3和保护膜5的状态。
根据上述结构,与实施方式1相比,能够进一步减少划片时产生的表面崩边20、层间裂纹21和膜剥离。另外,区划区域9和槽6a的宽度等可适当设定,本实施方式中区划区域9的宽度为90μm,区划区域9中自密封环4起残留的电介质膜3的宽度为15μm,槽6a的宽度为60μm。
(表面崩边和层间裂纹)
接着,基于图10至图12,对本实施方式的半导体芯片111的制造方法与实施方式1的半导体芯片111的制造方法中划片后产生的表面崩边20和层间裂纹21的差异进行说明。
图10是表示本实施方式的半导体芯片111的制造方法中划片后的半导体晶圆101的表面状态的图。在实施方式1的半导体芯片111的制造方法下,与现有的半导体芯片的制造方法相比,虽然能够减少半导体晶圆101的表面崩边20和层间裂纹21的产生数量,但表面崩边20和层间裂纹21的与密封环4的接触以及向元件区域10内的侵入则很难防止。
不过,在本实施方式中,如图10所示,表面崩边20和层间裂纹21被限制在除去了电介质膜3的槽6a的范围内。另外,对图7所示的实施方式1的半导体芯片111的制造方法中划片后的半导体晶圆101的表面状态与图10进行比较,本实施方式中表面崩边20和层间裂纹21的大小变小,半导体晶圆101的状态可谓良好。关于上述半导体晶圆101的状态变得良好的理由说明如下。
在本实施方式中,在第四工序中使形成在GaN类半导体膜2上的电介质膜3残留在区划区域9的两侧部。由此,区划区域9的两侧部的GaN类半导体膜2被电介质膜3覆盖。而位于除去了电介质膜3的槽6a处的GaN类半导体膜2则没有被电介质膜3覆盖。因此,划片区域11中产生的应力不向被电介质膜3覆盖的GaN类半导体膜2与硅类衬底1的界面传播而是在元件区域10的跟前向上(保护膜5一侧)传播。因而,如图11所示,因在划片区域11进行划片而产生的层间裂纹21在侵入元件区域10之前朝着槽6a的端部6b的方向向上前进。图11是表示实施方式2的半导体芯片111的制造方法下的划片后的半导体晶圆101的状态的截面图。
像这样,通过在形成槽6a时在区划区域9的两侧部保留电介质膜3,能够抑制层间裂纹21侵入元件区域10内的GaN类半导体膜2与硅类衬底1的界面。并且,由于区划区域9的两侧部的GaN类半导体膜2的表面被电介质膜3覆盖,所以能够抑制表面崩边20侵入元件区域10。因而,划片后的半导体晶圆101的状态变得良好。
图12是就划片后的半导体晶圆101的表面崩边20和层间裂纹21的产生量,表示本实施方式的半导体芯片111的制造方法和实施方式1的半导体芯片111的制造方法的比较的图。在图12中,电介质膜全部除去表示实施方式1的半导体芯片111的制造方法,电介质膜部分保留表示本实施方式的半导体芯片111的制造方法。另外,X轴表示所产生的表面崩边20和层间裂纹21从槽侧面向元件区域10内部延伸的宽度(自槽侧面的距离),Y轴表示表面崩边20和层间裂纹21产生的数量。
根据本实施方式的半导体芯片111的制造方法,如图12所示,与实施方式1的半导体芯片111的制造方法相比,表面崩边20和层间裂纹21的产生数量进一步减少,表面崩边20和层间裂纹21的自槽侧面向内部延伸的宽度进一步减小。另外,与密封环4接触或侵入密封环4内的表面崩边20和层间裂纹21不再存在。
如上所述,根据本实施方式的半导体芯片111的制造方法,由于能够减少表面崩边20和层间裂纹21,所以能够改善半导体芯片111的成品率,与实施方式1的半导体芯片111的制造方法相比,能够进一步提高生产效率。
[总结]
本发明第一技术方案的半导体元件(半导体芯片111)的制造方法包括:半导体元件形成工序,在形成于衬底(硅类衬底1)上的GaN类半导体膜(2)上形成电介质膜(3),由此形成多个半导体元件(元件区域10);划片区域形成工序(第四工序),将区划上述多个半导体元件的区划区域(9)上的上述电介质膜除去,由此形成槽形状的划片区域(11);和划片工序(第七工序),在上述划片区域进行划片,由此切割出上述多个半导体元件。
根据上述结构,电介质膜由划片区域区划成多个半导体元件,因此通过对划片区域进行划片能够切割出多个半导体元件(半导体芯片)。另外,通过在除去了划片区域的电介质膜后进行划片,能够减少划片时在衬底与GaN类半导体膜的界面附近产生的层间裂纹、表面崩边和膜剥离。因此,无需使用激光划片就能够减少上述层间裂纹等,所以能够抑制半导体元件的制造成本。另外,无需对GaN类半导体膜进行干法蚀刻就能够减少上述层间裂纹等,所以能够缩短半导体元件的制造时间。其结果,能够实现半导体元件的制造中的成品率的改善和生产效率的提高。
本发明第二技术方案的半导体元件(半导体芯片111)的制造方法可以是这样的,即,在上述第一技术方案中,在上述划片区域形成工序(第四工序)中,在上述区划区域(9)的两侧部保留上述电介质膜(3)。
根据上述结构,在区划区域的两侧部保留电介质膜而形成划片区域。因此,与不在区划区域的两侧部保留上述电介质膜地形成划片区域的情况相比,能够进一步减少划片时在衬底与GaN类半导体膜的界面附近产生的裂纹、表面崩边和膜剥离。
本发明第三技术方案的半导体元件(半导体芯片111)的制造方法可以是这样的,即,在上述第一或第二技术方案中,在上述划片工序(第七工序)中使用划片刀(110)。
根据上述结构,由于不使用激光划片而是使用划片刀来对衬底进行划片,因此能够抑制半导体元件的制造成本。
本发明第四技术方案的半导体元件(半导体芯片111)的制造方法可以是这样的,即,在上述第三技术方案中,上述划片刀(110)至少具有用于切断上述GaN类半导体膜(2)的单轴旋转刀刃和用于切断上述衬底(硅类衬底1)的双轴旋转刀刃,在上述划片工序(第七工序)中,利用分步切断方式进行划片。
根据上述结构,划片刀具有切断GaN类半导体膜的单轴旋转刀刃和切断上述衬底的双轴旋转刀刃,使用划片刀以分步切断方式切断半导体晶圆。因此,与一次性切断半导体晶圆的全断方式相比,能够减轻刀的负担。另外,与上述全断方式相比,能够进一步减少切断半导体晶圆时在衬底与GaN类半导体膜的界面附近产生的裂纹、表面崩边和膜剥离。
本发明第五技术方案的半导体元件(半导体芯片111)是从半导体晶圆(101)切割出的半导体元件,该半导体晶圆包括形成在衬底(硅类衬底1)上的GaN类半导体膜(2)和形成在上述GaN类半导体膜上的电介质膜(3),上述半导体元件通过在除去了上述电介质膜的划片区域(11)进行划片而从上述半导体晶圆被切割出。
根据上述结构,能够起到与第一技术方案同样的效果。
本发明并不限定于上述各实施方式,在各技术方案要求保护的范围内可以有各种变更,由不同实施方式各自公开的技术手段适当组合而得到的实施方式也包含在本发明的技术范围内。另外,通过组合各实施方式各自公开的技术手段,能够形成新的技术特征。
工业利用性
本发明的半导体元件的制造方法能够应用于制造半导体元件的领域。
附图标记说明
1硅类衬底(衬底)
2GaN类半导体膜
3电介质膜
4密封环
5保护膜
6槽
6a槽
6b端部
7单轴切断区域
8双轴切断区域
9区划区域
10元件区域(半导体元件)
11划片区域
20表面崩边
21层间裂纹
101半导体晶圆
102表面保护胶带
110划片刀
111半导体芯片(半导体元件)。
Claims (5)
1.一种半导体元件的制造方法,其特征在于,包括:
半导体元件形成工序,在形成于衬底上的GaN类半导体膜上形成电介质膜,由此形成多个半导体元件;
划片区域形成工序,将区划所述多个半导体元件的区划区域中的所述电介质膜除去,由此形成槽形状的划片区域;和
划片工序,对所述划片区域进行划片,由此切割出所述多个半导体元件。
2.如权利要求1所述的半导体元件的制造方法,其特征在于:
在所述划片区域形成工序中,在所述区划区域的两侧部保留所述电介质膜。
3.如权利要求1或2所述的半导体元件的制造方法,其特征在于:
在所述划片工序中使用划片刀。
4.如权利要求3所述的半导体元件的制造方法,其特征在于:
所述划片刀至少包括切断所述GaN类半导体膜的单轴旋转刀刃和切断所述衬底的双轴旋转刀刃,
在所述划片工序中利用分步切断方式进行划片。
5.一种从半导体晶圆切割出的半导体元件,所述半导体晶圆具有形成在衬底上的GaN类半导体膜和形成在所述GaN类半导体膜上的电介质膜,所述半导体元件的特征在于:
所述半导体元件通过在除去了所述电介质膜的划片区域进行划片而从所述半导体晶圆被切割出。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019129160A1 (zh) * | 2017-12-29 | 2019-07-04 | 上海微电子装备(集团)股份有限公司 | 芯片崩边缺陷检测方法 |
CN115050645A (zh) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | 改善晶圆表面胶膜残留的方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2017055014A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | 半導体装置の製造方法 |
US10083866B2 (en) | 2016-07-27 | 2018-09-25 | Texas Instruments Incorporated | Sawn leadless package having wettable flank leads |
JP7235379B2 (ja) * | 2019-06-19 | 2023-03-08 | 住友電工デバイス・イノベーション株式会社 | 電子デバイスの製造方法 |
US11322421B2 (en) * | 2020-07-09 | 2022-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197564A (ja) * | 2001-12-21 | 2003-07-11 | Disco Abrasive Syst Ltd | 低誘電体絶縁材料を積層した基板のダイシング方法 |
CN101136535A (zh) * | 2006-09-01 | 2008-03-05 | 松下电器产业株式会社 | 半导体激光装置及其制造方法 |
JP2008130929A (ja) * | 2006-11-22 | 2008-06-05 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US20100051987A1 (en) * | 2008-08-28 | 2010-03-04 | Kabushiki Kaisha Toshiba | Semiconductor light-emitting device and method for manufacturing same |
JP2013219271A (ja) * | 2012-04-11 | 2013-10-24 | Disco Abrasive Syst Ltd | 光デバイスウエーハの加工方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4305296C3 (de) * | 1993-02-20 | 1999-07-15 | Vishay Semiconductor Gmbh | Verfahren zum Herstellen einer strahlungsemittierenden Diode |
US6838299B2 (en) * | 2001-11-28 | 2005-01-04 | Intel Corporation | Forming defect prevention trenches in dicing streets |
JP2005012206A (ja) | 2003-05-29 | 2005-01-13 | Mitsubishi Cable Ind Ltd | 窒化物系半導体素子およびその製造方法 |
KR100604903B1 (ko) * | 2004-09-30 | 2006-07-28 | 삼성전자주식회사 | 단차피복성을 향상시킨 반도체 웨이퍼 및 그 제조방법 |
US8779445B2 (en) * | 2008-07-02 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress-alleviation layer for LED structures |
JP5573192B2 (ja) * | 2010-01-22 | 2014-08-20 | 三菱電機株式会社 | 半導体装置の製造方法 |
US8802545B2 (en) * | 2011-03-14 | 2014-08-12 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
EP2795675A4 (en) * | 2011-12-20 | 2015-11-25 | Intel Corp | HYBRID INTEGRATION OF GROUP III-V SEMICONDUCTOR COMPONENTS ON SILICON |
US8748297B2 (en) * | 2012-04-20 | 2014-06-10 | Infineon Technologies Ag | Methods of forming semiconductor devices by singulating a substrate by removing a dummy fill material |
TW201411692A (zh) * | 2012-04-23 | 2014-03-16 | Nanocrystal Asia Inc | 以壓印方式製造選擇性成長遮罩之方法 |
JP5608762B2 (ja) | 2013-01-10 | 2014-10-15 | 株式会社東芝 | 半導体発光素子 |
US9087854B1 (en) * | 2014-01-20 | 2015-07-21 | Hrl Laboratories, Llc | Thermal management for heterogeneously integrated technology |
DE112014002026T5 (de) * | 2013-04-17 | 2016-01-14 | Panasonic Intellectual Property Management Co., Ltd. | Verbundhalbleitervorrichtung, Verfahren zu ihrer Herstellung und Halbleitervorrichtung vom mit Harz versiegelten Typ |
US20150079738A1 (en) * | 2013-06-18 | 2015-03-19 | Stephen P. Barlow | Method for producing trench high electron mobility devices |
US9711463B2 (en) * | 2015-01-14 | 2017-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dicing method for power transistors |
-
2014
- 2014-10-24 JP JP2015546604A patent/JP6100396B2/ja active Active
- 2014-10-24 WO PCT/JP2014/078353 patent/WO2015068597A1/ja active Application Filing
- 2014-10-24 US US15/032,907 patent/US9721838B2/en active Active
- 2014-10-24 CN CN201480061046.2A patent/CN105706215B/zh active Active
- 2014-11-03 TW TW103138097A patent/TWI647753B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197564A (ja) * | 2001-12-21 | 2003-07-11 | Disco Abrasive Syst Ltd | 低誘電体絶縁材料を積層した基板のダイシング方法 |
CN101136535A (zh) * | 2006-09-01 | 2008-03-05 | 松下电器产业株式会社 | 半导体激光装置及其制造方法 |
JP2008130929A (ja) * | 2006-11-22 | 2008-06-05 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US20100051987A1 (en) * | 2008-08-28 | 2010-03-04 | Kabushiki Kaisha Toshiba | Semiconductor light-emitting device and method for manufacturing same |
JP2013219271A (ja) * | 2012-04-11 | 2013-10-24 | Disco Abrasive Syst Ltd | 光デバイスウエーハの加工方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019129160A1 (zh) * | 2017-12-29 | 2019-07-04 | 上海微电子装备(集团)股份有限公司 | 芯片崩边缺陷检测方法 |
CN115050645A (zh) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | 改善晶圆表面胶膜残留的方法 |
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