CN102934225A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN102934225A CN102934225A CN2012800015006A CN201280001500A CN102934225A CN 102934225 A CN102934225 A CN 102934225A CN 2012800015006 A CN2012800015006 A CN 2012800015006A CN 201280001500 A CN201280001500 A CN 201280001500A CN 102934225 A CN102934225 A CN 102934225A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229920005989 resin Polymers 0.000 claims abstract description 111
- 239000011347 resin Substances 0.000 claims abstract description 111
- 239000000463 material Substances 0.000 claims abstract description 76
- 238000007789 sealing Methods 0.000 claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 description 21
- 241000446313 Lamella Species 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004382 potting Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/45001—Core members of the connector
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- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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Abstract
本发明提供一种半导体装置,其具有形成有切口部(5a)的引脚(5)、芯片焊盘部(11)、芯片焊盘部(11)所保持的功率元件(1)、对包括功率元件(1)在内的芯片焊盘部(11)及引脚(5)的内侧端部进行密封且由树脂材料构成的外装体(6)。切口部(5a)被配置于引脚(5)中的包括与外装体(6)的边界部分在内的区域,并且被填充有树脂材料。
Description
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
期望控制设备(例如逆变器控制设备)小型化。响应于该期望,被组装到控制设备内部的半导体装置(例如功率组件)也期盼实现小型化及轻质化。
半导体装置例如是将功率元件和控制该功率元件的控制元件分别装载到引脚框(lead frame),对这些引脚框进行电接合,然后密封到由树脂材料构成的外装体(package)的内部而形成的。具有功率元件的半导体装置在变成高电位的外部端子彼此之间需要确保绝缘距离。因而,例如专利文献1中记载了一种在外部端子彼此之间的区域设置凹状的爬电结构(凹状结构)、由此利用该凹状的爬电结构(creepage structure)而确保了爬电距离的半导体装置。
图11(a)~图11(c)表示设置了一般的爬电结构的现有的半导体装置。现有的设置了爬电结构的半导体装置由引脚框103、被保持在芯片焊盘(ダイパツド:die pad)109A之上的功率元件101、被保持在芯片焊盘109B之上的控制元件111以及由树脂材料构成的外装体106而构成。引脚框103具有多个引脚(外部端子)105及多个芯片焊盘109A、109B。外装体106包括功率元件101及控制元件111,对芯片焊盘109A、109B及各引脚105在芯片焊盘109A、109B侧的端部进行密封。功率元件101和引脚105在芯片焊盘109A侧的端部通过金属部件121而被电连接在一起。再有,控制元件111、功率元件101、及引脚105在芯片焊盘109B侧的端部通过金(Au)导线122而被电连接在一起。
在此,如将图11(a)的区域C放大后的图11(b)所示,现有的半导体装置在外装体106内的多个引脚105彼此之间的区域中分别形成凹状结构106a。
如此,现有的半导体装置利用各凹状结构106a来确保互相相邻的引脚105彼此之间的爬电距离,通过缩短引脚105彼此的间隔来实现半导体装置的小型化。
在先技术文献
专利文献
专利文献1:JP特开2003-124437号公报
发明内容
发明所要解决的技术课题
现有的半导体装置为了确保爬电距离而需要在外装体设置凹状结构。然而,该凹状结构对于半导体装置的小型化而言成为用于确保爬电距离的制约。再有,为了形成具有该凹状结构的这种复杂外形的外装体,存在密封用模具的结构变得复杂的问题。
若考虑到半导体装置的小型化的发展以及电流量及电压增大,则这些问题可能还会成为更大的问题。
本发明的目的在于,实现一种无需在外装体设置凹状结构就能确保爬电距离(creepage distance)的半导体装置。
用于解决问题的技术方案
为了达成上述目的,本发明涉及的半导体装置具备形成有切口部的引脚、芯片焊盘部、由芯片焊盘部保持的第1元件以及对包括第1元件在内的芯片焊盘部及引脚的内侧端部进行密封且由树脂材料构成的外装体,切口部被配置于引脚上的包括与外装体的边界部分在内的区域中,并且被填充了树脂材料。
再有,在本发明涉及的半导体装置的制造方法中,准备保持第1元件的芯片焊盘部和具有切口部的引脚;通过将引脚的切口部配置到模具的夹紧位置并向模具注入密封用的树脂材料,从而利用树脂材料对包括第1元件在内的芯片焊盘部及引脚的内侧端部进行密封。
发明效果
根据本发明涉及的半导体装置及其制造方法,可实现无需在外装体形成凹状结构就能确保爬电距离的半导体装置。
附图说明
图1(a)是表示本发明一实施方式涉及的半导体装置的俯视图。图1(b)是将图1(a)中的区域A放大后的俯视图。图1(c)是区域A的详细的俯视图。
图2(a)是将其他方式的一工序涉及的区域A放大后的俯视图。图2(b)是将其他方式的一工序涉及的区域A放大后的俯视图。图2(c)是将其他方式涉及的半导体装置的区域A放大后的俯视图。
图3(a)是本发明表示一实施方式涉及的半导体装置的仰视图。图3(b)是将图3(a)中的区域B放大后的仰视图。
图4(a)是表示本发明一实施方式涉及的半导体装置的内部结构的俯视图。图4(b)及图4(c)是表示一实施方式涉及的切口部的形状的变形例的局部俯视图。
图5是图4的V-V线处的剖视图。
图6是表示本发明一实施方式涉及的半导体装置的制造方法的一工序的示意性剖视图。
图7是表示本发明一实施方式涉及的半导体装置的制造方法的一工序的示意性剖视图。
图8是表示本发明一实施方式涉及的半导体装置的制造方法的一工序的示意性剖视图。
图9是表示本发明一实施方式涉及的半导体装置的制造方法的一工序的示意性剖视图。
图10是表示本发明一实施方式涉及的半导体装置的制造方法的一工序的示意性剖视图。
图11(a)是表示现有的半导体装置的俯视图。图11(b)是将图11(a)中的区域C放大后的俯视图。图11(c)是表示现有的半导体装置的内部结构的示意性俯视图。
具体实施方式
参照附图对本发明一实施方式进行说明。
其中,本发明只要基于本说明书所记载的基本特征,并不限定于以下记载的内容。
图1(a)是表示本发明一实施方式涉及的半导体装置的俯视图。图1
(b)是将图1(a)中的区域A放大后的俯视图。图1(c)是区域A的详细的俯视图。图3(a)是表示本发明一实施方式涉及的半导体装置的仰视图。图3(b)是将图3(a)中的区域B放大后的仰视图。图4(a)是表示本发明一实施方式涉及的半导体装置的内部结构的俯视图。图4(b)及图4(c)是表示一实施方式涉及的切口部的形状的变形例的局部俯视图。图5是图4的V-V线处的剖视图。
如图1及图3~图5所示,本实施方式涉及的半导体装置15具备功率元件1、散热板2、引脚框3、控制元件4和外装体6。引脚框3具有第1芯片焊盘部9、第2芯片焊盘部11及成为外部端子的多根引脚5。外装体6将功率元件1、控制元件4及多个引脚5的内侧端部一体地密封。外装体6由密封用的树脂材料构成。功率元件1是第1元件的一例。控制元件4是第2元件的一例。
作为本实施方式的半导体装置15的一例,例如有功率组件(功率半导体)。本实施方式的半导体装置15例如组装到控制设备来使用。
引脚框3例如由铜(Cu)等导电性优越的材料构成。引脚框3中,从外装体6的侧面突出的引脚5构成外部端子并作为本半导体装置15的安装端子而与逆变器控制设备等的电路连接。
功率元件1例如通过钎料(solder material)8或银(Ag)膏剂材料固定粘接并保持在引脚框3的第1芯片焊盘部9的上表面9a上。功率元件1的接合焊盘(未图示)和引脚框3的多根引脚5藉由金属部件21而相互地电连接。功率元件1例如可以采用IGBT(绝缘栅极型双极性晶体管)或MOSFET(金属氧化膜型场效应晶体管)。金属部件21例如可以采用铝(Al)导线、金(Au)或铜(Cu)等构成的金属导线、铝(Al)带或铜(Cu)夹子。铝带或铜夹子和铝导线相比,横截面积大且布线的电阻值,因此可以降低金属部件21内的功率损耗。在本实施方式中,作为功率元件1的一例采用内置有二极管的横型功率MOSFET、作为金属部件21的一例采用铝导线进行说明。
如图5所示,在引脚框3的第1芯片焊盘部9的下表面9b,隔着绝缘薄片10而固定粘接有散热板2。散热板2例如可以采用铜(Cu)或铝(Al)等热传导性优越的金属。
绝缘薄片10由热传导性绝缘材料构成,例如具有利用粘接层来夹持绝缘层的3层结构。绝缘薄片10是为了将功率元件1产生的热量有效地传导至散热板2而设置的。
控制元件4例如内置驱动电路及过电流防止电路。例如利用银(Ag)膏剂材料16,将控制元件4固定粘接并保持在引脚框3中的第2芯片焊盘部11的上表面11a上。控制元件4的接合焊盘(未图示)和引脚框3的多根引脚5藉由金(Au)导线22而相互地电连接。进而,功率元件1的接合焊盘(未图示)和控制元件4的接合焊盘(未图示)藉由金导线22而电连接在一起。藉由该金导线22,功率元件1能够实现基于控制元件4的控制。
外装体6覆盖功率元件1、第1芯片焊盘部9、控制元件4、第2芯片焊盘部11及各引脚5的内侧端部、以及散热板2的上表面及侧面2c。因此,散热板2的下表面2b自外装体6的下表面6b露出。
如图5所示,散热板2的下表面2b自外装体6的下表面6b露出。因而,可以有效地将功率元件1产生的热量从散热板2的下表面2b传导至外部。再有,由于散热板2的侧面2c被外装体6覆盖,故散热板2和引脚框3的接合牢固。
如图4所示,本实施方式涉及的半导体装置的特征在于:在从外装体6的侧面突出且成为外部端子的引脚5的侧面预先形成切口部(凹状部)5a。因此,在本实施方式涉及的半导体装置15中,如图1(b)及图3(b)所示,在形成于引脚5侧面的切口部5a,形成填充构成外装体6的树脂材料而成的树脂填充部6c。
即,在本实施方式涉及的半导体装置15中,对于预先形成在引脚5上的切口部5a而言,利用密封外装体6的工序同时填充树脂材料,以形成树脂填充部6c。因而,树脂填充部6c成为与外装体6之间不存在界面的一体结构。
在此,设置切口部5a的引脚5成为与控制元件4直接连接的引脚。这是因为:一般而言,控制元件4所需的输入输出信号要比功率元件1所需的输入输出信号还多。因而,为了实现半导体装置自身的小型化,如图1(a)所示需要缩小与控制元件4直接连接的引脚5彼此的间隔。另外,在与功率元件1直接连接的引脚5中,在设计上需要提高相邻的引脚间耐压等的情况下,只要针对与功率元件1连接的引脚5而预先设置切口部5a并形成树脂填充部6c即可。
在此,利用将图1(b)的主要部分放大后的图1(c),对本实施方式涉及的半导体装置15的引脚5更具体地进行说明。在本实施方式涉及的半导体装置15中,如图1(c)所示,按照在多根引脚5的各侧面分别残留堤坝(dam bar)5b的方式,在切断堤坝5b的同时,除去树脂填充部6c的毛边(flash)。如图1(c)所示,本实施方式涉及的半导体装置15的树脂填充部6c及切口部5a被设置在并未与该堤坝5b相接的位置处且比堤坝5b更靠近内侧(外装体6侧)。这是因为在堤坝5b的切断时堤坝切断用刀刃14不会切断树脂填充部6c的缘故。
再有,作为图1(b)、图1(c)的其他方式。也能采取图2(c)的结构。图2(c)由图2(a)及图2(b)的工序构成。
图2(a)是表示在其他方式中在切口部5a彼此之间填充了树脂的状态的图。图2(b)是在其他方式中利用堤坝切断用刀刃14切断被填充在切口部5a彼此之间的树脂而形成了沟槽6d的图。
在上述的图1(c)中,虽然堤坝切断用刀刃14不会切断树脂填充部6c,但在其他方式的图2(a)~图2(c)中,堤坝切断用刀刃14切断其他方式的树脂填充部6c来形成沟槽6d。如此,通过在其他方式的树脂填充部6c形成与引脚5的突出方向平行的沟槽6d,从而可以构成在引脚5间形成了沟槽6d的树脂填充部6c。如图2(a)~图2(c)所示,通过形成沟槽6d,从而可以延长爬电距离。
在此,在想要进一步延长爬电距离的情况下,如图2(c)所示希望使堤坝切断用刀刃14嵌入到外装体6,以在外装体6设置凹陷。此时,由于外装体6的高度(附图的纸面垂直方向的宽度)和引脚5相比足够大,故外装体6不会被分开。这样,通过利用堤坝切断用刀刃14在外装体6设置凹陷,从而可以在外装体6内配置形成于树脂填充部6c的沟槽6d的一部分。
外装体6例如由环氧系树脂等热固化型树脂材料构成。构成外装体6及树脂填充部6c的树脂材料希望采用例如在环氧系树脂中混合掺杂有粉碎填料或球形填料而得到的材料。作为球形填料,例如通过采用氧化铝(alumina),从而可以提高树脂填充部6c的热传导性。
在本实施方式的半导体装置15中,由于在引脚5上设置切口部5a,故包括树脂填充部6c的引脚5需要具备规定的强度。因而,在本实施方式的半导体装置15中,在图1(b)中将一个引脚5中的树脂填充部6c彼此的间隔L2设为L2≥0.4mm。该树脂填充部6c彼此的间隔L2虽然根据引脚5的材质、宽度及长度而不同,但希望至少L2≥0.4mm。在此,间隔L2和引脚5中的设置了切口部5a的部分的宽度大致相等。通过设为L2≥0.4mm,从而引脚5可以具备规定的强度,并且可以抑制设置了切口部5a的引脚5的高电阻化。在此,一般而言引脚5的宽度L1为:L1=0.5mm以上且2.0mm以下。
再有,在本实施方式的半导体装置15中,为了尽可能地延长相邻的引脚5彼此的爬电距离,相对于引脚5的突出长度L3=2.0mm以上且5.0mm以下而言,将树脂填充部6c的长度L4最大设为L4=2.0mm。
另外,如果引脚5具备足够的强度,则如图1(b)所示,树脂填充部6c可以设置在引脚5的两侧面。如果在相邻的引脚5的至少一方设置树脂填充部6c,则可以延长引脚5彼此之间的爬电距离。然而,在想尽可能地延长爬电距离的情况下,希望在一个引脚5的两侧面设置树脂填充部6c。
此外,配置于外装体6内的切口部5a的长度L5(参照图4(a))只要比混合掺杂于树脂材料中的填料的直径还大即可。在本实施方式中,作为一例设定为L5≥20μm。
再有,如图4(b)所示也可以使配置于外装体6内的切口部5a的壁面形状向外装体6的内侧倾斜而成为倾斜状。还有,如图4(c)所示,也可以设为阶梯状。通过将壁面形状设为图4(b)或图4(c)所示的形状,从而易于填充用于形成树脂填充部6c的树脂材料。
如上所述,本实施方式の半导体装置15在成为外部端子的引脚5中,在与外装体6之间的边界部分预先形成切口部5a。而且,在该切口部5a设置有被填充了构成外装体6的树脂材料的树脂填充部6c。由此,为了提高半导体装置中的电绝缘性,不需要现有的结构中所需的外装体外周部的凹状结构。因而,也可以使构成半导体装置的外装体的外形尺寸小型化。
进而,本实施方式涉及的半导体装置15由于外装体6的形状简单,故可以简化用于制作外装体6的模具的结构。
另外,在本实施方式中,被填充到树脂填充部6c的树脂材料是在注入构成外装体6的树脂材料时而被填充的。因此,构成外装体6的树脂材料和构成树脂填充部6c的树脂材料在组成上是相同的。
然而,作为本实施方式的半导体装置15的一个变形例,也能在注入构成外装体6的树脂材料之前预先将树脂材料填充到各切口部5a。这样也能向各切口部5a填充具有与构成外装体6的树脂材料不同的组成的树脂材料、例如低介电常数的绝缘性树脂材料、或散热性高的绝缘性树脂材料。通过将低介电常数的绝缘性树脂材料填充到切口部5a,从而可以提高树脂填充部6c的绝缘性。再有,通过将散热性高的绝缘性树脂材料填充到切口部5a,从而可以提高树脂填充部6c的散热性。
(制造方法)
以下,参照图6~图10对本实施方式涉及的半导体装置的制造方法的一例进行说明。
首先,如图6所示将在上表面临时粘接了绝缘薄片10的散热板2以绝缘薄片10为上的方式载置到下模具12的底面上。接着,分别固定粘接功率元件1及控制元件4,并将通过金属部件及金导线而连接的引脚框3按照第1芯片焊盘部9的下表面9b与绝缘薄片10相接的方式载置到下模具12上。此时,如图4所示,在与控制元件4直接连接的引脚5上预先形成切口部5a。在形成切口部5a时,例如可以采用机械的冲压法、或化学的蚀刻法。另外图6~图10是与图5同等的剖视图,省略金属部件21及金导线22的图示。
如图6所示,在与下模具12对应的上模具13形成模具插入销13A。
在此,在流入树脂材料并填充了树脂材料时,在本实施方式中按照该树脂材料不会从切口部5a溢出的方式将成为外部端子的引脚5的侧面侧的切口部5a的端部配置在上模具13与下模具12的夹紧位置。即,切口部5a配置于被上模具13与下模具12围起来的空间内。通过这样配置,从而在树脂材料的填充时该树脂材料不会从切口部5a溢出,可以将树脂填充部6c形成在所期望的位置上。
接下来,如图7所示,使上模具13向下模具12下降,利用上模具13与下模具12从上下方向夹紧引脚框3。在此,设置于上模具13的多个模具插入销13A被配置在引脚框3中的第1芯片焊盘部9的上方。因此,若使上模具13下降,利用上模具13与下模具12从上下方向夹紧引脚框3,则通过各模具插入销13A,将被载置于散热板2之上的引脚框3的第1芯片焊盘部9向下方被按压。其结果是,粘贴在引脚框3的第1芯片焊盘部9的下表面9b上的散热板2被压向下模具12。
由此,如图7所示多个模具插入销13A中的至少一个模具插入销13A在俯视的情况下配置于功率元件1与控制元件4之间。此时,设置于功率元件1与控制元件4之间的模具插入销13A具有从与引脚框3的第1芯片焊盘部9的接触面向上方扩展的圆锥台形状(truncated cone)。其中,模具插入销13A的形状也可以是棱锥台形状(truncated pyramid)。
接下来,作为树脂注入工序,利用传递模塑法,例如将环氧树脂构成的密封用树脂材料注入到上模具13与下模具12之间。通过注入树脂材料,从而如图8所示,形成按照包括引脚框3的模具的内侧部分在内并覆盖功率元件1、控制元件4、及散热板2的侧面的方式进行密封的外装体6。此时,散热板2被模具插入销13A向下模具12按压,因此被注入的树脂材料不会进入散热板2的下表面2b侧。在该树脂注入工序中,向在从外装体6侧面突出的规定的引脚5上预先形成的切口部5a填充所注入的树脂材料,从而组成与外装体6相同的树脂填充部6c和外装体6一体地形成。
另外,在本实施方式的制造方法中,在树脂密封后的散热板2的下表面2b并不存在所注入的树脂材料。结果是,自功率元件1经由散热板2而向外装体6外侧的散热有效地进行。
此外,通过利用各模具插入销13A来按压第1芯片焊盘部9的上表面9a,从而各模具插入销13A向第1芯片焊盘部9的上表面9a突入少许。因而,树脂材料不会流入到各模具插入销13A和第1芯片焊盘部9的接触面。
再有,在本实施方式的制造方法中,在树脂密封工序中由于从下模具12及上模具13的传递的热量而使配置在引脚框3的第1芯片焊盘部9和散热板2之间的绝缘薄片10的粘接层(未图示)熔融,并进一步固化。因而,绝缘薄片10和引脚框3的第1芯片焊盘部9的下表面9b及散热板2的粘接变得更加牢固。
接下来,如图9所示使树脂材料固化而进行了树脂密封之后,若使上模具13上升,则在外装体6中的各模具插入销13A被插入的位置处,分别形成从引脚框3的第1芯片焊盘部9向上方扩展的开口部6A。由于各模具插入销13A为圆锥台形状,故各开口部6A也为圆锥台形状,因此各模具插入销13A容易自外装体6拔出。此时。各开口部6A的底面并未附着密封用树脂材料,引脚框3的第1芯片焊盘部9露出。各开口部6A可以根据用途或目的而容易地填充树脂材料,也能填充树脂材料来堵塞各开口部6A。
这样,可以制造图10所示的半导体装置15。
如上所述,在本实施方式中,在从外装体6侧面的突出的外部端子、即引脚5上预先设置切口部5a,在该切口部5a中填充与密封用树脂材料相同的树脂材料来形成树脂填充部6c。如此,通过在引脚5形成树脂填充部6c,从而可以提高接近配置的引脚5彼此的电绝缘性,并且可以使外装体6的外形尺寸小型化。进而,可以简化制作外装体6的模具的结构。
工业实用性
本发明涉及的半导体装置及其制造方法可以适用于IGBT组件或智能功率组件(IPM)等的半导体装置。
符号说明
1 功率元件
2 散热板
2b 下表面
2c 侧面
3 引脚框
4 控制元件
5 引脚(lead)
5a 切口部
5b 堤坝
6 外装体
6a 上表面
6b 下表面
6c 树脂填充部
6d 沟槽
6A 开口部
8 钎料
9 第1芯片焊盘部
9a 上表面
9b 下表面
10 绝缘薄片
11 第2芯片焊盘部
11a 上表面
12 下模具
13 上模具
13A 模具插入销
14 堤坝切断用刀刃
21 金属部件
22 金导线
权利要求书(按照条约第19条的修改)
1.(修改后)一种半导体装置,其具备:
形成有切口部的引脚;
芯片焊盘部;
由所述芯片焊盘部保持的第1元件;以及
对包括所述第1元件在内的芯片焊盘部及所述引脚的内侧端部进行密封且由树脂材料构成的外装体,
所述切口部被配置于所述引脚中的包括与所述外装体的边界部分在内的区域,并且被填充了树脂材料,
被填充于所述切口部的树脂材料和构成所述外装体的树脂材料一体地形成。
2.根据权利要求1所述的半导体装置,其中,
被填充在所述切口部中的树脂材料和构成所述外装体的树脂材料在组成上是相同的。
3.根据权利要求1或2所述的半导体装置,其中,
所述切口部形成于相邻的引脚彼此至少一方上。
4.根据权利要求1~3中任一项所述的半导体装置,其中,
所述切口部形成在一个引脚的两侧面上。
5.(删除)
6.根据权利要求1~5中任一项所述的半导体装置,其中,
所述第1元件是功率元件。
7.根据权利要求6所述的半导体装置,其中,
该半导体装置还具备控制元件,该控制元件是对所述功率元件进行控制的第2元件,
形成有所述切口部的引脚和所述控制元件连接。
8.根据权利要求1~7中任一项所述的半导体装置,其中,
在所述引脚上,所述切口部形成得比形成于所述引脚上的堤坝还靠内侧。
9.根据权利要求1~7中任一项所述的半导体装置,其中,
在被填充于所述切口部间的树脂材料中形成了与所述引脚的突出方向平行的沟槽。
10.根据权利要求9所述的半导体装置,其中,
所述沟槽的一部分被配置在所述外装体的内部。
11.根据权利要求1~10中任一项所述的半导体装置,其中,
在一个引脚上,由被填充于所述切口部的树脂材料组成的树脂填充部彼此的间隔为0.4mm以上。
12.根据权利要求1~11中任一项所述的半导体装置,其中,
所述切口部的一部分被配置在所述外装体内。
13.根据权利要求12所述的半导体装置,其中,
被配置在所述外装体内的所述切口部的长度要比混合掺杂在所述树脂材料中的填料的直径大。
14.根据权利要求1~13中任一项所述的半导体装置,其中,
所述切口部内侧的形状为倾斜状或阶梯状。
15.(修改后)一种半导体装置的制造方法,其中,
准备保持第1元件的芯片焊盘部和具有切口部的引脚;
通过将所述引脚的切口部配置到模具的夹紧位置,并向所述模具注入密封用的树脂材料,从而利用所述树脂材料对包括所述第1元件在内的芯片焊盘部及所述引脚的内侧端部一体地进行密封。
16.(修改后)根据权利要求15所述的半导体装置的制造方法,其中,
通过将所述引脚的切口部配置到所述模具的夹紧位置,并将所述树脂材料注入到所述模具内,从而在形成于所述引脚的切口部中填充所述树脂材料。
Claims (16)
1.一种半导体装置,其具备:
形成有切口部的引脚;
芯片焊盘部;
由所述芯片焊盘部保持的第1元件;以及
对包括所述第1元件在内的芯片焊盘部及所述引脚的内侧端部进行密封且由树脂材料构成的外装体,
所述切口部被配置于所述引脚中的包括与所述外装体的边界部分在内的区域,并且被填充了树脂材料。
2.根据权利要求1所述的半导体装置,其中,
被填充在所述切口部中的树脂材料和构成所述外装体的树脂材料在组成上是相同的。
3.根据权利要求1或2所述的半导体装置,其中,
所述切口部形成于相邻的引脚彼此至少一方上。
4.根据权利要求1~3中任一项所述的半导体装置,其中,
所述切口部形成在一个引脚的两侧面上。
5.根据权利要求1~4中任一项所述的半导体装置,其中,
被填充于所述切口部的树脂材料和构成所述外装体的树脂材料一体地形成。
6.根据权利要求1~5中任一项所述的半导体装置,其中,
所述第1元件是功率元件。
7.根据权利要求6所述的半导体装置,其中,
该半导体装置还具备控制元件,该控制元件是对所述功率元件进行控制的第2元件,
形成有所述切口部的引脚和所述控制元件连接。
8.根据权利要求1~7中任一项所述的半导体装置,其中,
在所述引脚上,所述切口部形成得比形成于所述引脚上的堤坝还靠内侧。
9.根据权利要求1~7中任一项所述的半导体装置,其中,
在被填充于所述切口部间的树脂材料中形成了与所述引脚的突出方向平行的沟槽。
10.根据权利要求9所述的半导体装置,其中,
所述沟槽的一部分被配置在所述外装体的内部。
11.根据权利要求1~10中任一项所述的半导体装置,其中,
在一个引脚上,由被填充于所述切口部的树脂材料组成的树脂填充部彼此的间隔为0.4mm以上。
12.根据权利要求1~11中任一项所述的半导体装置,其中,
所述切口部的一部分被配置在所述外装体内。
13.根据权利要求12所述的半导体装置,其中,
被配置在所述外装体内的所述切口部的长度要比混合掺杂在所述树脂材料中的填料的直径大。
14.根据权利要求1~13中任一项所述的半导体装置,其中,
所述切口部内侧的形状为倾斜状或阶梯状。
15.一种半导体装置的制造方法,其中,
准备保持第1元件的芯片焊盘部和具有切口部的引脚;
通过将所述引脚的切口部配置到模具的夹紧位置,并向所述模具注入密封用的树脂材料,从而利用所述树脂材料对包括所述第1元件在内的芯片焊盘部及所述引脚的内侧端部进行密封。
16.根据权利要求15所述的半导体装置的制造方法,其中,
通过将所述引脚的切口部配置到所述模具的夹紧位置,并将所述树脂材料注入到所述模具内,
从而在形成于所述引脚的切口部中填充所述树脂材料。
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CN104009010A (zh) * | 2013-02-27 | 2014-08-27 | 株式会社电装 | 半导体器件 |
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CN106233457B (zh) * | 2014-05-15 | 2019-09-27 | 英特尔公司 | 用于集成电路组件的模塑复合壳体 |
CN108269771A (zh) * | 2017-01-03 | 2018-07-10 | 英飞凌科技股份有限公司 | 包括限定出凹口的包封材料的半导体装置 |
CN108269771B (zh) * | 2017-01-03 | 2021-11-23 | 英飞凌科技股份有限公司 | 包括限定出凹口的包封材料的半导体装置 |
WO2021103354A1 (zh) * | 2019-11-25 | 2021-06-03 | 武汉华星光电半导体显示技术有限公司 | 一种显示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN102934225B (zh) | 2016-05-04 |
EP2677539A4 (en) | 2016-03-30 |
JPWO2012111254A1 (ja) | 2014-07-03 |
US8772923B2 (en) | 2014-07-08 |
JP5873998B2 (ja) | 2016-03-01 |
US20120326289A1 (en) | 2012-12-27 |
EP2677539B1 (en) | 2017-07-05 |
WO2012111254A1 (ja) | 2012-08-23 |
EP2677539A1 (en) | 2013-12-25 |
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