JP6275292B1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6275292B1 JP6275292B1 JP2016575686A JP2016575686A JP6275292B1 JP 6275292 B1 JP6275292 B1 JP 6275292B1 JP 2016575686 A JP2016575686 A JP 2016575686A JP 2016575686 A JP2016575686 A JP 2016575686A JP 6275292 B1 JP6275292 B1 JP 6275292B1
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- wiring board
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- power supply
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Abstract
Description
以下、本発明の一実施形態による半導体装置について、図面を参照して説明する。
図1に示すように、本実施形態の半導体装置10は、装置本体20、並びに、装置本体20から突出する電源端子(リード)31,32,33、出力端子(リード)34,35,36及びグランド端子(リード)37,38,39をそれぞれ有する回路ユニット41,42,43を備えている。
装置単位21,22,23は、互いに間隔を空けて配された複数の配線板(電源配線板24、グランド配線板25,26,27、出力配線板28,29,30、ゲート配線板81〜86)と、一部の配線板の第一主面に配されて、配線板に電気接続される半導体素子(半導体素子91〜96)とを有する。
装置本体20は、装置単位21,22,23を被覆する封止樹脂50を有する。
第二回路ユニット42は、第二装置単位22と、第二装置単位22から突出する第二電源端子32、第二出力端子35及び第二グランド端子38と、を有する。
第三回路ユニット43は、第三装置単位23と、第三装置単位23から突出する第三電源端子33、第三出力端子36及び第三グランド端子39と、を有する。
第一回路ユニット41と、第二回路ユニット42と、第三回路ユニット43とは、平面視した場合、略等しい形状をなしている。
第二装置単位22は、電源配線板24と、第二グランド配線板26と、第二出力配線板29と、第二半導体素子92と、第五半導体素子95と、を有する。
第三装置単位23は、電源配線板24と、第三グランド配線板27と、第三出力配線板30と、第三半導体素子93と、第六半導体素子96と、を有する。
電源端子31,32,33、出力端子34,35,36及びグランド端子37,38,39は、封止樹脂50から突出している。
ゲート端子61〜66は、封止樹脂50から突出している。
電源配線板24と、グランド配線板25,26,27と、出力配線板28,29,30とは、互いに間隔を空けて配置されている。
電源配線板24は、3つの回路ユニット41,42,43の全体にわたって延在している。
3つの電源端子31,32,33は、電源配線板24の各幅広部24Bに接続され、各幅広部24Bから突出している。すなわち、3つの電源端子31,32,33と電源配線板24とが一体に形成されている。
グランド端子37,38,39は、グランド配線板25,26,27に接続され、グランド配線板25,26,27から突出している。すなわち、グランド端子37,38,39とグランド配線板25,26,27とが一体に形成されている。
出力配線板28,29,30は、平面視した場合、前記の直線方向に直交する方向に連続する幅狭部28A,29A,30Aと幅広部28B,29B,30Bとを有する。幅狭部28A,29A,30Aは、前記の直線方向において幅が狭い。幅広部28B,29B,30Bは、前記の直線方向において、幅狭部28A,29A,30Aよりも幅が広い。幅広部28B,29B,30Bは、前記の直線方向において、幅狭部28A,29A,30Aの一方側(図1において下側)に突出している。
出力端子34,35,36は、出力配線板28,29,30の幅広部28B,29B,30Bに接続され、幅広部28B,29B,30Bから突出している。すなわち、出力端子34,35,36と出力配線板28,29,30とが一体に形成されている。
電源配線板24の幅広部24Bは、出力配線板28,29,30の幅狭部28A,29A,30Aに向かい合うように配置されている。
ゲート端子61〜66は、ゲート配線板81〜86に接続され、ゲート配線板81〜86から突出している。
第二回路ユニット42において、第三ゲート配線板83は、第二出力配線板29の幅狭部29Aに隣接するように配置されている。また、第四ゲート配線板84は、第二出力配線板29と第三出力配線板30の間に配置されている。
第三回路ユニット43において、第五ゲート配線板85は、第三出力配線板30の幅狭部30Aに隣接するように配置されている。また、第六ゲート配線板86は、第三出力配線板30における、第三出力端子36及び第三グランド端子39の配列方向の面に沿って配置されている。
第二回路ユニット42において、第二電源端子32、電源配線板24、第二半導体素子92、第二接続子102、第二出力配線板29及び第二出力端子35が、第一電流経路73を形成している。
第三回路ユニット43において、第三電源端子33、電源配線板24、第三半導体素子93、第三接続子103、第三出力配線板30及び第三出力端子36が第一電流経路75を形成している。
第二回路ユニット42において、第二出力端子35、第二出力配線板29、第五半導体素子95、第五接続子108、第二グランド配線板26及び第二グランド端子38が、第二電流経路74を形成している。
第三回路ユニット43において、第三出力端子36、第三出力配線板30、第六半導体素子96、第六接続子109、第三グランド配線板27及び第三グランド端子39が、第二電流経路76を形成している。
一方、3つの出力配線板28,29,30の幅広部28B,29B,30Bのそれぞれに配された半導体素子94,95,96は前記の直線方向に直交する方向に間隔を空けて配列されて第二素子群を構成している。
また、第二素子群を構成する第六半導体素子96の中心が、前記の直線方向に直交する方向において第一素子群を構成する第二半導体素子92と第三半導体素子93の中心間に位置している。
半導体素子91〜96がスイッチング素子の場合、本実施形態の半導体装置10は、モータ(例えば、三相モータ)の動作制御に使用することができる。
電源端子31,32,33に直流電流が流れ、スイッチング素子である半導体素子91,92,93のゲート電極に対してゲート信号が断続的に印加されると、第一電流経路71,73,75においては、電源端子31,32,33から出力端子34,35,36に向けて、断続的に直流電流が流れる。一方、スイッチング素子である半導体素子94,95,96のゲート電極に対してゲート信号が断続的に印加されると、第二電流経路72,74,76においては、出力端子34,35,36とグランド端子37,38,39との間で交流電流が流れる。
図5において、コンデンサ121〜123は、電源配線板24と出力配線板28〜30との間において半導体素子91〜93と並列に接続されている。また、コンデンサ124〜126は、出力配線板28,29,30とグランド配線板25,26,27との間において半導体素子94〜96と並列に接続されている。
また、貫通孔51,51は、封止樹脂50における前記の直線方向に直交する方向の両端に形成されている。このため、図6に例示するように、電源配線板24、出力配線板28,29,30、グランド配線板25,26,27の第二主面(装置本体20の下面)と放熱部材150との面接触を確保できる。これにより、半導体素子91〜96で発生した熱を、これらの配線板の第二主面から放熱部材150に、さらに効率よく逃がすことができる。
以下、本発明の一実施形態によるリードフレームについて、図面を参照して説明する。
図7に示すように、本実施形態のリードフレーム200は、複数の配線板(電源配線板24、グランド配線板25,26,27、出力配線板28,29,30、ゲート配線板81〜86)と、複数の端子(電源端子(リード)31,32,33、出力端子(リード)34,35,36、グランド端子(リード)37,38,39、ゲート端子61〜66)とが一体に形成され、複数の端子が連結部(タイバー201,202と枠体部203)によって連結されている。
本実施形態では、図7に示すリードフレーム200において、図1に示す半導体装置10と同一の構成要素には、同一の符号を付して、それらの構成要素に関する説明を省略する。
連結部のうち枠体部203は、複数の端子における複数の配線板とは反対側の部分と、タイバー201,202における複数の端子から離隔する部分とを連結し、複数の配線板と複数の端子を囲むように形成されている。
すなわち、本実施形態のリードフレーム200は、半導体装置10を構成する、複数の配線板(電源配線板24、グランド配線板25,26,27、出力配線板28,29,30、ゲート配線板81〜86)と、複数の端子(電源端子(リード)31,32,33、出力端子(リード)34,35,36、グランド端子(リード)37,38,39、ゲート端子61〜66)として用いられる。
次に、リードフレーム200を用いて、半導体装置10を製造する方法の一例について説明する。
半導体装置10を製造する際には、はじめに、上記構成のリードフレーム200を用意する(フレーム準備工程)。
搭載工程においては、半田等のように通電性を有する導電性接着剤を介して半導体素子91〜96の下面を、電源配線板24の3つの幅広部24Bの第一主面24a及び出力配線板28,29,30の3つの幅広部28B,29B,30Bの第一主面28a,29a,30aに接合する。これにより、半導体素子91〜96が、電源配線板24及び出力配線板28,29,30に固定されると共に電気接続される。
また、封止工程において前述したサポートピン300を用いた場合、封止工程後の状態では、例えば、図11に示すように、封止樹脂50に、前述したサポートピン300によるピン穴52,53が形成されている。
この切断工程を実施することで、電源端子31,32,33、出力端子34,35,36、グランド端子37,38,39及びゲート端子61〜66は互いに電気的に分離されることになる。
20 装置本体
21,22,23 装置単位
24 電源配線板
25,26,27 グランド配線板
28,29,30 出力配線板
31,32,33 電源端子
34,35,36 出力端子
37,38,39 グランド端子
41,42,43 回路ユニット
50 封止樹脂
51 貫通孔
52,53 ピン穴
61,62,63,64,65,66 ゲート端子
71,73,75 第一電流経路
72,74,76 第二電流経路
81,82,83,84,85,86 ゲート配線板
91,92,93,94,95,96 半導体素子
101,102,103,104,105,106,107,108,109,110,111,112 接続子
121,122,123,124,125,126 コンデンサ
150 放熱部材
160 回路基板
200 リードフレーム
201,202 タイバー
203 枠体部
211,212 押付位置
Claims (14)
- 互いに間隔を空けて配された複数の配線板と、
前記配線板の第一主面に配されて、前記配線板に電気接続される半導体素子と、
前記配線板に電気接続される端子と、
前記配線板の第二主面が露出するように、前記配線板、前記半導体素子を封止する樹脂と、
を備え、
前記配線板には、電源配線板と、グランド配線板と、出力配線板と、があり、
前記電源配線板は、直線方向に連続する幅狭部と幅広部を有し、
前記電源配線板の幅広部に前記半導体素子が配され、
前記樹脂は、前記電源配線板の前記幅狭部と前記幅広部との境界部分と、前記出力配線板の前記幅狭部と前記幅広部との境界部分とにピン穴を有する、
ことを特徴とする半導体装置。 - 前記複数の配線板と前記端子が一体に形成されたことを特徴とする請求項1に記載の半導体装置。
- 前記電源配線板は、前記幅狭部及び前記幅広部を複数有することを特徴とする請求項1に記載の半導体装置。
- 前記電源配線板の幅広部の第一主面に配された半導体素子と、前記出力配線板の幅狭部とが接続子で接続されている請求項1又は3に記載の半導体装置。
- 前記出力配線板は、前記直線方向に連続する幅狭部と幅広部を有し、
前記出力配線板の幅広部に前記半導体素子が配され、
前記電源配線板の幅狭部は、前記出力配線板の幅広部に向かい合うように配され、
前記電源配線板の幅広部は、前記出力配線板の幅狭部に向かい合うように配されることを特徴とする請求項1、3、及び4のいずれか1項に記載の半導体装置。 - 前記電源配線板の複数の前記幅広部のそれぞれに配された半導体素子は前記直線方向に間隔を空けて配列されて第一素子群を構成し、
複数の前記出力配線板の前記幅広部のそれぞれに配された半導体素子は前記直線方向に間隔を空けて配列されて第二素子群を構成し、
前記第二素子群を構成する前記半導体素子の中心が、前記直線方向において前記第一素子群を構成する2つの前記半導体素子の中心間に位置していることを特徴とする請求項5に記載の半導体装置。 - 前記出力配線板の幅広部の第一主面に配された半導体素子と、前記グランド配線板とが接続子で接続されたことを特徴とする請求項5又は6に記載の半導体装置。
- 前記配線板には、ゲート配線板があり、
前記端子には、前記電源配線板に接続された電源端子と、前記グランド配線板に接続されたグランド端子と、前記出力配線板に接続された出力端子と、前記ゲート配線板に接続されたゲート端子と、があり、
前記電源端子、前記出力端子及び前記グランド端子の幅は、前記ゲート端子の幅よりも大きいことを特徴とする請求項1、及び3から7のいずれか1項に記載の半導体装置。 - 前記配線板には、電源配線板と、グランド配線板と、出力配線板と、があり、
前記出力配線板は、直線方向に連続する幅狭部と幅広部を有し、
前記出力配線板の幅広部に前記半導体素子が配されることを特徴とする請求項1から8のいずれか1項に記載の半導体装置。 - 前記樹脂に前記配線板の厚み方向に貫通する貫通孔が形成され、
前記貫通孔は、前記樹脂における前記直線方向の両端に形成されていることを特徴とする請求項1、及び3から9のいずれか1項に記載の半導体装置。 - 前記樹脂に前記配線板の厚み方向に貫通する貫通孔が形成されていることを特徴とする請求項1から10のいずれか1項に記載の半導体装置。
- 前記配線板から延びる前記端子の先端部は、前記配線板の第一主面から突出するように前記配線板の厚み方向に延びていることを特徴とする請求項1から11のいずれか1項に記載の半導体装置。
- 前記複数の配線板のうち互いに隣り合う配線板は、コンデンサによって接続されていることを特徴とする請求項1から12のいずれか1項に記載の半導体装置。
- 複数の配線板と複数の端子とが一体に形成され、前記複数の端子が連結部によって連結されたリードフレームを準備するフレーム準備工程と、
前記リードフレームの第一主面に半導体素子を固定する搭載工程と、
前記半導体素子と、前記配線板のうち前記半導体素子が設けられていない部分とを電気接続する接続工程と、
前記リードフレームの第二主面が露出するように、前記リードフレーム及び前記半導体素子を樹脂で封止する封止工程と、
前記リードフレームの連結部を切り落とす切断工程と、
を備え、
前記配線板には、電源配線板と、グランド配線板と、出力配線板と、があり、
前記電源配線板は、直線方向に連続する幅狭部と幅広部を有し、
前記出力配線板は、前記直線方向に連続する幅狭部と幅広部を有し、
前記封止工程において、サポートピンを、前記電源配線板の前記幅狭部と前記幅広部との境界部分と、前記出力配線板の前記幅狭部と前記幅広部との境界部分とに押し付ける、
ことを特徴とする半導体装置の製造方法。
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